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1. 发明专利

JPH02298073A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH02298073A
公开(公告)日：1990-12-10
申请号：JP11926889
申请日：1989-05-12
申请人： NIPPON SOKEN , NIPPON DENSO CO
发明人： TSURUTA KAZUHIRO , KATADA MITSUTAKA , FUJINO SEIJI , YAMAOKA MASAMI
IPC分类号： H01L29/73 , H01L21/331 , H01L29/06 , H01L29/732 , H01L29/739 , H01L29/78 , H01L29/861
摘要： PURPOSE:To acquire a high breakdown strength and to realize a large diameter of a substrate by making a P-N junction side on a first semiconductor substrate flat at a peripheral section thereof forming a mesa structure with a specified incline and by coating the incline with an insulator layer which consists of a thermal oxidation film. CONSTITUTION:At first, a mirror surface 1a of a first semiconductor substrate 1 of high resistance N -type is provided with a mesa groove 3 which is formed crosswise having an incline 3a and opens to a substrate edge. The semiconductor substrate and a low resistance second semiconductor substrate 2 of N -type are fully cleaned to remove a spontaneous oxide film thereon. Then, an amount of water on the surface is controlled, and mirrors 1a, 2a are tightly bonded each other and dried. The substrates 1, 2 are directly bonded at a bonding side through heat treatment to acquire a completely integrated substrate 5. The substrate 5 is thermally treated to protect the incline 3a of the mesa groove 3 by an oxide film 6. The substrate surface 1b is lap-polished, a P-N junction surface 7 and a P-layer are formed, a mask is applied, an N -layer is formed, and an aluminum wiring is applied to a specified position of the element surface. Dicing is carried out at a position of the mesa groove 3.

2. 发明专利

JPH02178965A INSULATED ISOLATION TYPE FIELD-EFFECT SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH02178965A
公开(公告)日：1990-07-11
申请号：JP33164488
申请日：1988-12-29
申请人： NIPPON DENSO CO , NIPPON SOKEN
发明人： SAKAKIBARA NOBUYOSHI , FUJINO SEIJI , MURAMOTO HIDETOSHI , HATTORI TADASHI , YAMAOKA MASAMI
IPC分类号： H01L27/00 , H01L27/10 , H01L27/12 , H01L29/786
摘要： PURPOSE:To stabilize the electrical characteristics of an SOI element, and to prevent a back channel by applying bias voltage to a conductor electrically conducted with a channel region and electrically isolated from source-drain regions. CONSTITUTION:A conductor 21, which is arranged just under a channel region 33 while being formed onto at least an insulator 20 and buried into the insulator 20, a top face of which in integral combination is formed to a plane shape and which is conducted electrically with the channel region 33 and isolated electrically from source-drain regions 32a, 32b, is shaped. Consequently, the conductor 21 is formed just under the channel region 33 while being electrically conducted with the channel region 33, thus applying bias voltage to the conductor 21 even when any potential is applied to a semiconductor substrate 10. Accordingly, the electrical characteristics of an SOI(Silicon on Insulator) element are stabilized, and the generation of a back channel can be prevented.

3. 发明专利

JPH0296350A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0296350A
公开(公告)日：1990-04-09
申请号：JP24873788
申请日：1988-09-30
申请人： NIPPON SOKEN , NIPPON DENSO CO
发明人： TSURUTA KAZUHIRO , FUJINO SEIJI , KATADA MITSUTAKA , HATTORI TADASHI , YAMAOKA MASAMI
IPC分类号： H01L21/762 , H01L21/76 , H01L27/088 , H01L27/144
摘要： PURPOSE:To form vertical power elements and form an element isolation region in a little time in such a way that its region has high breakdown strength and does not diffuse crosswise very much by forming an insulation isolating region which is isolated by an oxide film in the first semiconductor substrate. CONSTITUTION:An recessed part 2 is formed on the mirror side of the first semiconductor substrate 1 on which one side face of its substrate is polished into a mirror and along the most part of an interface between the recessed part 2 and the mirror 1a, each trench part 3 which is deeper than the recessed part 2 is formed. The mirror of the second semiconductor substrate 5 where one side face of it is polished into the mirror is joined directly with the mirror of the first semiconductor substrate 1. A space which is formed on a joined substrate 10 between the recessed part 2 of the first semiconductor substrate 1 and the mirror of the second semiconductor substrate 5 is buried by an oxide film 11; besides, the oxide film 11 is formed at side faces of each trench part of the semiconductor substrate 1 to allow the trench part to be exposed to the outside from the other side of the first semiconductor substrate 1. Consequently, vertical power elements are formed at regions other than the element isolating region and then, an insulating isolating region is thus formed by the oxide film 11. Its region is formed in a short time in such a manner that it does not diffuse crosswise very much and has high breakdown strength.

4. 发明专利

JPH0246722A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0246722A
公开(公告)日：1990-02-16
申请号：JP19844288
申请日：1988-08-09
申请人： NIPPON SOKEN , NIPPON DENSO CO
发明人： KATADA MITSUTAKA , FUJINO SEIJI , TSURUTA KAZUHIRO , HATTORI TADASHI , YAMAOKA MASAMI
IPC分类号： H01L21/20
摘要： PURPOSE:To lessen the resistance of a junction interface and to improve the uniformity of a junction by a method wherein the polished joint surfaces of two sheets of semiconductor substrates are turned into a hydrophilic property, water molecules of a thickness of a degree identical with the degrees of surface roughness of the joint surfaces are adhered on the joint surfaces, the fellow joint surfaces are joined. with each other to use as a substrate, the water molecules are removed by a vacuum drying and a heat treatment is performed on the substrate. CONSTITUTION:An oxide film of a controlled film thickness is formed on the surfaces of polished joint surfaces 13 and 14. Silanol groups are each formed on the uppermost surfaces of the surfaces 13 and 14 by the formation of this oxide film and the surfaces 13 and 14 are turned into a hydrophilic property. By rubbing the upper part of the surface 13 and the surface, which opposes to the surface 14, of the surface 13 with an insulative material, charges different from each other are each stored on the surfaces 13 and 14. After that, a spin drying is performed to control the amount of water molecules to adhere on the surfaces 13 and 14 and the water molecules are adhered in a thickness of water molecules of a degree identical with the degrees of surface roughness of the surfaces 13 and 14. Then, the fellow surfaces 13 and 14 are joined with each other to use as a substrate 20. The substrate is dried by standing in a vacuum atmosphere. After that, a heat treatment is performed on the substrate at a temperature of 1100 deg.C or higher in an inert gas-containing atmosphere.

5. 发明专利

JPH01295463A THIN FILM SEMICONDUCTOR ELEMENT AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH01295463A
公开(公告)日：1989-11-29
申请号：JP12632388
申请日：1988-05-24
申请人： NIPPON SOKEN , NIPPON DENSO CO
发明人： MURAMOTO HIDETOSHI , SAKAKIBARA NOBUYOSHI , FUJINO SEIJI , HATTORI TADASHI , YAMAOKA MASAMI
IPC分类号： H01L29/78 , H01L21/20 , H01L21/31 , H01L21/316 , H01L21/336 , H01L21/762 , H01L27/12 , H01L29/786
摘要： PURPOSE:To improve step coverage property, by covering a semiconductor island having a right-angle edge part with a dummy insulating film having a smoothly curved surface. CONSTITUTION:A semiconductor film 10 which is formed on an insulating substrate 1 is divided by anisotropic etching to form a plurality of semiconductor islands 2. A dummy insulating film 3 having a smoothly curved surface is formed so as to cover at least a plurality of the semiconductor islands 2. Of the dummy insulating film 3, a part covering a functional-element forming surface 2a on the upper surface of each semiconductor island is removed by isotropic etching. Thereafter, a film layer 4 constituting functional elements is overlapped and formed on the upper part. Even if the film layers are overlapped and formed on the exposed element-forming surface 2a and dummy insulating film 3, there is no problem such as the local thinning of the film layers, and the step coverage property is improved.

6. 发明专利

JPH01289109A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH01289109A
公开(公告)日：1989-11-21
申请号：JP11895388
申请日：1988-05-16
申请人： NIPPON SOKEN , NIPPON DENSO CO
发明人： KATADA MITSUTAKA , FUJINO SEIJI , MURAMOTO HIDETOSHI , HATTORI TADASHI , YAMAOKA MASAMI
IPC分类号： H01L21/20
摘要： PURPOSE:To display excellent interfacial characteristics subject to less transition and defects by a method wherein, after forming an amorphous layer on the mirror surface part of a semiconductor substrate, two substrates are bonded together through the intermediary of the amorphous layer to solid-deposit the amorphous layer. CONSTITUTION:The ground surface of a mirror-ground low concentration N substrate 20 is implanted with Si ion to form an amorphous layer 21 by making the crystal surface amorphous. Both of the substrate 20 and another mirror- ground high concentration N substrate 22 are subjected to the surface cleaning process a and hydrophilic process (b). First, the formation surface of a layer 21 on the substrate 20 is brought into contact with the mirror-ground surface of the substrate 22 to form a contact substrate for heat treatment (exceeding 600 deg.C). Through these procedures, the solid epitaxial deposition is performed conforming to the crystalline structure of the substrate 22 to form a boundary layer 30. Secondly, the layer 20 is lapped or mirror-ground down to proper thickness to form a junction substrate 23. Finally, a high concentration P layer 27 is formed and then electrodes 28, 29 are formed to form a diode 24 in high breakdown strength.

7. 发明专利

DE3687952T2 未知
公开(公告)号：DE3687952T2
公开(公告)日：1993-09-30
申请号：DE3687952
申请日：1986-11-28
申请人： NIPPON DENSO CO
发明人： TSUZUKI YUKIO , YAMAOKA MASAMI
IPC分类号： H01L23/58 , H01L21/822 , H01L23/34 , H01L27/02 , H01L27/04 , H01L29/78
摘要： A semiconductor substrate (11) has a power region (12) and a control region (13). The control region (13) is located in the center portion of the substrate (11), and the power region (12) surrounds the control region (13) and is separated therefrom. A vertical type, MOS transistor (22), i.e., an active semiconductor element, is formed on the power region (12). An insulation film (24) is formed on part of the control region (13). A polycrystalline silicon diode (25), which functions as a heat-sensitive element, is formed on the insultation film (24). A control section comprising a lateral type, MOS transistor (26) is formed on the control region (13). The lateral type, MOS transistor (26) is connected to receive a signal from the polycrystalline silicon diode. (25). Further, a polycrystalline silicon resistor (271, which determines a circuit constant, is formed on the insultation film (24). The MOS transistor (26) protects the active semiconductor element in response to a signal suppled from said heat-sensitive element and show ing that the temperature of said semi-conductor substrate has risen above a predetermined value.

8. 发明专利

DE3788500D1 未知
公开(公告)号：DE3788500D1
公开(公告)日：1994-01-27
申请号：DE3788500
申请日：1987-10-29
申请人： NIPPON DENSO CO
发明人： KATO NAOHITO , MIYASE YOSHIYUKI , MAKINO TOMOATSU , YAMADA KAZUHIRO , YAMAOKA MASAMI , MATSUI TAKESHI , YAMAMOTO MASAHIRO , ISHIDA YOSHIKI , NOMURA TOHRU
IPC分类号： H01L29/72 , H01L29/06 , H01L29/417 , H01L29/52
摘要： Base regions (32, 33) of first and second stage transistors are formed in semiconductor substrate (31) consisting of low and high resistivity collector layers (311, 312), and emitter regions (34, 35) are formed in the respective base regions. The emitter region of the second stage transistor has an interdigital structure with a plurality of finger portions (37 to 44), and emitter surface electrode (47) is formed on the emitter region of the second stage transistor. The second stage transistor emitter surface electrode has extending portion (471) at a position spaced apart from a transistor operation region where the finger portions are formed. Emitter connection electrode (48) is formed on the extending portion, and a lead is connected by soldering or the like to the emitter connection electrode. In a portion of the emitter surface electrode extending from the emitter connection electrode to the transistor operation region, slits (472, 473) are formed such that they are bypassed by emitter current so that the lead resistance from each finger portion to the emitter connection electrode is substantially uniform.

9. 发明专利

DE3276091D1 SEMICONDUCTOR DEVICE INCLUDING OVERVOLTAGE PROTECTION DIODE 未知
公开(公告)号：DE3276091D1
公开(公告)日：1987-05-21
申请号：DE3276091
申请日：1982-12-21
申请人： NIPPON DENSO CO
发明人： YAMAOKA MASAMI , TOYOSHIMA SHOJI
IPC分类号： H01L27/02 , H01L29/739 , H01L29/866
摘要： A semiconductor device includes a diode element for protecting a transistor against an overvoltage. A first region (11) of p-type conductivity is formed on an upper surface of an n-type semiconductor substrate (10) in which base and emitter regions of the transistor are formed. A second region (12) of n -type conductivity whose impurity concentration is higher than that of the n-type semiconductor substrate is formed on its upper surface to be spaced apart from the first region (11). An insulating film (13) is formed to cover the upper surface of the semiconductor substrate (10). Furthermore, a conductive film (14) is formed to partially overlap the first and second regions (11, 12) through the insulating film (13). The first region (11) serves as an anode, the second region (12) serves as a cathode, and the conductive film (14) serves as a gate electrode; thus an overvoltage protection diode is obtained.

10. 发明专利

DE68908520T2 未知
公开(公告)号：DE68908520T2
公开(公告)日：1994-02-24
申请号：DE68908520
申请日：1989-09-14
申请人： NIPPON DENSO CO
发明人： KONDO ICHIHARU , YONEYAMA TAKAO , YAMAOKA MASAMI , TAKENAKA OSAMU
IPC分类号： C30B28/12 , C23C14/02 , C23C14/14 , C23C14/16 , C23C14/18 , C23C14/34 , C30B29/02 , H01L21/28 , H01L21/285 , H01L29/45 , H01L29/40 , H01L29/54

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