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1. 发明专利

CA2130806A1 SEMICONDUCTOR DEVICE 未知
公开(公告)号：CA2130806A1
公开(公告)日：1994-06-26
申请号：CA2130806
申请日：1993-12-24
申请人： NIPPON DENSO CO
发明人： IIDA MAKIO , ISHIHARA OSAMU , SAKAKIBARA TOSHIO , SUGISAKA TAKAYUKI , MIURA SHOJI
IPC分类号： H01L21/762 , H01L29/06 , H01L29/10 , H01L29/73 , H01L29/732 , H01L23/62 , H01L29/70
摘要： It is an object of the present invention to provide a semiconductor device which can compatibly achieve the improvement of the withstand voltage and the integration degree. PN junction between a buried collector region 3 and a collector withstand voltage region 4 is subjected to reverse bias, and a depletion layer in the PN junction reaches a side dielectric isolation region 9a which dielectrically isolates the side of the collector withstand voltage region 4. A circumferential semiconductor region 14 which is in adjacency to the collector withstand voltage with the side dielectric isolation region 9a therebetween has an electric potential that is approximate to that at a base region 5 rather than that at the buried collector region 3. As a result, the depletion layer is subjected to the effect of low electric potential from both the base region 5 and the circumferential semiconductor region 14. This mitigates electrostatic focusing in the vicinity of the corner parts between the sides of the base region 5 and the bottom thereof, restraining the avalanche breakdown there and improving the withstand voltage there.

2. 发明专利

CA2130806C SEMICONDUCTOR DEVICE 未知
公开(公告)号：CA2130806C
公开(公告)日：2002-02-19
申请号：CA2130806
申请日：1993-12-24
申请人： NIPPON DENSO CO
发明人： IIDA MAKIO , MIURA SHOJI , SUGISAKA TAKAYUKI , SAKAKIBARA TOSHIO , ISHIHARA OSAMU
IPC分类号： H01L21/762 , H01L29/06 , H01L29/10 , H01L29/73 , H01L29/732 , H01L23/62 , H01L29/70
摘要： It is an object of the present invention to provide a semiconductor device which can compatibly achieve the improvement of the withstand voltage and the integration degree. PN junction between a buried collector region 3 and a collector withstand voltage region 4 is subjected to reverse bias, and a depletion layer in the PN junction reaches a side dielectric isolation region 9a which dielectrically isolates the side of the collector withstand voltage region 4. A circumferential semiconductor region 14 which is in adjacency to the collector withstand voltage with the side dielectric isolation region 9a therebetween has an electric potential that is approximate to that at a base region 5 rather than that at the buried collector region 3. As a result, the depletion layer is subjected to the effect of low electric potential from both the base region 5 and the circumferential semiconductor region 14. This mitigates electrostatic focusing in the vicinity of the corner parts between the sides of the base region 5 and the bottom thereof, restraining the avalanche breakdown there and improving the withstand voltage there.

3. 发明公开

EP0628996A4 SEMICONDUCTOR DEVICE. 有权转让
标题翻译： HALBLEITER VORRICHTUNG。
公开(公告)号：EP0628996A4
公开(公告)日：1995-08-30
申请号：EP94903045
申请日：1993-12-24
申请人： NIPPON DENSO CO
发明人： MIURA SHOJI , IIDA MAKIO , SUGISAKA TAKAYUKI , SAKAKIBARA TOSHIO , ISHIHARA OSAMU
IPC分类号： H01L21/762 , H01L29/06 , H01L29/10 , H01L29/73 , H01L29/732 , H01L21/76
CPC分类号： H01L29/7317 , H01L21/76264 , H01L21/76275 , H01L21/76286 , H01L29/0615 , H01L29/1075 , H01L29/1087 , H01L29/7322 , H01L2924/0002 , H01L2924/00
摘要： Both breakdown strength and integration degree of the device are enhanced. The PN junction of the buried collector region (3) and the region (4) for increasing the collector breakdown strength is reversely biased. The depletion layer reaches the side isolation region (9a) for isolating the collector breakdown strength increasing region (4) at their sides. The surrounding semiconductor region (14) adjacent to the region (4) through the isolation region (9a) has a potential which is more approximate to the base area (5) than to the buried collector region (3). As a result, the depletion layer is affected by the low potentials from both sides of the base region (5) and the circumferential semiconductor region (14). The field concentration at and near the corner sections between the side and bottom of the base region (5) are relaxed. Avalanche breakdown at these sections is suppressed, and the breakdown strength is thus enhanced.
摘要翻译：提高了器件的击穿强度和集成度。掩埋集电极区域（3）和区域（4）的PN结用于提高集电极击穿强度被反向偏置。耗尽层到达侧面隔离区域（9a），用于隔离其两侧的集电极击穿强度增加区域（4）。通过隔离区（9a）与区域（4）相邻的周围半导体区域（14）的电位比埋藏集电极区域（3）更接近于基极区域（5）。结果，耗尽层受到基极区域（5）和周向半导体区域（14）两侧的低电位的影响。在基部区域（5）的侧面和底部之间的拐角部分处和其附近的场浓度被放宽。抑制这些部位的雪崩击穿，从而提高击穿强度。

4. 发明专利

JPH06291260A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH06291260A
公开(公告)日：1994-10-18
申请号：JP7800993
申请日：1993-04-05
申请人： NIPPON DENSO CO
发明人： OKAWA MAKOTO , IIDA MAKIO , MIURA SHOJI , ISHIHARA OSAMU , KAMIYA TETSUAKI
IPC分类号： H01L21/265 , H01L21/268 , H01L21/28 , H01L21/822 , H01L27/04
摘要： PURPOSE:To provide a semiconductor device capable of suppressing variations of the absorption rate of laser beam energy in a thin film resistor and readily regulating a resistance value of the thin film resistor by laser beams. CONSTITUTION:A substrate 7 formed with an embedded SiO2 layer 6 by heat- oxidating a Si substrate is attached to and bonded to an N- type substrate 10 forming a high density N diffused layer 9 by diffusing Sb on the surface to grind a substrate 10. Phosphorus ions are ion-implanted and heat-diffused from the grinding surface to form a higher density N diffusion part 8 than the N diffused layer 9. Next, a BPSG film 4 is formed on the surface of the substrate 10 to form a thin film resistor 3 and a TiW film 11 composed of a CrSi film to pattern. Next, an Al wire 2 containing Si of 1% is formed. Further, an excessive TiW thin film 11 is etched and removed to form a silicon oxide film 12 and a silicon nitride film 13 being a protection film 1. Lastly, a wiring window opening is performed in the protection film 1.

5. 发明专利

JPH05198758A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH05198758A
公开(公告)日：1993-08-06
申请号：JP24045392
申请日：1992-09-09
申请人： NIPPON DENSO CO
发明人： SAKAKIBARA TOSHIO , FUJIMOTO YUTAKA , NAKAYAMA YOSHIAKI , ISHIHARA OSAMU
IPC分类号： H01L21/762 , H01L21/76 , H01L21/8234 , H01L21/8236 , H01L27/08 , H01L27/088 , H01L29/78
摘要： PURPOSE:To obtain a sufficient output current in a compact shape without erroneous operation at the time of driving an inductive load. CONSTITUTION:An insulating layer 4 is formed in a box shape opened on one surface of a semiconductor substrate 3 in the substrate 3, lateral double diffused MOS field-effect transistors 2A, 2B are formed in a semiconductor layer surrounded by the box-shaped insulating layer, and longitudinal double diffused MOS field-effect transistors 1A, 1B are formed in the semiconductor layer out of the box-shaped insulating layer. Even if potentials of terminals of outputs 1, 2 become lower than a ground potential due to an electromotive force at the time of driving an inductive load, since an element isolation is conducted by the insulating layer, a parasitic transistor is not generated, and a problem of an erroneous operation due to conduction of the transistor does not occur. Since the ON resistance of the longitudinal double diffused MOS field-effect transistor is small, even if its forming area is reduced, a sufficient output current is obtained.

6. 发明专利

JPS5265662A METHOD AND DEVICE FOR DIFFUSION TO SEMICONDUCTOR SUBSTRATE BY HIGH FRE QUENCY INDUCTION HEATING 失效
公开(公告)号：JPS5265662A
公开(公告)日：1977-05-31
申请号：JP14178875
申请日：1975-11-26
申请人： NIPPON DENSO CO
发明人： YAMAWAKI MASAO , AOKI KATSUO , OKA YOSHIO , SUZUKI TAKAO , AMANO MASAHIKO , OZAKI HIDEKI , ISHIHARA OSAMU
IPC分类号： C30B31/06 , B65G49/07 , C30B31/10 , C30B31/12 , H01L21/00 , H01L21/205 , H01L21/22 , H01L21/677
摘要： PURPOSE:To obtain a means of performing thermal diffusion operations which provide high uniformity and volume productivity, by high-frequency-heating the susceptors moving in a reaction tube and obtaining the same heat hysteresis in the wafers on the susceptors.

7. 发明专利

JPH06224312A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH06224312A
公开(公告)日：1994-08-12
申请号：JP919493
申请日：1993-01-22
申请人： NIPPON DENSO CO
发明人： ISOBE YOSHIHIKO , IIDA MAKIO , ISHIHARA OSAMU
IPC分类号： H01L21/768 , H01L21/822 , H01L27/04 , H01L21/90
摘要： PURPOSE:To provide a semiconductor device and its manufacturing method characterized by passivating an aluminum film with a P-SiN film and a PSG film, capable of suppressing void generation in case of high-temperature annealing. CONSTITUTION:When an aluminum film 4, a PSG film 6, and a P-SiN film 7 are laminated on a single crystal silicon substrate 1 interposing a base silicon oxide film 3, void generation in the aluminum film 4 can be prevented, or can be greatly decreased by applying a room temperature residual stress of -1 (compressive) to +2 (tensile) X100 mega pascal to a double-layer passivation film composed of the PSG film 6 and the silicon nitride film 7, even if high- temperature treatment such as annealing, etc., is performed.

8. 发明专利

JPH06196477A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH06196477A
公开(公告)日：1994-07-15
申请号：JP34587492
申请日：1992-12-25
申请人： NIPPON DENSO CO
发明人： ISOBE YOSHIHIKO , SUZUKI MIKIMASA , ITO SHUICHI , IIDA MAKIO , ISHIHARA OSAMU
IPC分类号： H01L21/316 , H01L21/318 , H01L21/822 , H01L27/04
摘要： PURPOSE:To obtain a void-free aluminum film by a method wherein a silicon nitride film is formed through a plasma CVD method on a protecting silicon oxide film provided onto the aluminum film, and the aluminum film is annealed under specific conditions. CONSTITUTION:An opening is provided to the prescribed region of a field oxide film 2, and then a thermal silicon oxide film 3 is formed on the exposed surface of an N capacitor electrode 9. Then, an opening is provided to the field oxide film 2 for the formation of a contact hole, an aluminum film 4 is formed on the thermal silicon oxide film 3, and an aluminum electrode 5 is provided inside the above contact hole. Then, a protecting silicon oxide film 6 is formed thereon through a CVD method, and furthermore a P-SiN film 7 is provided thereon through an RF plasma CVD method. Thereafter, a semiconductor device of this constitution is annealed for 5 to 60 minutes at a temperature range of 440 to 500 deg.C to recover its characteristics deteriorated by a plasma CVD process. By this setup, voids can be restrained from being produced in an aluminum film even if it is annealed at a high temperature.

9. 发明专利

JPH06244239A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH06244239A
公开(公告)日：1994-09-02
申请号：JP3060693
申请日：1993-02-19
申请人： NIPPON DENSO CO
发明人： ISOBE YOSHIHIKO , OKAWA MAKOTO , IIDA MAKIO , ISHIHARA OSAMU
IPC分类号： H01L21/60 , H01L29/41 , H01L29/44
摘要： PURPOSE:To provide the SOI semiconductor device capable of impressing a semiconductor substrate with a potential from an element side surface. CONSTITUTION:A semiconductor layer 3 is insulated from a semiconductor substrate 1 by an intermediate insulating film 2. A shortcircuit conductor 10 laid down on the side of a recession 9 reaching the semiconductor 1 makes a shortcircuit of the semiconductor substrate 1 and an ambient region 3b thereby impressing the semiconductor substrate 1 with the same potential as that of the ambient region 3. At this time, the ambient region 3b is impressed with a potential from a wiring substrate 8 e.g. through a bump 7 similar to an element formation region. Accordingly, the semiconductor substrate l can be impressed with a specific potential even if the wiring substrate 8 is connected to a chip through the intermediary of the bump 7 by such a method as flip chip, TAB arc.

10. 发明专利

JPH06163816A DESIGN OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH06163816A
公开(公告)日：1994-06-10
申请号：JP33547592
申请日：1992-11-20
申请人： NIPPON DENSO CO
发明人： SUZUI KEISUKE , IIDA MAKIO , ISHIHARA OSAMU
IPC分类号： H01L21/22 , G06F17/50 , H01L21/822 , H01L27/04 , G06F15/60
摘要： PURPOSE:To gurantee the breakdown strength of a circuit element, which can not be directly inspected, with a margin and to contrive to improve the reliability of a semiconductor device by a method wherein the constitution of a low-breakdown strength circuit is made to have an antiapated value of 6 times, 6sigma, of the standard deviation (sigma), which is obtainable by regarding the data on the irregularity in the manufacture of the device to be normal distribution. CONSTITUTION:The longer the length between a diffused region and a diffused region, that is, the length between diffusion windows, is, the higher a breakdown voltage to the length between the diffused regions, that is, the length between the diffusion windows, becomes, but the voltage is not increased to that higher than a voltage which is decided by an avalanche phenomenon. There, when a pattern of such a semiconductor device as a low-breakdown strength element is specified by a high-breakdown strength element, such as a semiconductor device as its interior is a voltage stabilizer, is designed, a high-breakdown strength setpoint and a low-breakdown strength setpoint of a targeted breakdown strength are respectively set like (a) and (b), for example, and the lengths between diffusion windows to correspond to the target are decided like (c) and (d) allowing safety on the basis of the standard deviation sigmaof the irregularity in the manufacture of the device, which is previously held found empirically. At that time, an amount to allow the safety in a design value is set at 4sigma for the high-breakdown strength system and is set at 6sigma for the low-breakdown strength system.

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