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1. 发明公开

EP0562127A4 METHOD FOR FABRICATION OF SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件制造方法
公开(公告)号：EP0562127A4
公开(公告)日：1994-11-23
申请号：EP93908767
申请日：1992-10-12
申请人： NIPPON DENSO CO
发明人： MIURA SHOJI , SUGISAKA TAKAYUKI , KOMURA ATSUSHI , SAKAKIBARA TOSHIO
IPC分类号： H01L21/762 , H01L21/763 , H01L21/768 , H01L21/76
CPC分类号： H01L21/763 , H01L21/76264 , H01L21/76275 , H01L21/76281 , H01L21/76286 , H01L21/76802 , Y10S148/05 , Y10S148/135 , Y10S438/977

2. 发明公开

EP0628996A4 SEMICONDUCTOR DEVICE. 有权转让
标题翻译： HALBLEITER VORRICHTUNG。
公开(公告)号：EP0628996A4
公开(公告)日：1995-08-30
申请号：EP94903045
申请日：1993-12-24
申请人： NIPPON DENSO CO
发明人： MIURA SHOJI , IIDA MAKIO , SUGISAKA TAKAYUKI , SAKAKIBARA TOSHIO , ISHIHARA OSAMU
IPC分类号： H01L21/762 , H01L29/06 , H01L29/10 , H01L29/73 , H01L29/732 , H01L21/76
CPC分类号： H01L29/7317 , H01L21/76264 , H01L21/76275 , H01L21/76286 , H01L29/0615 , H01L29/1075 , H01L29/1087 , H01L29/7322 , H01L2924/0002 , H01L2924/00
摘要： Both breakdown strength and integration degree of the device are enhanced. The PN junction of the buried collector region (3) and the region (4) for increasing the collector breakdown strength is reversely biased. The depletion layer reaches the side isolation region (9a) for isolating the collector breakdown strength increasing region (4) at their sides. The surrounding semiconductor region (14) adjacent to the region (4) through the isolation region (9a) has a potential which is more approximate to the base area (5) than to the buried collector region (3). As a result, the depletion layer is affected by the low potentials from both sides of the base region (5) and the circumferential semiconductor region (14). The field concentration at and near the corner sections between the side and bottom of the base region (5) are relaxed. Avalanche breakdown at these sections is suppressed, and the breakdown strength is thus enhanced.
摘要翻译：提高了器件的击穿强度和集成度。掩埋集电极区域（3）和区域（4）的PN结用于提高集电极击穿强度被反向偏置。耗尽层到达侧面隔离区域（9a），用于隔离其两侧的集电极击穿强度增加区域（4）。通过隔离区（9a）与区域（4）相邻的周围半导体区域（14）的电位比埋藏集电极区域（3）更接近于基极区域（5）。结果，耗尽层受到基极区域（5）和周向半导体区域（14）两侧的低电位的影响。在基部区域（5）的侧面和底部之间的拐角部分处和其附近的场浓度被放宽。抑制这些部位的雪崩击穿，从而提高击穿强度。

3. 发明专利

DE4441542A1 SOI-semiconductor device manufacturing method 未知
公开(公告)号：DE4441542A1
公开(公告)日：1995-06-01
申请号：DE4441542
申请日：1994-11-22
申请人： NIPPON DENSO CO
发明人： SUGISAKA TAKAYUKI , MIURA SHOJI , SAKAKIBARA TOSHIO
IPC分类号： H01L21/02 , H01L21/76 , H01L21/762 , H01L27/12
摘要： A semiconductor substrate with an outer insulation film is connected with a semiconductor layer used for element forming. An inner insulation layer is arranged between the two. A nitride film (9) is formed as a mask, which is used for channel forming, on a surface of the semiconductor layer. The nitride film which has accumulated on the outer insulation film during the forming step is removed. The nitride film on the semiconductor layer is used as a mask to produce a channel (12) in the semiconductor layer. Filling material is inserted in the channel and a semiconductor island region formed.

4. 发明专利

CA2130806A1 SEMICONDUCTOR DEVICE 未知
公开(公告)号：CA2130806A1
公开(公告)日：1994-06-26
申请号：CA2130806
申请日：1993-12-24
申请人： NIPPON DENSO CO
发明人： IIDA MAKIO , ISHIHARA OSAMU , SAKAKIBARA TOSHIO , SUGISAKA TAKAYUKI , MIURA SHOJI
IPC分类号： H01L21/762 , H01L29/06 , H01L29/10 , H01L29/73 , H01L29/732 , H01L23/62 , H01L29/70
摘要： It is an object of the present invention to provide a semiconductor device which can compatibly achieve the improvement of the withstand voltage and the integration degree. PN junction between a buried collector region 3 and a collector withstand voltage region 4 is subjected to reverse bias, and a depletion layer in the PN junction reaches a side dielectric isolation region 9a which dielectrically isolates the side of the collector withstand voltage region 4. A circumferential semiconductor region 14 which is in adjacency to the collector withstand voltage with the side dielectric isolation region 9a therebetween has an electric potential that is approximate to that at a base region 5 rather than that at the buried collector region 3. As a result, the depletion layer is subjected to the effect of low electric potential from both the base region 5 and the circumferential semiconductor region 14. This mitigates electrostatic focusing in the vicinity of the corner parts between the sides of the base region 5 and the bottom thereof, restraining the avalanche breakdown there and improving the withstand voltage there.

5. 发明专利

CA2130806C SEMICONDUCTOR DEVICE 未知
公开(公告)号：CA2130806C
公开(公告)日：2002-02-19
申请号：CA2130806
申请日：1993-12-24
申请人： NIPPON DENSO CO
发明人： IIDA MAKIO , MIURA SHOJI , SUGISAKA TAKAYUKI , SAKAKIBARA TOSHIO , ISHIHARA OSAMU
IPC分类号： H01L21/762 , H01L29/06 , H01L29/10 , H01L29/73 , H01L29/732 , H01L23/62 , H01L29/70
摘要： It is an object of the present invention to provide a semiconductor device which can compatibly achieve the improvement of the withstand voltage and the integration degree. PN junction between a buried collector region 3 and a collector withstand voltage region 4 is subjected to reverse bias, and a depletion layer in the PN junction reaches a side dielectric isolation region 9a which dielectrically isolates the side of the collector withstand voltage region 4. A circumferential semiconductor region 14 which is in adjacency to the collector withstand voltage with the side dielectric isolation region 9a therebetween has an electric potential that is approximate to that at a base region 5 rather than that at the buried collector region 3. As a result, the depletion layer is subjected to the effect of low electric potential from both the base region 5 and the circumferential semiconductor region 14. This mitigates electrostatic focusing in the vicinity of the corner parts between the sides of the base region 5 and the bottom thereof, restraining the avalanche breakdown there and improving the withstand voltage there.

6. 发明专利

DE3670403D1 未知
公开(公告)号：DE3670403D1
公开(公告)日：1990-05-17
申请号：DE3670403
申请日：1986-07-18
申请人： NIPPON DENSO CO
发明人： FUJII TETSUO , SAKAKIBARA TOSHIO , SAKAKIBARA NOBUYOSHI
IPC分类号： H01L29/788 , H01L29/78

7. 发明专利

JPH06104393A IIL INTEGRATED CIRCUIT 失效
公开(公告)号：JPH06104393A
公开(公告)日：1994-04-15
申请号：JP27526092
申请日：1992-09-18
申请人： NIPPON DENSO CO
发明人： SUGISAKA TAKAYOSHI , MIURA SHOJI , SAKAKIBARA TOSHIO
IPC分类号： H01L27/082 , H01L21/8226
摘要： PURPOSE:To improve the fan-out, that is, performance indexes, of IIL unit elements by a method wherein the IIL unit elements are made to isolate from their adjacent elements and a semiconductor substrate by insulating layers in each unit element. CONSTITUTION:Vertical first transistor 3, 5 and 6 are used as switching transistor and lateral second transistors 4, 3 and 5 are used as current injection sources. A base 5 of a first transistor and a collector of a second transistor are used in common and an emitter 3 of the first transistor and a base of the second transistor are used in common. Such an IIL is used as a unit element and in an IIL integrated circuit formed by integrating the unit elements on a semiconductor substrate 1, the IIL unit elements are made to isolate from their adjacent elements and the substrate 1 by insulating layers 21 and 22 in each unit element. Thereby, an inverse beta of the first transistor can be increased. Accordingly, the fan-outs of the IIL unit elements can be increased.

8. 发明专利

JPH0574949B2 失效
公开(公告)号：JPH0574949B2
公开(公告)日：1993-10-19
申请号：JP21575885
申请日：1985-09-28
申请人： NIPPON DENSO CO
发明人： FUJII TETSUO , SAKAKIBARA TOSHIO , SAKAKIBARA NOBUYOSHI
IPC分类号： H01L21/8247 , H01L29/78 , H01L29/788 , H01L29/792

9. 发明专利

JPH0571147B2 失效
公开(公告)号：JPH0571147B2
公开(公告)日：1993-10-06
申请号：JP23970085
申请日：1985-10-25
申请人： NIPPON DENSO CO
发明人： FUJII TETSUO , SAKAKIBARA TOSHIO , SAKAKIBARA NOBUYOSHI , IWASAKI YUTAKA
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792

10. 发明专利

JPH05243502A 失效
公开(公告)号：JPH05243502A
公开(公告)日：1993-09-21
申请号：JP7907692
申请日：1992-02-27
申请人： NIPPON DENSO CO
发明人： IIDA MAKIO , MIURA SHOJI , SAKAKIBARA TOSHIO
IPC分类号： H01L27/06 , H01L21/8222
摘要： PURPOSE:To increase a surge current breakdown resistance by providing a protecting diode formed by P-N junction with a silicon layer in an area wherein an oxide silicon film is not present, and also to make it possible to set a breakdown voltage arbitrarily by changing the impurity concentration of a substrate. CONSTITUTION:An oxide silicon film 3 is formed on the surface of a P type silicon substrate l1. After an unnecessary part thereof is removed by a photoetching technique, polysilicon doped with arsenic is formed and the surface thereof is ground, so that an N type polycrystalline layer 3 can be formed. Next, an N type silicon substrate is joined directly to the polycrystalline layer 3 and the surface thereof is ground, so as to form an N type silicon layer 4. Thereafter an N type diffused region 6 is formed partially and an oxide silicon film 5 is formed as a surface insulation film thereon. Then, bipolar transistors Tr (4, 7, 8) and isolating separation layers 11 isolating and separating these Trs from the surroundings are provided in the silicon layer 4 on the oxide silicon film, and moreover a protective diode made up of the substrate 1, the polycrystalline layer 3 and the region 6 is made.

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