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1. 发明授权

US06894364B2 Capacitor in an interconnect system and method of manufacturing thereof 有权
标题翻译：互连系统中的电容器及其制造方法
公开(公告)号：US06894364B2
公开(公告)日：2005-05-17
申请号：US10248833
申请日：2003-02-24
申请人： Ming-Yin Hao , Tri-Rung Yew , Coming Chen , Tsong-Minn Hsieh , Nai-Chen Peng , Jih-Cheng Yeh
发明人： Ming-Yin Hao , Tri-Rung Yew , Coming Chen , Tsong-Minn Hsieh , Nai-Chen Peng , Jih-Cheng Yeh
IPC分类号： H01L21/02 , H01L21/768 , H01L23/522 , H01L29/00 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L28/60 , H01L21/76807 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： A fabrication method for an integrated device having a capacitor in an interconnect system is described. At least a first exposed metal line and a second metal line are provided in an insulating layer. A stack layer is deposited and patterned to form a film stack structure over the second metal line. An inter-metal dielectric layer is formed over the film stack structure, the first metal line and the insulating layer. At least a first dual damascene interconnect and a second dual damascene interconnect are formed over and in contact with the first metal line and the film stack structure, respectively.
摘要翻译：描述了在互连系统中具有电容器的集成器件的制造方法。至少第一露出金属线和第二金属线设置在绝缘层中。堆叠层并图案化以在第二金属线上形成膜堆叠结构。在膜堆叠结构，第一金属线和绝缘层之上形成金属间介电层。至少第一双镶嵌互连和第二双镶嵌互连分别形成在第一金属线和薄膜堆叠结构的上方并与之接触。

2. 发明授权

US06316330B1 Method of fabricating a shallow trench isolation semiconductor device 失效
标题翻译：制造浅沟槽隔离半导体器件的方法
公开(公告)号：US06316330B1
公开(公告)日：2001-11-13
申请号：US09699110
申请日：2000-10-26
申请人： Gwo-Shii Yang , Tri-Rung Yew , Coming Chen , Water Lur
发明人： Gwo-Shii Yang , Tri-Rung Yew , Coming Chen , Water Lur
IPC分类号： H01L2176
CPC分类号： H01L21/76224 , H01L21/3145
摘要： A method for fabricating a semiconductor device. A shallow trench isolation is formed by forming a well region, a gate oxide layer and a wiring layer prior to forming a trench in the substrate. The trench is then filled with silicon oxide layer doped with germanium, nitrogen, titanium or other refractory metal. In addition, a MOS device is also fabricated with a gate buried in the substrate with a shallow trench isolation filled with the doped silicon oxide layer formed therein.
摘要翻译：一种半导体器件的制造方法。通过在衬底中形成沟槽之前形成阱区，栅极氧化物层和布线层来形成浅沟槽隔离。然后用掺杂有锗，氮，钛或其它难熔金属的氧化硅层填充沟槽。此外，MOS器件还被制造成具有掩埋在衬底中的栅极，其中形成有在其中形成的掺杂氧化硅层的浅沟槽隔离。

3. 发明授权

US5976984A Process of making unlanded vias 失效
标题翻译：制作无人化过孔的过程
公开(公告)号：US5976984A
公开(公告)日：1999-11-02
申请号：US1416
申请日：1997-12-30
申请人： Coming Chen , Chih-Chien Liu , Kun-Chih Wang , Tri-Rung Yew
发明人： Coming Chen , Chih-Chien Liu , Kun-Chih Wang , Tri-Rung Yew
IPC分类号： H01L21/768 , H01L23/522 , H01L21/02
CPC分类号： H01L23/5226 , H01L21/76802 , H01L21/76829 , H01L2924/0002
摘要： A method of making vias in a semiconductor IC device having adequate contact to the surface of the interconnects and without inadequate landing is disclosed. The method has interconnects formed in a metal layer on the substrate of the IC device, and a first dielectric layer is formed covering the surface of the interconnects. An etch-stopping layer is then formed on top of the first dielectric layer, followed by the formation of a second dielectric layer on top of the etch-stopping layer. A photoresist layer then covers the second dielectric layer and reveals the surface regions of the second dielectric layer designated for the formation of the vias. A main etching procedure is then performed to etch into the second dielectric layer down to the surface of the etch-stopping layer, thereby forming the first section of the vias. An over-etching procedure is then implemented to strip off the etch-stopping layer and further etches into the first dielectric layer and the etching is then stopped when the surface of the interconnects are revealed to conclude the formation of the vias.
摘要翻译：公开了一种在半导体IC器件中形成通孔的方法，该半导体IC器件具有与互连表面的充分接触并且没有不足够的着陆。该方法具有形成在IC器件的衬底上的金属层中的互连，并且覆盖互连表面的第一介电层被形成。然后在第一介电层的顶部上形成蚀刻停止层，随后在蚀刻停止层的顶部形成第二电介质层。光致抗蚀剂层然后覆盖第二电介质层并且显露指定用于形成通孔的第二电介质层的表面区域。然后执行主蚀刻程序以蚀刻到第二介电层中，直到蚀刻停止层的表面，从而形成通孔的第一部分。然后实施过蚀刻程序以剥离蚀刻停止层并进一步蚀刻到第一介电层中，然后当显露互连表面以终止形成通孔时，停止蚀刻。

4. 发明授权

US06306722B1 Method for fabricating shallow trench isolation structure 有权
标题翻译：浅沟槽隔离结构的制造方法
公开(公告)号：US06306722B1
公开(公告)日：2001-10-23
申请号：US09304143
申请日：1999-05-03
申请人： Gwo-Shii Yang , Tri-Rung Yew , Coming Chen , Water Lur
发明人： Gwo-Shii Yang , Tri-Rung Yew , Coming Chen , Water Lur
IPC分类号： H01L2176
CPC分类号： H01L21/76224 , H01L21/3145
摘要： A method for fabricating, a shallow trench isolation structure. A pad oxide layer and a silicon nitride layer are formed in sequence on a substrate. A trench is formed in the substrate and a liner oxide layer is formed on a sidewall of the trench. A doped silicon dioxide layer is formed on the silicon nitride layer and fills the trench. An annealing process is performed to density the doped silicon dioxide layer. A portion of the doped silicon dioxide layer is removed to expose the silicon nitride layer by a planarization process.
摘要翻译：一种制造浅沟槽隔离结构的方法。在衬底上依次形成焊盘氧化物层和氮化硅层。在衬底中形成沟槽，并且在沟槽的侧壁上形成衬垫氧化物层。掺杂的二氧化硅层形成在氮化硅层上并填充沟槽。执行退火处理以使掺杂的二氧化硅层密集。去除掺杂二氧化硅层的一部分以通过平坦化工艺暴露氮化硅层。

5. 发明授权

US06475865B1 Method of fabricating semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US06475865B1
公开(公告)日：2002-11-05
申请号：US09699200
申请日：2000-10-26
申请人： Gwo-Shii Yang , Tri-Rung Yew , Coming Chen , Water Lur
发明人： Gwo-Shii Yang , Tri-Rung Yew , Coming Chen , Water Lur
IPC分类号： H01L21336
CPC分类号： H01L21/76224 , H01L21/3145
摘要： A method for fabricating a semiconductor device. A shallow trench isolation is formed by forming a well region, a gate oxide layer and a wiring layer prior to forming a trench in the substrate. The trench is then filled with silicon oxide layer doped with germanium, nitrogen, titanium or other refractory metal. In addition, a MOS device is also fabricated with a gate buried in the substrate with a shallow trench isolation filled with the doped silicon oxide layer formed therein.
摘要翻译：一种半导体器件的制造方法。通过在衬底中形成沟槽之前形成阱区，栅极氧化物层和布线层来形成浅沟槽隔离。然后用掺杂有锗，氮，钛或其它难熔金属的氧化硅层填充沟槽。此外，MOS器件还被制造成具有掩埋在衬底中的栅极，其中形成有在其中形成的掺杂氧化硅层的浅沟槽隔离。

6. 发明授权

US6117743A Method of manufacturing MOS device using anti reflective coating 失效
标题翻译：使用抗反射涂层制造MOS器件的方法
公开(公告)号：US6117743A
公开(公告)日：2000-09-12
申请号：US203023
申请日：1998-12-01
申请人： Wen-Kuan Yeh , Tony Lin , Coming Chen
发明人： Wen-Kuan Yeh , Tony Lin , Coming Chen
IPC分类号： H01L21/027 , H01L21/28 , H01L21/336 , H01L29/49
CPC分类号： H01L29/66575 , H01L21/0276 , H01L21/28061 , H01L21/28123 , H01L29/4941 , H01L29/66545 , Y10S438/952
摘要： A method of manufacturing MOS device including the steps of providing a semiconductor substrate that has a device isolation structure thereon, and then depositing a gate oxide layer, a polysilicon layer and an anti-reflection coating in sequence over the substrate. Next, a gate structure is patterned out of the gate oxide layer, the polysilicon layer and the anti-reflection coating. Then, spacers are formed on the sidewalls of the gate structure. Thereafter, a metal silicide layer is formed over source/drain regions. After that, an inter-layer dielectric (ILD) layer is formed over the gate structure and the entire substrate. Then, the inter-layer dielectric layer is planarized to expose the anti-reflection coating. Next, the anti-reflection coating is removed, and then a barrier layer is deposited over the inter-layer dielectric layer and the polysilicon layer. Subsequently, a conductive layer is deposited over the barrier layer. Finally, a chemical-mechanical polishing operation is carried out to planarize the conductive layer, retaining only the conductive layer above the polysilicon layer.
摘要翻译：一种制造MOS器件的方法，包括以下步骤：提供在其上具有器件隔离结构的半导体衬底，然后在衬底上依次沉积栅极氧化物层，多晶硅层和抗反射涂层。接下来，栅极结构从栅极氧化物层，多晶硅层和抗反射涂层构图。然后，在栅极结构的侧壁上形成间隔物。此后，在源极/漏极区域上形成金属硅化物层。之后，在栅极结构和整个衬底上形成层间介电层（ILD）层。然后，层间电介质层被平坦化以暴露抗反射涂层。接下来，去除防反射涂层，然后在层间电介质层和多晶硅层上沉积阻挡层。随后，在阻挡层上沉积导电层。最后，进行化学机械抛光操作以使导电层平坦化，仅在多晶硅层上保留导电层。

7. 发明授权

US6004852A Manufacture of MOSFET having LDD source/drain region 失效
标题翻译：具有LDD源极/漏极区域的MOSFET的制造
公开(公告)号：US6004852A
公开(公告)日：1999-12-21
申请号：US864217
申请日：1997-05-28
申请人： Wen-Kuan Yeh , Coming Chen , George Chou
发明人： Wen-Kuan Yeh , Coming Chen , George Chou
IPC分类号： H01L21/266 , H01L21/336 , H01L21/3205
CPC分类号： H01L29/66598 , H01L21/266 , H01L29/6659
摘要： An LDD source/drain region is manufactured adjacent a gate electrode using a single ion implantation step. The method begins by providing a polysilicon gate electrode on a gate oxide over a substrate and then providing a thin, layer of CVD oxide over the gate electrode and over the substrate. A thicker, second layer of a material different from the first silicon oxide layer is deposited over the device and is etched back to form sidewall spacer structures alongside and spaced slightly from the gate electrode. The spacer structures formed from the second layer are then used as a mask to etch the oxide layer where it is exposed over the active regions of the substrate and then the spacer structures are removed. The portion of the oxide layer that remains over the top and sides of the gate electrode and over portions of the substrate adjacent the gate electrode is then used as a mask for an ion implantation process. Implantation through the mask forms a more lightly doped and more shallowly doped region in the substrate beneath the mask and a more heavily doped and more deeply doped region in the portions of the source/drain regions that were not covered by the mask. Accordingly, implantation through the mask formed in this way forms a complete source/drain region having a lightly doped drain structure alongside the FET of the integrated circuit device. Formation of LDD source/drain regions in this manner saves a number of manufacturing steps, resulting in reduced turn around time and reduced costs.
摘要翻译：使用单个离子注入步骤在栅极附近制造LDD源极/漏极区域。该方法开始于在衬底上的栅极氧化物上提供多晶硅栅极电极，然后在栅电极和衬底上方提供薄的CVD氧化物层。将不同于第一氧化硅层的材料的较厚的第二层沉积在器件上并被回蚀刻以形成旁边并与栅电极稍微间隔开的侧壁间隔结构。然后将由第二层形成的间隔结构用作掩模以蚀刻其上暴露于衬底的有源区域上的氧化物层，然后去除衬垫结构。然后，使用保留在栅电极的顶部和侧面以及邻近栅电极的衬底的部分上的氧化物层的部分作为用于离子注入工艺的掩模。通过掩模的植入在掩模下面的衬底中形成更轻掺杂的并且更浅掺杂的区域，并且在源极/漏极区域的未被掩模覆盖的部分中的更重掺杂和更深的掺杂区域。因此，通过以这种方式形成的掩模的注入在集成电路器件的FET旁边形成具有轻掺杂漏极结构的完整源/漏区。以这种方式形成LDD源极/漏极区域节省了许多制造步骤，从而减少了周转时间并降低了成本。

8. 发明授权

US5770508A Method of forming lightly doped drains in metalic oxide semiconductor components 失效
标题翻译：在金属氧化物半导体部件中形成轻掺杂漏极的方法
公开(公告)号：US5770508A
公开(公告)日：1998-06-23
申请号：US868816
申请日：1997-06-04
申请人： Wen-Kuan Yeh , Coming Chen , Jih-Wen Chou
发明人： Wen-Kuan Yeh , Coming Chen , Jih-Wen Chou
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/66598 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The present invention relates to a method of forming lightly doped drains in metallic oxide semiconductor (MOS) components. The method includes forming a first, second, and third insulating layer above a silicon substrate having a gate, etching back the layers to leave behind L-shaped first spacers on sidewalls of the gate, followed by doping second type ions into the silicon substrate to form first lightly doped drains in the silicon substrate surface below the L-shaped first spacers, and second lightly doped drains in the silicon substrate surface elsewhere, further forming a fourth insulating to form third spacers, and using the using the third spacers, the first insulating layer, and the gate as masks when doping second type ions into the silicon substrate so as to form source/drain regions in silicon substrate surfaces not covered by the third spacers. Such a method produces greater yield and reduces leakage current from the transistor components.
摘要翻译：本发明涉及一种在金属氧化物半导体（MOS）部件中形成轻掺杂漏极的方法。该方法包括在具有栅极的硅衬底之上形成第一绝缘层，第二绝缘层和第三绝缘层，蚀刻层以留下栅极侧壁上的L形第一间隔物，然后将第二类型离子掺杂到硅衬底中在L基第一间隔物下面的硅衬底表面中形成第一轻掺杂漏极，在其他地方在硅衬底表面中形成第二轻掺杂漏极，进一步形成第四绝缘体以形成第三间隔物，并且使用第三间隔物，绝缘层和栅极作为掩模，当将第二类型离子掺入硅衬底中时，以便在未被第三间隔物覆盖的硅衬底表面中形成源/漏区。这种方法产生更大的产量并减少来自晶体管部件的泄漏电流。

9. 发明申请

US20060009005A1 CHEMICAL MECHANICAL POLISHING FOR FORMING A SHALLOW TRENCH ISOLATION STRUCTURE 有权
标题翻译：用于形成浅层隔离结构的化学机械抛光
公开(公告)号：US20060009005A1
公开(公告)日：2006-01-12
申请号：US10984045
申请日：2004-11-09
申请人： Coming Chen , Juan-Yuan Wu , Water Lur
发明人： Coming Chen , Juan-Yuan Wu , Water Lur
IPC分类号： H01L21/76 , H01L21/302
CPC分类号： H01L21/31144 , H01L21/31053 , H01L21/31056 , H01L21/76229 , Y10S438/942
摘要： A method of chemical-mechanical polishing for forming a shallow trench isolation is disclosed. A substrate having a number of active regions, including a number of relatively large active regions and a number of relatively small active regions, is provided. The method comprises the following steps. A silicon nitride layer on the substrate is first formed. A number of shallow trenches are formed between the active regions. An oxide layer is formed over the substrate, so that the shallow trenches are filled with the oxide layer. A partial reverse active mask is formed on the oxide layer. The partial reverse active mask has an opening at a central part of each relatively large active region. The opening exposes a portion of the oxide layer. The opening has at least a dummy pattern. The oxide layer on the central part of each large active region is removed to expose the silicon nitride layer. The partial reverse active mask is removed. The oxide layer is planarized to expose the silicon nitride layer.
摘要翻译：公开了用于形成浅沟槽隔离的化学机械抛光的方法。提供具有多个有源区的基板，包括多个相对较大的有源区和多个相对小的有源区。该方法包括以下步骤。首先形成衬底上的氮化硅层。在活性区域之间形成多个浅沟槽。在衬底上形成氧化物层，使得浅沟槽被氧化物层填充。在氧化物层上形成部分反向有源掩模。部分反向有源掩模在每个相对大的有效区域的中心部分具有开口。开口暴露氧化物层的一部分。开口至少有一个虚拟图案。去除每个大的有源区的中心部分的氧化物层，以露出氮化硅层。去除部分反向主动掩模。将氧化物层平坦化以暴露氮化硅层。

10. 发明授权

US06810511B2 Method of designing active region pattern with shift dummy pattern 有权
标题翻译：用移动虚拟图案设计有源区域图案的方法
公开(公告)号：US06810511B2
公开(公告)日：2004-10-26
申请号：US10284683
申请日：2002-10-30
申请人： Coming Chen , Juan-Yuan Wu , Water Lur
发明人： Coming Chen , Juan-Yuan Wu , Water Lur
IPC分类号： G06F1750
CPC分类号： H01L21/31053 , H01L21/76229 , H01L23/528 , H01L27/0207 , H01L2924/0002 , H01L2924/00
摘要： A method of designing an active region pattern with a shifted dummy pattern, wherein an integrated circuit having an original active region pattern thereon is provided. The original active region pattern is expanded with a first parameter of line width to obtain a first pattern. By subtracting the first pattern, a second pattern is obtained. A dummy pattern which comprises an array of a plurality of elements is provided. By shifting the elements, a shifted dummy pattern is obtained. The second pattern and the shifted dummy pattern are combined, so that an overlapped region thereof is extracted as a combined dummy pattern. The combined dummy pattern is expanded with a second parameter of line width, so that a resultant dummy pattern is obtained. The resultant dummy pattern is added to the first pattern, so that the active region pattern with a shifted dummy pattern is obtained.
摘要翻译：一种设计具有偏移的虚设图案的有源区域图案的方法，其中提供其上具有原始有源区域图案的集成电路。原始活动区域图案用线宽的第一参数展开以获得第一图案。通过减去第一图案，获得第二图案。提供了包括多个元件的阵列的虚拟图案。通过移动元件，获得移动的虚拟图案。第二图案和移位的虚拟图案被组合，使得其重叠区域被提取为组合的虚拟图案。组合的虚拟图案用线宽的第二参数扩展，从而获得合成的虚拟图案。将所得到的虚拟图案添加到第一图案，从而获得具有偏移的虚设图案的有源区域图案。

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