专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06306722B1 Method for fabricating shallow trench isolation structure 有权
标题翻译：浅沟槽隔离结构的制造方法
公开(公告)号：US06306722B1
公开(公告)日：2001-10-23
申请号：US09304143
申请日：1999-05-03
申请人： Gwo-Shii Yang , Tri-Rung Yew , Coming Chen , Water Lur
发明人： Gwo-Shii Yang , Tri-Rung Yew , Coming Chen , Water Lur
IPC分类号： H01L2176
CPC分类号： H01L21/76224 , H01L21/3145
摘要： A method for fabricating, a shallow trench isolation structure. A pad oxide layer and a silicon nitride layer are formed in sequence on a substrate. A trench is formed in the substrate and a liner oxide layer is formed on a sidewall of the trench. A doped silicon dioxide layer is formed on the silicon nitride layer and fills the trench. An annealing process is performed to density the doped silicon dioxide layer. A portion of the doped silicon dioxide layer is removed to expose the silicon nitride layer by a planarization process.
摘要翻译：一种制造浅沟槽隔离结构的方法。在衬底上依次形成焊盘氧化物层和氮化硅层。在衬底中形成沟槽，并且在沟槽的侧壁上形成衬垫氧化物层。掺杂的二氧化硅层形成在氮化硅层上并填充沟槽。执行退火处理以使掺杂的二氧化硅层密集。去除掺杂二氧化硅层的一部分以通过平坦化工艺暴露氮化硅层。

2. 发明授权

US06475865B1 Method of fabricating semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US06475865B1
公开(公告)日：2002-11-05
申请号：US09699200
申请日：2000-10-26
申请人： Gwo-Shii Yang , Tri-Rung Yew , Coming Chen , Water Lur
发明人： Gwo-Shii Yang , Tri-Rung Yew , Coming Chen , Water Lur
IPC分类号： H01L21336
CPC分类号： H01L21/76224 , H01L21/3145
摘要： A method for fabricating a semiconductor device. A shallow trench isolation is formed by forming a well region, a gate oxide layer and a wiring layer prior to forming a trench in the substrate. The trench is then filled with silicon oxide layer doped with germanium, nitrogen, titanium or other refractory metal. In addition, a MOS device is also fabricated with a gate buried in the substrate with a shallow trench isolation filled with the doped silicon oxide layer formed therein.
摘要翻译：一种半导体器件的制造方法。通过在衬底中形成沟槽之前形成阱区，栅极氧化物层和布线层来形成浅沟槽隔离。然后用掺杂有锗，氮，钛或其它难熔金属的氧化硅层填充沟槽。此外，MOS器件还被制造成具有掩埋在衬底中的栅极，其中形成有在其中形成的掺杂氧化硅层的浅沟槽隔离。

3. 发明授权

US06316330B1 Method of fabricating a shallow trench isolation semiconductor device 失效
标题翻译：制造浅沟槽隔离半导体器件的方法
公开(公告)号：US06316330B1
公开(公告)日：2001-11-13
申请号：US09699110
申请日：2000-10-26
申请人： Gwo-Shii Yang , Tri-Rung Yew , Coming Chen , Water Lur
发明人： Gwo-Shii Yang , Tri-Rung Yew , Coming Chen , Water Lur
IPC分类号： H01L2176
CPC分类号： H01L21/76224 , H01L21/3145
摘要： A method for fabricating a semiconductor device. A shallow trench isolation is formed by forming a well region, a gate oxide layer and a wiring layer prior to forming a trench in the substrate. The trench is then filled with silicon oxide layer doped with germanium, nitrogen, titanium or other refractory metal. In addition, a MOS device is also fabricated with a gate buried in the substrate with a shallow trench isolation filled with the doped silicon oxide layer formed therein.
摘要翻译：一种半导体器件的制造方法。通过在衬底中形成沟槽之前形成阱区，栅极氧化物层和布线层来形成浅沟槽隔离。然后用掺杂有锗，氮，钛或其它难熔金属的氧化硅层填充沟槽。此外，MOS器件还被制造成具有掩埋在衬底中的栅极，其中形成有在其中形成的掺杂氧化硅层的浅沟槽隔离。

4. 发明授权

US6087262A Method for manufacturing shallow trench isolation structure 有权
标题翻译：浅沟槽隔离结构的制造方法
公开(公告)号：US6087262A
公开(公告)日：2000-07-11
申请号：US189140
申请日：1998-11-09
申请人： Gwo-Shii Yang , Kuo-Tai Huang , Tri-Rung Yew , Water Lur
发明人： Gwo-Shii Yang , Kuo-Tai Huang , Tri-Rung Yew , Water Lur
IPC分类号： H01L21/3105 , H01L21/762 , H01L21/00
CPC分类号： H01L21/31053 , H01L21/76229
摘要： A method for manufacturing shallow trench isolation structure includes the steps of fabricating a self-aligned silicon nitride mask over the trench region so that a kink effect due to the misalignment of mask during a conventional mask-making process can be avoided. Moreover, the silicon nitride mask requires fewer steps and less complicated operations to construct than a conventional reverse tone mask.
摘要翻译：用于制造浅沟槽隔离结构的方法包括以下步骤：在沟槽区域上制造自对准氮化硅掩模，从而可以避免在常规掩模制造工艺期间由于掩模的未对准而产生的扭结效应。此外，与传统的反向色调掩模相比，氮化硅掩模需要更少的步骤和更少的复杂操作来构造。

5. 发明授权

US06228742B1 Method of fabricating shallow trench isolation structure 失效
标题翻译：制造浅沟槽隔离结构的方法
公开(公告)号：US06228742B1
公开(公告)日：2001-05-08
申请号：US09264692
申请日：1999-03-08
申请人： Tri-Rung Yew , Water Lur , Gwo-Shii Yang
发明人： Tri-Rung Yew , Water Lur , Gwo-Shii Yang
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： A method of fabricating a shallow trench isolation structure is described. A mask layer is formed on the substrate. The mask layer and the substrate are patterned to form trenches in the substrate. The trenches comprise a smallest trench. A first isolation layer is formed on the mask layer to fill partially the trenches. A densification step is performed. A second isolation layer is formed on the first isolation layer to fill completely the trench. The first isolation layer and the second isolation layer are removed until the mask layer is exposed. The mask layer is removed.
摘要翻译：描述了制造浅沟槽隔离结构的方法。在基板上形成掩模层。掩模层和衬底被图案化以在衬底中形成沟槽。沟槽包括最小的沟槽。在掩模层上形成第一隔离层以部分地填充沟槽。进行致密化步骤。在第一隔离层上形成第二隔离层以完全填充沟槽。去除第一隔离层和第二隔离层，直到掩模层露出。去除掩模层。

6. 发明授权

US06180492B2 Method of forming a liner for shallow trench isolation 有权
标题翻译：浅沟槽隔离衬垫的形成方法
公开(公告)号：US06180492B2
公开(公告)日：2001-01-30
申请号：US09237298
申请日：1999-01-25
申请人： Hsueh-Hao Shih , Tri-Rung Yew , Water Lur , Gwo-Shii Yang
发明人： Hsueh-Hao Shih , Tri-Rung Yew , Water Lur , Gwo-Shii Yang
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： An improved method for forming shallow trench isolation structure is described. The present method comprises the steps of providing a pad oxide layer and a mask layer on a semiconductor substrate and forming a trench structure therein. Next, a liner oxide layer is formed on the surface of the trench structure in the semiconductor substrate and is extensively formed on the side surface of the mask layer exposed therein and the top surface of the mask layer by wet oxidation. A dielectric material is deposited on the liner oxide layer and fills the trench structure. The dielectric material layer is planarized. The mask layer and the pad oxide layer are then removed to form the isolation structures. The method for forming the shallow trench structures on a semiconductor structure in accordance with the present invention can eliminate the kink effect that occurs in the conventional method.
摘要翻译：描述了一种用于形成浅沟槽隔离结构的改进方法。本方法包括以下步骤：在半导体衬底上提供衬垫氧化物层和掩模层，并在其中形成沟槽结构。接下来，在半导体衬底中的沟槽结构的表面上形成衬垫氧化物层，并且通过湿氧化在其中暴露于其中的掩模层的侧表面和掩模层的顶表面上广泛地形成衬里氧化物层。电介质材料沉积在衬垫氧化物层上并填充沟槽结构。介电材料层被平坦化。然后去除掩模层和焊盘氧化物层以形成隔离结构。根据本发明的在半导体结构上形成浅沟槽结构的方法可以消除在常规方法中发生的扭结效应。

7. 发明授权

US06251783B1 Method of manufacturing shallow trench isolation 失效
标题翻译：制造浅沟槽隔离的方法
公开(公告)号：US06251783B1
公开(公告)日：2001-06-26
申请号：US09189847
申请日：1998-11-12
申请人： Tri-Rung Yew , Kuo-Tai Huang , Gwo-Shii Yang , Water Lur
发明人： Tri-Rung Yew , Kuo-Tai Huang , Gwo-Shii Yang , Water Lur
IPC分类号： H01L21302
CPC分类号： H01L21/31053 , H01L21/76229
摘要： A method of manufacturing shallow trench isolation structures. The method includes the steps of depositing insulating material into the trench of a substrate to form an insulation layer. The substrate has a plurality of active regions, each occupying a different area and having different sizes. In addition, there is a silicon nitride layer on top of each active region. Thereafter, a photoresist layer is then deposited over the insulation layer. Next, a portion of the photoresist layer is etched back to expose a portion of the oxide layer so that the remaining photoresist material forms a cap layer over the recessed area of the insulation layer. Subsequently, using the photoresist cap layer as a mask, the insulation layer is etched to remove a portion of the exposed oxide layer, thereby forming trenches within the oxide layer. After that, the photoresist cap layer is removed. Finally, a chemical-mechanical polishing operation is carried out to polish the insulation layer until the silicon nitride layer is exposed.
摘要翻译：制造浅沟槽隔离结构的方法。该方法包括以下步骤：将绝缘材料沉积到衬底的沟槽中以形成绝缘层。基板具有多个活性区域，每个活性区域占据不同的区域并且具有不同的尺寸。此外，在每个有源区的顶部有一个氮化硅层。此后，然后将光致抗蚀剂层沉积在绝缘层上。接下来，将光致抗蚀剂层的一部分回蚀刻以暴露氧化物层的一部分，使得剩余的光致抗蚀剂材料在绝缘层的凹陷区域上形成覆盖层。随后，使用光致抗蚀剂覆盖层作为掩模，蚀刻绝缘层以去除暴露的氧化物层的一部分，从而在氧化物层内形成沟槽。之后，去除光致抗蚀剂覆盖层。最后，进行化学机械抛光操作以抛光绝缘层，直到暴露氮化硅层。

8. 发明授权

US5956598A Method for fabricating a shallow-trench isolation structure with a rounded corner in integrated circuit 有权
标题翻译：用于在集成电路中制造具有圆角的浅沟槽隔离结构的方法
公开(公告)号：US5956598A
公开(公告)日：1999-09-21
申请号：US164736
申请日：1998-10-01
申请人： Kuo-Tai Huang , Gwo-Shii Yang , Tri-Rung Yew , Water Lur
发明人： Kuo-Tai Huang , Gwo-Shii Yang , Tri-Rung Yew , Water Lur
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76224
摘要： A semiconductor fabrication method is provided for fabricating a shallow-trench isolation (STI) structure with a rounded corner in integrated circuits through a rapid thermal process (RTP). In the fabrication of the STI structure, a sharp corner is often undesirably formed. This sharp corner , if not eliminated, causes the occurrence of a leakage current when the resultant IC device is in operation that significantly degrades the performance of the resultant IC device. To eliminate this sharp corner , an RTP is performed at a temperature of above 1,100.degree. C., which temperature is higher than the glass transition temperature of the substrate, for about 1 to 2 minutes. The result is that the surface of the substrate is oxidized into an sacrificial oxide layer and the sharp corner is deformed into a rounded shape with a larger convex radius of curvature. This allows the problems arising from the existence of the sharp corner to be substantially eliminated. Compared to the prior art, this method not only is more simplified in process, but also allows a considerable saving in thermal budget, which makes this method more cost-effective to implement than the prior art.
摘要翻译：提供半导体制造方法，用于通过快速热处理（RTP）在集成电路中制造具有圆角的浅沟槽隔离（STI）结构。在STI结构的制造中，通常不希望地形成尖锐的拐角。如果不消除这个尖角，则当所得到的IC器件运行时会导致泄漏电流的发生，这显着降低了所得IC器件的性能。为了消除这个尖角，RTP在高于1100℃的温度下进行，该温度高于基板的玻璃化转变温度约1至2分钟。其结果是，衬底的表面被氧化成牺牲氧化物层，并且尖角变形为具有较大凸曲率半径的圆形形状。这允许基本上消除由尖角存在引起的问题。与现有技术相比，该方法不仅在过程中更简化，而且还可以大大节省热预算，这使得该方法比现有技术更具成本效益。

9. 发明授权

US06254676B1 Method for manufacturing metal oxide semiconductor transistor having raised source/drain 有权
标题翻译：制造具有升高的源极/漏极的金属氧化物半导体晶体管的方法
公开(公告)号：US06254676B1
公开(公告)日：2001-07-03
申请号：US09340969
申请日：1999-06-28
申请人： Gwo-Shii Yang , Michael W C Huang , Chien Chao Huang , Hsien-Ta Chung , Tri-Rung Yew
发明人： Gwo-Shii Yang , Michael W C Huang , Chien Chao Huang , Hsien-Ta Chung , Tri-Rung Yew
IPC分类号： C30B2514
CPC分类号： H01L29/6659 , H01L21/02532 , H01L21/02639 , H01L21/28035 , H01L29/41775 , H01L29/41783 , H01L29/6656 , H01L29/66628 , Y10S438/981
摘要： A method for manufacturing a metal oxide semiconductor transistor having a raised source/drain is described. A first spacer is formed on a sidewall of a gate electrode. An epitaxial layer is then formed on the exposed surface of the substrate and a top surface of the gate electrode. A light implantation step is then performed on the substrate while using the gate electrode and the first spacer as a first mask. Thereafter, a second spacer is formed on the sidewall of the gate electrode. A heavy implantation step is then performed on the substrate while using the gate electrode, the first spacer and the second spacer as a second mask. The epitaxial layer is then formed before the forming of the extension structure of the source/drain. Therefore, dopants in a source/drain extension structure avoid suffering the high temperature needed to form the epitaxial layer so that the redistribution of the dopants is prevented.
摘要翻译：描述了具有升高的源极/漏极的金属氧化物半导体晶体管的制造方法。在栅电极的侧壁上形成第一间隔物。然后在衬底的暴露表面和栅电极的顶表面上形成外延层。然后在使用栅电极和第一间隔件作为第一掩模的同时在衬底上执行光注入步骤。此后，在栅电极的侧壁上形成第二间隔物。然后在使用栅电极，第一间隔物和第二间隔物作为第二掩模的同时在衬底上执行沉重的注入步骤。然后在形成源极/漏极的延伸结构之前形成外延层。因此，源/漏扩展结构中的掺杂剂避免了形成外延层所需的高温，从而防止掺杂剂的再分布。

10. 发明授权

US06248644B1 Method of fabricating shallow trench isolation structure 有权
标题翻译：制造浅沟槽隔离结构的方法
公开(公告)号：US06248644B1
公开(公告)日：2001-06-19
申请号：US09301210
申请日：1999-04-28
申请人： Gwo-Shii Yang , Hsueh-Hao Shih , Chih-Chien Liu , Tri-Rung Yew
发明人： Gwo-Shii Yang , Hsueh-Hao Shih , Chih-Chien Liu , Tri-Rung Yew
IPC分类号： H01L2176
CPC分类号： H01L21/76235
摘要： A method of fabricating a shallow trench isolation structure is described. A preserve layer is formed on a substrate. A trench is formed in the substrate and the preserve layer. An oxide layer is formed over the substrate to fill the trench. A wet densification step is performed in a moist environment. A planarization step is performed until the preserve layer is exposed. A shallow trench isolation structure is formed.
摘要翻译：描述了制造浅沟槽隔离结构的方法。在基板上形成保护层。在衬底和保护层中形成沟槽。在衬底上形成氧化物层以填充沟槽。在潮湿的环境中进行湿致密化步骤。进行平坦化步骤直到保护层被暴露。形成浅沟槽隔离结构。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式