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1. 发明授权

US6004852A Manufacture of MOSFET having LDD source/drain region 失效
标题翻译：具有LDD源极/漏极区域的MOSFET的制造
公开(公告)号：US6004852A
公开(公告)日：1999-12-21
申请号：US864217
申请日：1997-05-28
申请人： Wen-Kuan Yeh , Coming Chen , George Chou
发明人： Wen-Kuan Yeh , Coming Chen , George Chou
IPC分类号： H01L21/266 , H01L21/336 , H01L21/3205
CPC分类号： H01L29/66598 , H01L21/266 , H01L29/6659
摘要： An LDD source/drain region is manufactured adjacent a gate electrode using a single ion implantation step. The method begins by providing a polysilicon gate electrode on a gate oxide over a substrate and then providing a thin, layer of CVD oxide over the gate electrode and over the substrate. A thicker, second layer of a material different from the first silicon oxide layer is deposited over the device and is etched back to form sidewall spacer structures alongside and spaced slightly from the gate electrode. The spacer structures formed from the second layer are then used as a mask to etch the oxide layer where it is exposed over the active regions of the substrate and then the spacer structures are removed. The portion of the oxide layer that remains over the top and sides of the gate electrode and over portions of the substrate adjacent the gate electrode is then used as a mask for an ion implantation process. Implantation through the mask forms a more lightly doped and more shallowly doped region in the substrate beneath the mask and a more heavily doped and more deeply doped region in the portions of the source/drain regions that were not covered by the mask. Accordingly, implantation through the mask formed in this way forms a complete source/drain region having a lightly doped drain structure alongside the FET of the integrated circuit device. Formation of LDD source/drain regions in this manner saves a number of manufacturing steps, resulting in reduced turn around time and reduced costs.
摘要翻译：使用单个离子注入步骤在栅极附近制造LDD源极/漏极区域。该方法开始于在衬底上的栅极氧化物上提供多晶硅栅极电极，然后在栅电极和衬底上方提供薄的CVD氧化物层。将不同于第一氧化硅层的材料的较厚的第二层沉积在器件上并被回蚀刻以形成旁边并与栅电极稍微间隔开的侧壁间隔结构。然后将由第二层形成的间隔结构用作掩模以蚀刻其上暴露于衬底的有源区域上的氧化物层，然后去除衬垫结构。然后，使用保留在栅电极的顶部和侧面以及邻近栅电极的衬底的部分上的氧化物层的部分作为用于离子注入工艺的掩模。通过掩模的植入在掩模下面的衬底中形成更轻掺杂的并且更浅掺杂的区域，并且在源极/漏极区域的未被掩模覆盖的部分中的更重掺杂和更深的掺杂区域。因此，通过以这种方式形成的掩模的注入在集成电路器件的FET旁边形成具有轻掺杂漏极结构的完整源/漏区。以这种方式形成LDD源极/漏极区域节省了许多制造步骤，从而减少了周转时间并降低了成本。

2. 发明授权

US6117743A Method of manufacturing MOS device using anti reflective coating 失效
标题翻译：使用抗反射涂层制造MOS器件的方法
公开(公告)号：US6117743A
公开(公告)日：2000-09-12
申请号：US203023
申请日：1998-12-01
申请人： Wen-Kuan Yeh , Tony Lin , Coming Chen
发明人： Wen-Kuan Yeh , Tony Lin , Coming Chen
IPC分类号： H01L21/027 , H01L21/28 , H01L21/336 , H01L29/49
CPC分类号： H01L29/66575 , H01L21/0276 , H01L21/28061 , H01L21/28123 , H01L29/4941 , H01L29/66545 , Y10S438/952
摘要： A method of manufacturing MOS device including the steps of providing a semiconductor substrate that has a device isolation structure thereon, and then depositing a gate oxide layer, a polysilicon layer and an anti-reflection coating in sequence over the substrate. Next, a gate structure is patterned out of the gate oxide layer, the polysilicon layer and the anti-reflection coating. Then, spacers are formed on the sidewalls of the gate structure. Thereafter, a metal silicide layer is formed over source/drain regions. After that, an inter-layer dielectric (ILD) layer is formed over the gate structure and the entire substrate. Then, the inter-layer dielectric layer is planarized to expose the anti-reflection coating. Next, the anti-reflection coating is removed, and then a barrier layer is deposited over the inter-layer dielectric layer and the polysilicon layer. Subsequently, a conductive layer is deposited over the barrier layer. Finally, a chemical-mechanical polishing operation is carried out to planarize the conductive layer, retaining only the conductive layer above the polysilicon layer.
摘要翻译：一种制造MOS器件的方法，包括以下步骤：提供在其上具有器件隔离结构的半导体衬底，然后在衬底上依次沉积栅极氧化物层，多晶硅层和抗反射涂层。接下来，栅极结构从栅极氧化物层，多晶硅层和抗反射涂层构图。然后，在栅极结构的侧壁上形成间隔物。此后，在源极/漏极区域上形成金属硅化物层。之后，在栅极结构和整个衬底上形成层间介电层（ILD）层。然后，层间电介质层被平坦化以暴露抗反射涂层。接下来，去除防反射涂层，然后在层间电介质层和多晶硅层上沉积阻挡层。随后，在阻挡层上沉积导电层。最后，进行化学机械抛光操作以使导电层平坦化，仅在多晶硅层上保留导电层。

3. 发明授权

US5770508A Method of forming lightly doped drains in metalic oxide semiconductor components 失效
标题翻译：在金属氧化物半导体部件中形成轻掺杂漏极的方法
公开(公告)号：US5770508A
公开(公告)日：1998-06-23
申请号：US868816
申请日：1997-06-04
申请人： Wen-Kuan Yeh , Coming Chen , Jih-Wen Chou
发明人： Wen-Kuan Yeh , Coming Chen , Jih-Wen Chou
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/66598 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The present invention relates to a method of forming lightly doped drains in metallic oxide semiconductor (MOS) components. The method includes forming a first, second, and third insulating layer above a silicon substrate having a gate, etching back the layers to leave behind L-shaped first spacers on sidewalls of the gate, followed by doping second type ions into the silicon substrate to form first lightly doped drains in the silicon substrate surface below the L-shaped first spacers, and second lightly doped drains in the silicon substrate surface elsewhere, further forming a fourth insulating to form third spacers, and using the using the third spacers, the first insulating layer, and the gate as masks when doping second type ions into the silicon substrate so as to form source/drain regions in silicon substrate surfaces not covered by the third spacers. Such a method produces greater yield and reduces leakage current from the transistor components.
摘要翻译：本发明涉及一种在金属氧化物半导体（MOS）部件中形成轻掺杂漏极的方法。该方法包括在具有栅极的硅衬底之上形成第一绝缘层，第二绝缘层和第三绝缘层，蚀刻层以留下栅极侧壁上的L形第一间隔物，然后将第二类型离子掺杂到硅衬底中在L基第一间隔物下面的硅衬底表面中形成第一轻掺杂漏极，在其他地方在硅衬底表面中形成第二轻掺杂漏极，进一步形成第四绝缘体以形成第三间隔物，并且使用第三间隔物，绝缘层和栅极作为掩模，当将第二类型离子掺入硅衬底中时，以便在未被第三间隔物覆盖的硅衬底表面中形成源/漏区。这种方法产生更大的产量并减少来自晶体管部件的泄漏电流。

4. 发明授权

US5861329A Method of fabricating metal-oxide semiconductor (MOS) transistors with reduced level of degradation caused by hot carriers 失效
标题翻译：制造由热载流子引起的劣化水平的金属氧化物半导体（MOS）晶体管的方法
公开(公告)号：US5861329A
公开(公告)日：1999-01-19
申请号：US764254
申请日：1996-12-12
申请人： Wen-Kuan Yeh , Coming Chen , Meng-Jin Tsai , Jih-Wen Chou
发明人： Wen-Kuan Yeh , Coming Chen , Meng-Jin Tsai , Jih-Wen Chou
IPC分类号： H01L21/28 , H01L21/318 , H01L21/336 , H01L29/49 , H01L21/265 , H01L21/31
CPC分类号： H01L29/6659 , H01L21/0217 , H01L21/02247 , H01L21/28176 , H01L21/3185 , H01L29/4983 , H01L29/6656
摘要： A method of fabricating a metal-oxide semiconductor (MOS) transistor is provided. This method is devised particularly to reduce the level of degradation to the MOS transistor caused by hot carriers. In the fabrication process, a plasma treatment is applied to the wafer to as to cause the forming of a thin layer of silicon nitride on the wafer which covers the gate and the lightly-doped diffusion (LDD) regions on the source/drain regions of the MOS transistor. This thin layer of silicon nitride acts as a barrier which prevents hot carriers from crossing the gate dielectric layer, such that the degradation of the MOS transistor due to hot carriers crossing the gate dielectric layer can be greatly minimized.
摘要翻译：提供一种制造金属氧化物半导体（MOS）晶体管的方法。该方法特别设计用于降低由热载流子引起的对MOS晶体管的劣化程度。在制造过程中，对晶片施加等离子体处理，以便在覆盖栅极的晶片和在源极/漏极区上的轻掺杂扩散（LDD）区域上形成氮化硅薄层 MOS晶体管。该氮化硅薄层作为阻止热载流子与栅极介电层交叉的阻挡层，从而可以极大地最小化由于与跨越栅极电介质层的热载流子导致的MOS晶体管的劣化。

5. 发明授权

US6083827A Method for fabricating local interconnect 失效
标题翻译：制造局部互连的方法
公开(公告)号：US6083827A
公开(公告)日：2000-07-04
申请号：US212084
申请日：1998-12-15
申请人： Tony Lin , Coming Chen , Wen-Kuan Yeh
发明人： Tony Lin , Coming Chen , Wen-Kuan Yeh
IPC分类号： H01L21/321 , H01L21/336 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/76895 , H01L21/3212 , H01L29/66545
摘要： A method for fabricating a local interconnect. A gate having a gate oxide layer, a gate polysilicon layer and a cap layer is formed on a provided substrate. A spacer is formed on the sidewall of the gate, and a source/drain region is formed in the substrate. A planarized dielectric layer is formed over the substrate to expose the cap layer. A portion of the dielectric layer and the spacer on one side of the gate is removed to form an opening, so that the source/drain region is exposed. The opening is transformed into a local-interconnect opening by removing the cap layer. A local interconnect is formed by forming a conductive layer in the local-interconnect opening.
摘要翻译：一种用于制造局部互连的方法。在所提供的衬底上形成具有栅极氧化物层，栅极多晶硅层和覆盖层的栅极。在栅极的侧壁上形成间隔物，在衬底中形成源/漏区。平坦化介电层形成在衬底上以露出盖层。电介质层的一部分和栅极一侧上的间隔物被去除以形成开口，从而暴露出源极/漏极区域。通过去除盖层将开口转变成局部互连开口。通过在局部互连开口中形成导电层形成局部互连。

6. 发明授权

US06277699B1 Method for forming a metal-oxide-semiconductor transistor 失效
标题翻译：金属氧化物半导体晶体管的形成方法
公开(公告)号：US06277699B1
公开(公告)日：2001-08-21
申请号：US09187140
申请日：1998-11-06
申请人： Coming Chen , Wen-Kuan Yeh , Jih-Wen Chou
发明人： Coming Chen , Wen-Kuan Yeh , Jih-Wen Chou
IPC分类号： H01L21335
CPC分类号： H01L29/6659 , H01L21/2652 , H01L21/28114 , H01L29/4941 , H01L29/7836
摘要： A method for forming a MOS transistor is provided. A gate oxide layer, a polysilicon layer, a barrier layer and a conductive layer are sequentially formed on a provided substrate. A photolithography and etching process is carried out to remove a portion of the conductive layer and a portion of the barrier layer until exposing the polysilicon layer. An ion implantation is performed to form lightly doped regions in the substrate using the remaining conductive layer and the remaining barrier layer as a mask. A spacer is formed on the side-wall of the conductive layer and on the side-wall of the barrier layer. The polysilicon layer and the gate oxide layer, which are in positions other than those of the remaining conductive layer and the spacer, are removed. The remaining conductive layer and the remaining polysilicon layer constitute a gate with an inversed, T-shaped cross-section. Source/drain regions comprising the lightly doped regions are formed in the substrate by ion implantation using the gate structure as a mask.
摘要翻译：提供一种形成MOS晶体管的方法。在所提供的基板上依次形成栅氧化层，多晶硅层，阻挡层和导电层。进行光刻和蚀刻处理以去除导电层的一部分和阻挡层的一部分直到暴露多晶硅层。执行离子注入，以使用剩余的导电层和剩余的阻挡层作为掩模在衬底中形成轻掺杂区域。在导电层的侧壁和阻挡层的侧壁上形成间隔物。除去剩余导电层和间隔物以外的位置的多晶硅层和栅极氧化物层被去除。剩余的导电层和剩余的多晶硅层构成具有反转的T形横截面的栅极。通过使用栅极结构作为掩模的离子注入，在衬底中形成包括轻掺杂区的源/漏区。

7. 发明授权

US5786255A Method of forming a metallic oxide semiconductor 失效
标题翻译：形成金属氧化物半导体的方法
公开(公告)号：US5786255A
公开(公告)日：1998-07-28
申请号：US863426
申请日：1997-05-27
申请人： Wen-Kuan Yeh , Coming Chen , Jih-Wen Chou
发明人： Wen-Kuan Yeh , Coming Chen , Jih-Wen Chou
IPC分类号： H01L21/336 , H01L29/417
CPC分类号： H01L29/66583 , H01L29/41775 , H01L29/41783
摘要： A method of forming MOS components provides that after the formation of the gate and the doped source/drain regions, a polysilicon layer is deposited and planarized using a chemical-mechanical polishing method. The resulting unremoved polysilicon layer acts as source/drain terminals. Through these arrangements, the ion doped source/drain regions will have shallow junctions, yet their junction integrity will not be compromised by subsequent contact window etching and metallization processes. Furthermore, the front-end processes for forming the MOS component provide a good planar surface that offers great convenience for the performance of subsequent back-end processes.
摘要翻译：形成MOS部件的方法提供了在形成栅极和掺杂源极/漏极区域之后，使用化学 - 机械抛光方法沉积并平坦化多晶硅层。所产生的未移动的多晶硅层用作源极/漏极端子。通过这些布置，离子掺杂的源极/漏极区域将具有浅结，但是它们的连接完整性将不会被随后的接触窗蚀刻和金属化处理所影响。此外，用于形成MOS部件的前端工艺提供了良好的平面表面，为后续工艺的性能提供了极大的便利。

8. 发明授权

US06177336B1 Method for fabricating a metal-oxide semiconductor device 失效
标题翻译：金属氧化物半导体器件的制造方法
公开(公告)号：US06177336B1
公开(公告)日：2001-01-23
申请号：US09187245
申请日：1998-11-06
申请人： Tony Lin , Wen-Kuan Yeh , Coming Chen , Jih-Wen Chou
发明人： Tony Lin , Wen-Kuan Yeh , Coming Chen , Jih-Wen Chou
IPC分类号： H01L214763
CPC分类号： H01L29/66545 , H01L29/66537
摘要： A method for fabricating a metal-oxide semiconductor (MOS) transistor is provided. The method has steps of sequentially forming an oxide layer, a polysilicon layer and a cap layer on a semiconductor substrate to form a first-stage gate. An interchangeable source/drain region with a lightly doped drain (LDD) structure is formed in the substrate at each side of the first-stage gate. An insulating layer is formed over the substrate, and is planarized so as to exposed the cap layer. Removing the exposed cap layer forms an opening that exposes the polysilicon layer. Using the insulating layer as a mask, a self-aligned selective local implantation process is performed to form a threshold-voltage doped region and an anti-punch-through doped region below the oxide layer in the substrate. A conductive layer is formed over the substrate to fill the opening. A chemical mechanical polishing process is performed to expose the insulating layer so that a remaining portion of the conductive layer fills the opening to form together with the polysilicon layer and the oxide layer to serve as an gate structure.
摘要翻译：提供一种制造金属氧化物半导体（MOS）晶体管的方法。该方法具有在半导体衬底上依次形成氧化物层，多晶硅层和覆盖层以形成第一级栅极的步骤。在第一级栅极的每一侧的衬底中形成具有轻掺杂漏极（LDD）结构的可互换的源极/漏极区域。绝缘层形成在衬底上，并被平坦化以使盖层露出。去除暴露的盖层形成暴露多晶硅层的开口。使用绝缘层作为掩模，执行自对准选择性局部注入工艺以在衬底中的氧化物层下方形成阈值电压掺杂区域和抗穿通掺杂区域。导电层形成在衬底上以填充开口。执行化学机械抛光工艺以暴露绝缘层，使得导电层的剩余部分填充开口以与多晶硅层和氧化物层一起形成以用作栅极结构。

9. 发明授权

US06200870B1 Method for forming gate 有权
标题翻译：浇口形成方法
公开(公告)号：US06200870B1
公开(公告)日：2001-03-13
申请号：US09189355
申请日：1998-11-09
申请人： Wen-Kuan Yeh , Tony Lin , Jih-Wen Chou
发明人： Wen-Kuan Yeh , Tony Lin , Jih-Wen Chou
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/26586 , H01L21/28061 , H01L21/28247
摘要： A method for forming a gate that improves the quality of the gate includes sequentially forming a gate oxide layer, a polysilicon layer, a conductive layer and a masking layer on a substrate. Thereafter, the masking layer, the conductive layer, the polysilicon layer and the gate oxide layer are patterned to form the gate. Then, a passivation layer, for increasing the thermal stability and the chemical stability of the gate, is formed on the sidewall of the conductive layer by ion implantation with nitrogen cations. The nitrogen cations are doped into the substrate, under the gate oxide layer, by ion implantation, which can improve the penetration of the phosphorus ions.
摘要翻译：用于形成提高栅极质量的栅极的方法包括在衬底上顺序地形成栅极氧化物层，多晶硅层，导电层和掩模层。此后，对掩模层，导电层，多晶硅层和栅极氧化物层进行图案化以形成栅极。然后，通过用氮阳离子的离子注入，在导电层的侧壁上形成用于增加栅极的热稳定性和化学稳定性的钝化层。氮阳离子通过离子注入在栅极氧化物层下方掺杂到衬底中，这可以改善磷离子的渗透。

10. 发明授权

US06165857A Method for forming a transistor with selective epitaxial growth film 有权
标题翻译：用选择性外延生长膜形成晶体管的方法
公开(公告)号：US06165857A
公开(公告)日：2000-12-26
申请号：US469008
申请日：1999-12-21
申请人： Wen-Kuan Yeh , Tony Lin , Jih-Wen Chou
发明人： Wen-Kuan Yeh , Tony Lin , Jih-Wen Chou
IPC分类号： H01L21/28 , H01L21/336 , H01L29/417
CPC分类号： H01L29/6659 , H01L21/28052 , H01L29/41775 , H01L29/665 , H01L29/6656 , H01L29/66628
摘要： A new improvement for selective epitaxial growth is disclosed. In one embodiment, the present invention provides a low power metal oxide semiconductor field effect transistor (MOSFET), which includes a substrate. Next, a gate oxide layer is formed on the substrate. Moreover, a polysilicon layer is deposited on the gate oxide layer. Patterning to etch the polysilicon layer and the gate oxide layer to define a gate. First ions are implanted into the substrate by using said gate as a hard mask. Sequentially, a liner oxide is covered over the entire exposed surface of the resulting structure. Moreover, a conformal first dielectric layer and second dielectric layer are deposited above the liner oxide in proper order. The second dielectric layer is etched back to form a dielectric spacer on sidewall of the first dielectric layer. Next, the first dielectric layer is etched until upper surface of the gate and a portion of the substrate are exposed, wherein a part of the second dielectric layer is also etched accompanying with etching a part of the first dielectric layer. Further, second ions are implanted into the exposed substrate to form a source/drain region. A conductive layer is selectively formed on said over the exposed gate and source/drain. Finally, a self-aligned silicide layer is formed over the conductive layer.
摘要翻译：公开了选择性外延生长的新改进。在一个实施例中，本发明提供一种包括衬底的低功率金属氧化物半导体场效应晶体管（MOSFET）。接着，在基板上形成栅极氧化层。此外，在栅极氧化物层上沉积多晶硅层。图案化以蚀刻多晶硅层和栅极氧化物层以限定栅极。通过使用所述栅极作为硬掩模将第一离子注入到衬底中。接下来，衬垫氧化物覆盖在所得结构的整个暴露表面上。此外，适形的第一介电层和第二介电层以适当的顺序沉积在衬垫氧化物的上方。回蚀第二电介质层以在第一电介质层的侧壁上形成电介质间隔物。接下来，蚀刻第一电介质层直到栅极的上表面和衬底的一部分被暴露，其中第二电介质层的一部分也被蚀刻，同时蚀刻第一介电层的一部分。此外，将第二离子注入暴露的衬底中以形成源/漏区。在暴露的栅极和源极/漏极上的选择性地形成导电层。最后，在导电层上形成自对准的硅化物层。

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