专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5976984A Process of making unlanded vias 失效
标题翻译：制作无人化过孔的过程
公开(公告)号：US5976984A
公开(公告)日：1999-11-02
申请号：US1416
申请日：1997-12-30
申请人： Coming Chen , Chih-Chien Liu , Kun-Chih Wang , Tri-Rung Yew
发明人： Coming Chen , Chih-Chien Liu , Kun-Chih Wang , Tri-Rung Yew
IPC分类号： H01L21/768 , H01L23/522 , H01L21/02
CPC分类号： H01L23/5226 , H01L21/76802 , H01L21/76829 , H01L2924/0002
摘要： A method of making vias in a semiconductor IC device having adequate contact to the surface of the interconnects and without inadequate landing is disclosed. The method has interconnects formed in a metal layer on the substrate of the IC device, and a first dielectric layer is formed covering the surface of the interconnects. An etch-stopping layer is then formed on top of the first dielectric layer, followed by the formation of a second dielectric layer on top of the etch-stopping layer. A photoresist layer then covers the second dielectric layer and reveals the surface regions of the second dielectric layer designated for the formation of the vias. A main etching procedure is then performed to etch into the second dielectric layer down to the surface of the etch-stopping layer, thereby forming the first section of the vias. An over-etching procedure is then implemented to strip off the etch-stopping layer and further etches into the first dielectric layer and the etching is then stopped when the surface of the interconnects are revealed to conclude the formation of the vias.
摘要翻译：公开了一种在半导体IC器件中形成通孔的方法，该半导体IC器件具有与互连表面的充分接触并且没有不足够的着陆。该方法具有形成在IC器件的衬底上的金属层中的互连，并且覆盖互连表面的第一介电层被形成。然后在第一介电层的顶部上形成蚀刻停止层，随后在蚀刻停止层的顶部形成第二电介质层。光致抗蚀剂层然后覆盖第二电介质层并且显露指定用于形成通孔的第二电介质层的表面区域。然后执行主蚀刻程序以蚀刻到第二介电层中，直到蚀刻停止层的表面，从而形成通孔的第一部分。然后实施过蚀刻程序以剥离蚀刻停止层并进一步蚀刻到第一介电层中，然后当显露互连表面以终止形成通孔时，停止蚀刻。

2. 发明授权

US06352918B1 Method of forming inter-metal interconnection 有权
标题翻译：形成金属间互连的方法
公开(公告)号：US06352918B1
公开(公告)日：2002-03-05
申请号：US09199877
申请日：1998-11-24
申请人： Yimin Huang , Chih-Chien Liu , Tri-Rung Yew
发明人： Yimin Huang , Chih-Chien Liu , Tri-Rung Yew
IPC分类号： H01L21311
CPC分类号： H01L21/76802
摘要： A method of forming an inter-metal interconnection is provided. A substrate is provided. A dielectric layer with a metal plug therein is formed on the substrate. An IMD layer is formed on the dielectric layer. An insulating layer and a PE-oxide layer are formed on the IMD layer. A photolithography and etching process is performed to form a trench in the IMD layer and to expose the metal plug in the dielectric layer. A metal is filled into the trench to electrically connect to the metal plug.
摘要翻译：提供了形成金属间互连的方法。提供基板。在基板上形成有金属塞的电介质层。在电介质层上形成IMD层。在IMD层上形成绝缘层和PE-氧化物层。进行光刻和蚀刻工艺以在IMD层中形成沟槽并露出介电层中的金属插塞。将金属填充到沟槽中以电连接到金属插头。

3. 发明授权

US06248644B1 Method of fabricating shallow trench isolation structure 有权
标题翻译：制造浅沟槽隔离结构的方法
公开(公告)号：US06248644B1
公开(公告)日：2001-06-19
申请号：US09301210
申请日：1999-04-28
申请人： Gwo-Shii Yang , Hsueh-Hao Shih , Chih-Chien Liu , Tri-Rung Yew
发明人： Gwo-Shii Yang , Hsueh-Hao Shih , Chih-Chien Liu , Tri-Rung Yew
IPC分类号： H01L2176
CPC分类号： H01L21/76235
摘要： A method of fabricating a shallow trench isolation structure is described. A preserve layer is formed on a substrate. A trench is formed in the substrate and the preserve layer. An oxide layer is formed over the substrate to fill the trench. A wet densification step is performed in a moist environment. A planarization step is performed until the preserve layer is exposed. A shallow trench isolation structure is formed.
摘要翻译：描述了制造浅沟槽隔离结构的方法。在基板上形成保护层。在衬底和保护层中形成沟槽。在衬底上形成氧化物层以填充沟槽。在潮湿的环境中进行湿致密化步骤。进行平坦化步骤直到保护层被暴露。形成浅沟槽隔离结构。

4. 发明授权

US06214691B1 Method for forming shallow trench isolation 失效
标题翻译：形成浅沟槽隔离的方法
公开(公告)号：US06214691B1
公开(公告)日：2001-04-10
申请号：US09228932
申请日：1999-01-12
申请人： Gwo-Shii Yong , Chih-Chien Liu , Tri-Rung Yew , Water Lur
发明人： Gwo-Shii Yong , Chih-Chien Liu , Tri-Rung Yew , Water Lur
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： A method for forming shallow trench isolation is disclosed. The method includes forming a trench in a semiconductor substrate, and then blanket depositing a silicon oxide layer over the semiconductor substrate by a plasma process, thereby substantially refilling the trench. Thereafter, a photoresist layer is formed on the plasma deposited silicon oxide layer, followed by etching back a portion of the photoresist layer. The plasma deposited silicon oxide layer is then isotropically etched, and the photoresist layer is then finally removed.
摘要翻译：公开了一种用于形成浅沟槽隔离的方法。该方法包括在半导体衬底中形成沟槽，然后通过等离子体工艺在半导体衬底上覆盖氧化硅层，从而基本上重新填充沟槽。此后，在等离子体沉积的氧化硅层上形成光致抗蚀剂层，然后蚀刻光致抗蚀剂层的一部分。然后等离子体沉积的氧化硅层被各向同性地蚀刻，然后最终去除光致抗蚀剂层。

5. 发明授权

US6080660A Via structure and method of manufacture 失效
标题翻译：通过结构和制造方法
公开(公告)号：US6080660A
公开(公告)日：2000-06-27
申请号：US32682
申请日：1998-02-27
申请人： Kun-Chih Wang , Hsiao-Pang Chou , Wen-Yi Hsieh , Tri-Rung Yew
发明人： Kun-Chih Wang , Hsiao-Pang Chou , Wen-Yi Hsieh , Tri-Rung Yew
IPC分类号： H01L21/311 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/31116 , H01L21/76802 , H01L21/76805
摘要： A method for manufacturing a via structure comprising the steps of providing a semiconductor substrate, and then forming conductive line and dielectric layer over the substrate. Next, a photolithographic and a first etching operation are conducted so that an opening in the dielectric layer exposing the conductive line surface is formed. The first etching operation uses several etchants including fluorobutane, which has the highest concentration. Since there is a re-entrance structure at the bottom of the opening, a second etching operation is performed. In the second etching operation, a portion of the conductive line is etched for a fixed time interval to control the degree of etching. Consequently, a slanting surface is formed at the bottom of the opening and the re-entrance structure is eliminated. With a planarized bottom, step coverage of subsequently deposited material is increased.
摘要翻译：一种用于制造通孔结构的方法，包括以下步骤：提供半导体衬底，然后在衬底上形成导电线和电介质层。接下来，进行光刻和第一蚀刻操作，从而形成暴露导电线表面的电介质层中的开口。第一蚀刻操作使用多种蚀刻剂，包括具有最高浓度的氟代丁烷。由于在开口的底部存在再入口结构，因此进行第二蚀刻操作。在第二蚀刻操作中，导电线的一部分被蚀刻固定的时间间隔以控制蚀刻程度。因此，在开口的底部形成倾斜表面，并且消除了再入口结构。在平坦化的底部，随后沉积材料的阶梯覆盖率增加。

6. 发明授权

US6013579A Self-aligned via process for preventing poison via formation 有权
标题翻译：通过形成防止毒物的自对准通过过程
公开(公告)号：US6013579A
公开(公告)日：2000-01-11
申请号：US176385
申请日：1998-10-21
申请人： Kun-Chih Wang , Tri-Rung Yew
发明人： Kun-Chih Wang , Tri-Rung Yew
IPC分类号： H01L21/768 , H01L21/00
CPC分类号： H01L21/76829 , H01L21/76802 , H01L21/76897
摘要： A self-aligned via process to prevent the via poisoning includes forming a hydrogen silsesquioxane layer on the substrate and over a pre-formed metal layer, forming an etching stop layer on the hydrogen silsesquioxane layer, forming an oxide layer on the etching stop layer, and then proceeding with a two-step etching process to form a via. The two-step etching process first patterns the oxide layer using a patterned photoresist layer as a mask, and then patterns the etching stop layer together with the hydrogen silsesquioxane layer using the patterned oxide layer as a mask. Because the etching stop layer prevents the hydrogen silsesquioxane layer from reacting with the oxygen plasma during the photoresist layer removal process, via poisoning is eliminated.
摘要翻译：用于防止通路中毒的自对准通孔工艺包括在基板上和预成型的金属层上形成氢倍半硅氧烷层，在氢倍半硅氧烷层上形成蚀刻停止层，在蚀刻停止层上形成氧化物层，然后进行两步蚀刻工艺以形成通孔。两步蚀刻工艺首先使用图案化的光致抗蚀剂层作为掩模对氧化物层进行图案化，然后使用图案化氧化物层作为掩模，将蚀刻停止层与氢倍半硅氧烷层一起图案化。因为蚀刻停止层防止在光致抗蚀剂层去除过程中氢倍半硅氧烷层与氧等离子体反应，消除了中毒。

7. 发明授权

US06894364B2 Capacitor in an interconnect system and method of manufacturing thereof 有权
标题翻译：互连系统中的电容器及其制造方法
公开(公告)号：US06894364B2
公开(公告)日：2005-05-17
申请号：US10248833
申请日：2003-02-24
申请人： Ming-Yin Hao , Tri-Rung Yew , Coming Chen , Tsong-Minn Hsieh , Nai-Chen Peng , Jih-Cheng Yeh
发明人： Ming-Yin Hao , Tri-Rung Yew , Coming Chen , Tsong-Minn Hsieh , Nai-Chen Peng , Jih-Cheng Yeh
IPC分类号： H01L21/02 , H01L21/768 , H01L23/522 , H01L29/00 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L28/60 , H01L21/76807 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： A fabrication method for an integrated device having a capacitor in an interconnect system is described. At least a first exposed metal line and a second metal line are provided in an insulating layer. A stack layer is deposited and patterned to form a film stack structure over the second metal line. An inter-metal dielectric layer is formed over the film stack structure, the first metal line and the insulating layer. At least a first dual damascene interconnect and a second dual damascene interconnect are formed over and in contact with the first metal line and the film stack structure, respectively.
摘要翻译：描述了在互连系统中具有电容器的集成器件的制造方法。至少第一露出金属线和第二金属线设置在绝缘层中。堆叠层并图案化以在第二金属线上形成膜堆叠结构。在膜堆叠结构，第一金属线和绝缘层之上形成金属间介电层。至少第一双镶嵌互连和第二双镶嵌互连分别形成在第一金属线和薄膜堆叠结构的上方并与之接触。

8. 发明授权

US06316330B1 Method of fabricating a shallow trench isolation semiconductor device 失效
标题翻译：制造浅沟槽隔离半导体器件的方法
公开(公告)号：US06316330B1
公开(公告)日：2001-11-13
申请号：US09699110
申请日：2000-10-26
申请人： Gwo-Shii Yang , Tri-Rung Yew , Coming Chen , Water Lur
发明人： Gwo-Shii Yang , Tri-Rung Yew , Coming Chen , Water Lur
IPC分类号： H01L2176
CPC分类号： H01L21/76224 , H01L21/3145
摘要： A method for fabricating a semiconductor device. A shallow trench isolation is formed by forming a well region, a gate oxide layer and a wiring layer prior to forming a trench in the substrate. The trench is then filled with silicon oxide layer doped with germanium, nitrogen, titanium or other refractory metal. In addition, a MOS device is also fabricated with a gate buried in the substrate with a shallow trench isolation filled with the doped silicon oxide layer formed therein.
摘要翻译：一种半导体器件的制造方法。通过在衬底中形成沟槽之前形成阱区，栅极氧化物层和布线层来形成浅沟槽隔离。然后用掺杂有锗，氮，钛或其它难熔金属的氧化硅层填充沟槽。此外，MOS器件还被制造成具有掩埋在衬底中的栅极，其中形成有在其中形成的掺杂氧化硅层的浅沟槽隔离。

9. 发明授权

US06306722B1 Method for fabricating shallow trench isolation structure 有权
标题翻译：浅沟槽隔离结构的制造方法
公开(公告)号：US06306722B1
公开(公告)日：2001-10-23
申请号：US09304143
申请日：1999-05-03
申请人： Gwo-Shii Yang , Tri-Rung Yew , Coming Chen , Water Lur
发明人： Gwo-Shii Yang , Tri-Rung Yew , Coming Chen , Water Lur
IPC分类号： H01L2176
CPC分类号： H01L21/76224 , H01L21/3145
摘要： A method for fabricating, a shallow trench isolation structure. A pad oxide layer and a silicon nitride layer are formed in sequence on a substrate. A trench is formed in the substrate and a liner oxide layer is formed on a sidewall of the trench. A doped silicon dioxide layer is formed on the silicon nitride layer and fills the trench. An annealing process is performed to density the doped silicon dioxide layer. A portion of the doped silicon dioxide layer is removed to expose the silicon nitride layer by a planarization process.
摘要翻译：一种制造浅沟槽隔离结构的方法。在衬底上依次形成焊盘氧化物层和氮化硅层。在衬底中形成沟槽，并且在沟槽的侧壁上形成衬垫氧化物层。掺杂的二氧化硅层形成在氮化硅层上并填充沟槽。执行退火处理以使掺杂的二氧化硅层密集。去除掺杂二氧化硅层的一部分以通过平坦化工艺暴露氮化硅层。

10. 发明授权

US06475865B1 Method of fabricating semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US06475865B1
公开(公告)日：2002-11-05
申请号：US09699200
申请日：2000-10-26
申请人： Gwo-Shii Yang , Tri-Rung Yew , Coming Chen , Water Lur
发明人： Gwo-Shii Yang , Tri-Rung Yew , Coming Chen , Water Lur
IPC分类号： H01L21336
CPC分类号： H01L21/76224 , H01L21/3145
摘要： A method for fabricating a semiconductor device. A shallow trench isolation is formed by forming a well region, a gate oxide layer and a wiring layer prior to forming a trench in the substrate. The trench is then filled with silicon oxide layer doped with germanium, nitrogen, titanium or other refractory metal. In addition, a MOS device is also fabricated with a gate buried in the substrate with a shallow trench isolation filled with the doped silicon oxide layer formed therein.
摘要翻译：一种半导体器件的制造方法。通过在衬底中形成沟槽之前形成阱区，栅极氧化物层和布线层来形成浅沟槽隔离。然后用掺杂有锗，氮，钛或其它难熔金属的氧化硅层填充沟槽。此外，MOS器件还被制造成具有掩埋在衬底中的栅极，其中形成有在其中形成的掺杂氧化硅层的浅沟槽隔离。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式