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    • 3. 发明申请
    • OPERATING METHOD OF A NON-VOLATILE MEMORY
    • 非易失性存储器的操作方法
    • US20070263448A1
    • 2007-11-15
    • US11778657
    • 2007-07-17
    • Wei-Zhe WongChing-Sung YangChih-Chen Cho
    • Wei-Zhe WongChing-Sung YangChih-Chen Cho
    • G11C11/34G11C16/04
    • G11C16/0416H01L27/115H01L27/11521H01L29/40114H01L29/42328H01L29/66825H01L29/7887
    • A non-volatile memory is provided. A substrate has at least two isolation structures therein to define an active area. A well is located in the substrate. A shallow doped region is located in the well. At least two stacked gate structures are located on the substrate. Pocket doped regions are located in the substrate at the peripheries of the stacked gate structures; each of the pocket doped regions extends under the stacked gate structure. Drain regions are located in the pocket doped regions at the peripheries of the stacked gate structures. An auxiliary gate layer is located on the substrate between the stacked gate structures. A gate dielectric layer is located between the auxiliary gate layer and the substrate and between the auxiliary gate layer and the stacked gate structure. Plugs are located on the substrate and extended to connect with the pocket doped region and the drain regions therein.
    • 提供非易失性存储器。 衬底在其中具有至少两个隔离结构以限定有效区域。 一个井位于基板中。 浅掺杂区域位于井中。 至少两个堆叠的栅极结构位于衬底上。 袋状掺杂区域位于堆叠栅极结构的周边的衬底中; 每个口袋掺杂区域在堆叠的栅极结构之下延伸。 漏极区位于堆叠栅极结构的周边的口袋掺杂区域中。 辅助栅极层位于堆叠栅极结构之间的衬底上。 栅极电介质层位于辅助栅极层和衬底之间,并且位于辅助栅极层和堆叠栅极结构之间。 插头位于衬底上并延伸以与其中的口袋掺杂区域和漏极区域连接。
    • 5. 发明申请
    • NON-VOLATILE MEMORY CELL, FABRICATION METHOD AND OPERATING METHOD THEREOF
    • 非挥发性记忆体,制造方法及其操作方法
    • US20060039200A1
    • 2006-02-23
    • US10907031
    • 2005-03-17
    • Ching-Sung YangWei-Zhe WongChih-Chen Cho
    • Ching-Sung YangWei-Zhe WongChih-Chen Cho
    • G11C7/10
    • G11C16/0483G11C16/0466H01L27/115H01L27/11519H01L27/11568
    • A non-volatile memory including a plurality of memory units is provided. Each of the memory units includes a first memory cell and a second memory cell. The first memory cell is disposed over the substrate. The second memory cell is disposed next to the sidewall of the first memory cell and over the substrate. The first memory cell includes a first gate disposed over the substrate, a first composite dielectric layer disposed between the first gate and the substrate. The second memory cell includes a second gate disposed over the substrate and a second composite dielectric layer disposed between the second gate and the substrate and between the second gate and the first memory cell. Each of the first and second composite dielectric layers includes a bottom dielectric layer, a charge-trapping layer and a top dielectric layer.
    • 提供包括多个存储单元的非易失性存储器。 每个存储单元包括第一存储单元和第二存储单元。 第一存储单元设置在衬底上。 第二存储单元设置在第一存储单元的侧壁旁边且在衬底上。 第一存储单元包括设置在衬底上的第一栅极,设置在第一栅极和衬底之间的第一复合介电层。 第二存储单元包括设置在衬底上的第二栅极和设置在第二栅极和衬底之间以及第二栅极和第一存储单元之间的第二复合电介质层。 第一和第二复合电介质层中的每一个包括底部电介质层,电荷俘获层和顶部电介质层。
    • 8. 发明授权
    • Method of forming a field effect transistor
    • 形成场效应晶体管的方法
    • US06599789B1
    • 2003-07-29
    • US09713844
    • 2000-11-15
    • Todd R. AbbottZhongze WangJigish D. TrivediChih-Chen Cho
    • Todd R. AbbottZhongze WangJigish D. TrivediChih-Chen Cho
    • H01L2184
    • H01L29/66651H01L21/26533H01L29/0653H01L29/41766H01L29/66636
    • A method of forming a field effect transistor includes forming a channel region within bulk semiconductive material of a semiconductor substrate. Source/drain regions are formed on opposing sides of the channel region. An insulative dielectric region is formed within the bulk semiconductive material proximately beneath at least one of the source/drain regions. A method of forming a field effect transistor includes providing a semiconductor-on-insulator substrate, said substrate comprising a layer of semiconductive material formed over a layer of insulative material. All of a portion of the semiconductive material layer and all of the insulative material layer directly beneath the portion are removed thereby creating a void in the semiconductive material layer and the insulative material layer. Semiconductive channel material is formed within the void. Opposing source/drain regions are provided laterally proximate the channel material. A gate is formed over the channel material. Integrated circuitry includes a bulk semiconductor substrate. A field effect transistor thereon includes a gate, a channel region in the bulk semiconductor substrate, and source/drain regions within the substrate on opposing sides of the channel region. A field isolation region is formed in the bulk semiconductor substrate and laterally adjoins with one of the source/drain regions. The field isolation region includes a portion which extends beneath at least some of the one source/drain region. Other aspects are contemplated.
    • 形成场效应晶体管的方法包括在半导体衬底的本体半导体材料内形成沟道区。 源极/漏极区域形成在沟道区域的相对侧上。 绝缘电介质区域在本体半导体材料内形成在源极/漏极区域中的至少一个附近。 形成场效应晶体管的方法包括提供绝缘体上半导体衬底,所述衬底包括在绝缘材料层上形成的半导体材料层。 半导体材料层的一部分和直接在该部分正下方的所有绝缘材料层被除去,从而在半导体材料层和绝缘材料层中产生空隙。 半导体通道材料形成在空隙内。 相邻的源极/漏极区域横向靠近通道材料提供。 在通道材料上形成一个栅极。 集成电路包括体半导体衬底。 其中的场效应晶体管包括栅极,体半导体衬底中的沟道区,以及在沟道区的相对侧上的衬底内的源极/漏极区。 在体半导体衬底中形成场隔离区域,并且与源极/漏极区域之一横向邻接。 场隔离区域包括在一个源极/漏极区域中的至少一些的下方延伸的部分。 考虑其他方面。