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1. 发明授权

US06373088B1 Edge stress reduction by noncoincident layers 失效
公开(公告)号：US06373088B1
公开(公告)日：2002-04-16
申请号：US09096012
申请日：1998-06-10
申请人： Siang Ping Kwok , William F. Richardson , Dirk N. Anderson
发明人： Siang Ping Kwok , William F. Richardson , Dirk N. Anderson
IPC分类号： H01L2100
摘要： The stress at the edges of a thin film conductor can be reduced by noncoincident layered structures, which takes advantage of the characteristic stress polarity changing from tensile to compressive or vice versa in the edge vicinity in order to avoid device reliability and performance problems. By using noncoincident layered structures, destructive stress interference from different layers can be achieved to reduce the stress or stress gradient at the edge. The structures and methods disclosed herein can advantageously be used in many integrated circuit and device manufacturing applications (including gates, wordlines, and bitlines).

2. 发明授权

US5300447A Method of manufacturing a minimum scaled transistor 失效
标题翻译：制造最小比例晶体管的方法
公开(公告)号：US5300447A
公开(公告)日：1994-04-05
申请号：US953632
申请日：1992-09-29
申请人： Dirk N. Anderson
发明人： Dirk N. Anderson
IPC分类号： H01L29/41 , H01L21/336 , H01L29/78
CPC分类号： H01L29/66621
摘要： An extremely small minimum scaled Metal-Oxide-Semiconductor, MOS, transistor is manufactured by forming a trench in a semiconductor substrate, forming a gate in the trench, and then forming source and drain regions. The source and drain regions may be diffused into the semiconductor substrate and annealed to drive the diffusions around the trench corners, thus forming the transistor channel. This improves punchthrough resistance of the transistor while yielding an extremely small gate channel. The diffusion concentration will be larger near the surface of the semiconductor substrate and smaller near the plane of the gate channel underneath the trench bottom. The trench corners have the effect of serving as a line source of dopant for diffusion under the trench such that the doping profile is the same along a radius of a cylindrical junction, thus keeping the minimum diffusion separation at the channel surface.
摘要翻译：通过在半导体衬底中形成沟槽，在沟槽中形成栅极，然后形成源极和漏极区域，制造极小的最小尺寸的金属氧化物半导体MOS晶体管。源极和漏极区域可以扩散到半导体衬底中并退火以驱动围绕沟槽角的扩散，从而形成晶体管沟道。这提高了晶体管的穿透阻抗，同时产生极小的栅极通道。在半导体衬底的表面附近的扩散浓度将更大，并且在沟槽底部下方的栅极通道的平面附近更小。沟槽角部具有用作沟槽下方扩散的掺杂剂的线源的作用，使得掺杂分布沿着圆柱形结的半径相同，从而保持在沟道表面处的最小扩散分离。

3. 发明授权

US4751198A Process for making contacts and interconnections using direct-reacted silicide 失效
标题翻译：使用直接反应的硅化物进行接触和互连的方法
公开(公告)号：US4751198A
公开(公告)日：1988-06-14
申请号：US774675
申请日：1985-09-11
申请人： Dirk N. Anderson
发明人： Dirk N. Anderson
IPC分类号： H01L21/28 , H01L21/285 , H01L21/3205 , H01L21/768 , H01L21/283
CPC分类号： H01L21/76879 , H01L21/28518 , Y10S148/147
摘要： Metal contacts and interconnections for semiconductor integrated circuits are formed by a process using direct-reacted silicide to increase step or sidewall coverage. A thin layer of titanium or the like is deposited, extending into a contact hole, then polysilicon is deposited over the titanium coating the vertical sides of steps or apertures. A second thin layer of titanium is deposited, then a heat treatment forms silicide to create a titanium silicide layer, including conductive sidewalls or a plug. Metal contacts and interconnections then engage the direct-reacted silicide rather than relying upon step coverage.
摘要翻译：用于半导体集成电路的金属触点和互连通过使用直接反应的硅化物来增加步骤或侧壁覆盖的工艺形成。沉积薄层的钛等，延伸到接触孔中，然后将多晶硅沉积在钛涂层上的台阶或孔的垂直侧面上。沉积第二薄钛层，然后热处理形成硅化物以产生包括导电侧壁或插头的硅化钛层。然后金属接触和互连接合直接反应的硅化物，而不是依赖于台阶覆盖。

4. 发明授权

US4744858A Integrated circuit metallization with reduced electromigration 失效
公开(公告)号：US4744858A
公开(公告)日：1988-05-17
申请号：US710346
申请日：1985-03-11
申请人： James M. McDavid , Dirk N. Anderson
发明人： James M. McDavid , Dirk N. Anderson
IPC分类号： H01L21/768 , H01L23/532 , B44C1/22 , C03C15/00 , C03C25/06
CPC分类号： H01L21/76804 , H01L23/53214 , H01L2924/0002 , Y10S438/927 , Y10S438/964
摘要： The specification discloses a method and a device wherein circuit elements (10) are formed on the surface of a semiconductor body (12). A layer of oxide (22) is applied over the circuit element (10). An aperture (32) is opened through the oxide layer (22). The surface of oxide layer (22) is nonuniformly substantially roughened. A layer of metal (24) such as aluminum is formed over the oxide layer (22) and extends into the aperture (32) for contact with a portion of the device (10). The layer of metal (24) has increased granular structure and a roughened exterior surface to provide enhanced electromigration properties.

5. 发明授权

US5112762A High angle implant around top of trench to reduce gated diode leakage 失效
标题翻译：在沟槽顶部的高角度植入物，以减少栅极二极管泄漏
公开(公告)号：US5112762A
公开(公告)日：1992-05-12
申请号：US622468
申请日：1990-12-05
申请人： Dirk N. Anderson , William R. McKee , Gishi Chung
发明人： Dirk N. Anderson , William R. McKee , Gishi Chung
IPC分类号： H01L21/265 , H01L21/316 , H01L21/32 , H01L21/334 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108
CPC分类号： H01L29/66181 , H01L21/0217 , H01L21/022 , H01L21/02211 , H01L21/02238 , H01L21/02255 , H01L21/02271 , H01L21/26586 , H01L21/31662 , H01L21/32
摘要： A method of reducing gated diode leakage in trench capacitor type field plate isolated dynamic random access memory devices is disclosed. The storage node of the capacitor is formed by placing a storage node material, such as implanted arsenic, into the trench walls of the device at a first tilt and a second tilt. The angle of the second tilt is preferably larger, higher, than the angle of the first tilt. This higher angle provides the storage node with a larger concentration of doping around the upper portion the trench walls. This larger concentration of doping reduces the charge leaking from the upper portion of the storage node into the substrate of semiconductor material. A trench type storage capacitor for a dynamic random access memory device is also disclosed.
摘要翻译：公开了一种在沟槽电容器型场板隔离型动态随机存取存储器件中降低栅极二极管泄漏的方法。电容器的存储节点通过将诸如注入的砷的存储节点材料以第一倾斜和第二倾斜放置在器件的沟槽壁中而形成。第二倾斜的角度优选地比第一倾斜的角度更大，更高。这种较高的角度为存储节点提供了围绕沟槽壁上部的更大的掺杂浓度。这种较大的掺杂浓度降低了从存储节点的上部泄漏到半导体材料的衬底中的电荷。还公开了一种用于动态随机存取存储器件的沟槽型存储电容器。

6. 发明授权

US06380008B2 Edge stress reduction by noncoincident layers 有权
标题翻译：非积层的边缘应力降低
公开(公告)号：US06380008B2
公开(公告)日：2002-04-30
申请号：US09738001
申请日：2000-12-14
申请人： Siang Ping Kwok , William F. Richardson , Dirk N. Anderson
发明人： Siang Ping Kwok , William F. Richardson , Dirk N. Anderson
IPC分类号： H01L2100
CPC分类号： H01L29/42376 , H01L21/28044 , H01L21/28114 , H01L29/4941
摘要： The stress at the edges of a thin film conductor can be reduced by noncoincident layered structures, which takes advantage of the characteristic stress polarity changing from tensile to compressive or vice versa in the edge vicinity in order to avoid device reliability and performance problems. By using noncoincident layered structures, destructive stress interference from different layers can be achieved to reduce the stress or stress gradient at the edge. The structures and methods disclosed herein can advantageously be used in many integrated circuit and device manufacturing applications (including gates, wordlines, and bitlines).
摘要翻译：薄膜导体边缘处的应力可以通过不重合的分层结构来减少，这样就可以利用边缘附近的拉伸到压缩特性应力极性，反之亦然，以避免器件的可靠性和性能问题。通过使用非重合分层结构，可以实现来自不同层的破坏性应力干扰，以减少边缘处的应力或应力梯度。本文公开的结构和方法可有利地用于许多集成电路和器件制造应用（包括门，字线和位线）中。

7. 发明授权

US06245605B1 Method to protect metal from oxidation during poly-metal gate formation in semiconductor device manufacturing 有权
标题翻译：在半导体器件制造中多金属栅极形成期间保护金属免于氧化的方法
公开(公告)号：US06245605B1
公开(公告)日：2001-06-12
申请号：US09369132
申请日：1999-08-05
申请人： Ming Hwang , Wei-Yung Hsu , Chih-Chen Cho , Dirk N. Anderson
发明人： Ming Hwang , Wei-Yung Hsu , Chih-Chen Cho , Dirk N. Anderson
IPC分类号： H01L218238
CPC分类号： H01L21/02164 , H01L21/02211 , H01L21/02238 , H01L21/02255 , H01L21/02271 , H01L21/28061 , H01L21/28247 , H01L21/31662 , H01L21/32105 , H01L29/4983
摘要： A method for protecting metal (112) from oxidation during various oxidation steps such as CVD SiO2 oxidation for forming an overlying oxide layer (114), smile oxidation, and sidewall (116) deposition. The gas CO2 is added to the oxidation chemistry. The CO2/H2 ratio is controlled for selective oxidation. The metal (112) is effectively protected from oxidation due to the existence of both H2 and CO2 as strong reduction reagents.
摘要翻译：一种用于在各种氧化步骤（例如CVD SiO 2氧化）中保护金属（112）不被氧化的方法，用于形成上覆氧化物层（114），微笑氧化和侧壁（116）沉积。气体二氧化碳被添加到氧化化学物质中。 CO 2 / H 2比被控制用于选择性氧化。由于H2和CO2作为强还原试剂的存在，金属（112）被有效地保护免于氧化。

8. 发明授权

US6159835A Encapsulated low resistance gate structure and method for forming same 有权
标题翻译：封装低电阻栅极结构及其形成方法
公开(公告)号：US6159835A
公开(公告)日：2000-12-12
申请号：US543642
申请日：2000-04-06
申请人： Mark R. Visokay , Dirk N. Anderson
发明人： Mark R. Visokay , Dirk N. Anderson
IPC分类号： H01L21/28 , H01L21/336 , H01L29/49 , H01L21/3205 , H01L21/4763
CPC分类号： H01L29/66583 , H01L21/28061 , H01L29/4941
摘要： An encapsulated gate structure includes a polysilicon layer, a barrier layer overlying the polysilicon layer and having opposing sidewalls, a metal layer overlying the barrier layer and having opposing sidewalls, a top dielectric layer overlying the metal layer and having opposing sidewalls, and a vertically oriented dielectric layer extending over and covering each of the opposing sidewalls of the barrier layer and the metal layer to encapsulate the barrier layer and metal layer on the polysilicon layer. The encapsulated gate and barrier layer are thus unaffected by oxidation and other similar detrimental effects of subsequent processing steps.
摘要翻译：封装的栅极结构包括多晶硅层，覆盖多晶硅层并具有相对侧壁的阻挡层，覆盖阻挡层并具有相对侧壁的金属层，覆盖金属层并具有相对侧壁的顶部电介质层和垂直定向电介质层延伸并覆盖阻挡层和金属层的相对侧壁中的每一个，以将阻挡层和金属层封装在多晶硅层上。因此，封装的栅极和阻挡层不受后续处理步骤的氧化和其它类似的有害影响的影响。

9. 发明授权

US4922320A Integrated circuit metallization with reduced electromigration 失效
标题翻译：具有减少电迁移的集成电路金属化
公开(公告)号：US4922320A
公开(公告)日：1990-05-01
申请号：US156132
申请日：1988-02-16
申请人： James M. McDavid , Dirk N. Anderson
发明人： James M. McDavid , Dirk N. Anderson
IPC分类号： H01L21/60 , H01L21/768 , H01L23/532
CPC分类号： H01L21/76897 , H01L21/76804 , H01L23/53214 , H01L2924/0002
摘要： The specification discloses a method and a device wherein circuit elements (10) are formed on the surface of a semiconductor body (12). A layer of oxide (22) is applied over the circuit element (10). An aperture (32) is opened through the oxide layer (22). The surface of oxide layer (22) is nonuniformly substantially roughened. A layer of metal (24) such as aluminum is formed over the oxide layer (22) and extends into the aperture (32) for contact with a portion of the device (10). The layer of metal (24) has increased granular structure and a roughened exterior surface to provide enhanced electromigration properties.
摘要翻译：该说明书公开了一种方法和装置，其中电路元件（10）形成在半导体本体（12）的表面上。在电路元件（10）上施加一层氧化物（22）。通过氧化物层（22）打开孔（32）。氧化物层（22）的表面不均匀地粗糙化。在氧化物层（22）之上形成诸如铝的金属层（24），并且延伸到孔（32）中以与装置（10）的一部分接触。金属层（24）具有增加的颗粒结构和粗糙的外表面，以提供增强的电迁移性能。

10. 发明授权

US4589196A Contacts for VLSI devices using direct-reacted silicide 失效
标题翻译：使用直接反应硅化物的VLSI器件的触点
公开(公告)号：US4589196A
公开(公告)日：1986-05-20
申请号：US659610
申请日：1984-10-11
申请人： Dirk N. Anderson
发明人： Dirk N. Anderson
IPC分类号： H01L21/285 , H01L21/768 , H01L21/24
CPC分类号： H01L21/28518 , H01L21/76889 , Y10S148/019 , Y10S148/02 , Y10S148/147
摘要： Metal contacts and interconnections for semiconductor integrated circuits are formed by a process using direct-reacted silicide to increase step or sidewall coverage. First a thin layer of titanium or other refractory metal is deposited, extending into a contact hole, then polysilicon is deposited and a preferential etch removes all of the polysilicon except on the vertical sides of steps or apertures. A second thin layer of titanium is deposited, then a heat treatment forms silicide to create conductive sidewalls or a plug. Metal contacts then engage the direct-reacted silicide rather than relying upon step coverage.
摘要翻译：用于半导体集成电路的金属触点和互连通过使用直接反应的硅化物来增加步骤或侧壁覆盖的工艺形成。首先，沉积薄层的钛或其他难熔金属，延伸到接触孔中，然后沉积多晶硅，优先蚀刻除去除了台阶或孔的垂直侧之外的所有多晶硅。沉积第二薄层钛，然后热处理形成硅化物以产生导电侧壁或塞子。然后金属触点接合直接反应的硅化物，而不是依赖于台阶覆盖。

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