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1. 发明授权

US06599789B1 Method of forming a field effect transistor 失效
标题翻译：形成场效应晶体管的方法
公开(公告)号：US06599789B1
公开(公告)日：2003-07-29
申请号：US09713844
申请日：2000-11-15
申请人： Todd R. Abbott , Zhongze Wang , Jigish D. Trivedi , Chih-Chen Cho
发明人： Todd R. Abbott , Zhongze Wang , Jigish D. Trivedi , Chih-Chen Cho
IPC分类号： H01L2184
CPC分类号： H01L29/66651 , H01L21/26533 , H01L29/0653 , H01L29/41766 , H01L29/66636
摘要： A method of forming a field effect transistor includes forming a channel region within bulk semiconductive material of a semiconductor substrate. Source/drain regions are formed on opposing sides of the channel region. An insulative dielectric region is formed within the bulk semiconductive material proximately beneath at least one of the source/drain regions. A method of forming a field effect transistor includes providing a semiconductor-on-insulator substrate, said substrate comprising a layer of semiconductive material formed over a layer of insulative material. All of a portion of the semiconductive material layer and all of the insulative material layer directly beneath the portion are removed thereby creating a void in the semiconductive material layer and the insulative material layer. Semiconductive channel material is formed within the void. Opposing source/drain regions are provided laterally proximate the channel material. A gate is formed over the channel material. Integrated circuitry includes a bulk semiconductor substrate. A field effect transistor thereon includes a gate, a channel region in the bulk semiconductor substrate, and source/drain regions within the substrate on opposing sides of the channel region. A field isolation region is formed in the bulk semiconductor substrate and laterally adjoins with one of the source/drain regions. The field isolation region includes a portion which extends beneath at least some of the one source/drain region. Other aspects are contemplated.
摘要翻译：形成场效应晶体管的方法包括在半导体衬底的本体半导体材料内形成沟道区。源极/漏极区域形成在沟道区域的相对侧上。绝缘电介质区域在本体半导体材料内形成在源极/漏极区域中的至少一个附近。形成场效应晶体管的方法包括提供绝缘体上半导体衬底，所述衬底包括在绝缘材料层上形成的半导体材料层。半导体材料层的一部分和直接在该部分正下方的所有绝缘材料层被除去，从而在半导体材料层和绝缘材料层中产生空隙。半导体通道材料形成在空隙内。相邻的源极/漏极区域横向靠近通道材料提供。在通道材料上形成一个栅极。集成电路包括体半导体衬底。其中的场效应晶体管包括栅极，体半导体衬底中的沟道区，以及在沟道区的相对侧上的衬底内的源极/漏极区。在体半导体衬底中形成场隔离区域，并且与源极/漏极区域之一横向邻接。场隔离区域包括在一个源极/漏极区域中的至少一些的下方延伸的部分。考虑其他方面。

2. 发明授权

US06583518B2 Cross-diffusion resistant dual-polycide semiconductor structure and method 有权
公开(公告)号：US06583518B2
公开(公告)日：2003-06-24
申请号：US09945380
申请日：2001-08-31
申请人： Jigish D. Trivedi , Zhongze Wang , Todd R. Abbott , Chih-Chen Cho
发明人： Jigish D. Trivedi , Zhongze Wang , Todd R. Abbott , Chih-Chen Cho
IPC分类号： H01L2711
CPC分类号： H01L27/11 , H01L27/1104 , Y10S257/903 , Y10S257/904
摘要： A dual-polycide semiconductor structure and method for forming the same having reduced dopant cross-diffusion. A conductive layer is formed over a polysilicon layer having a first region doped with a first dopant and a second region adjoining the first region at an interface doped with a second dopant. A region of discontinuity is then formed in the conductive layer located away from the interface. The conductive layer formed over the polysilicon gate overlaps the interface to provide electrical continuity between the first and second regions of the polysilicon gate, but also includes a region of discontinuity to reduce dopant cross-diffusion.

3. 发明授权

US07153731B2 Method of forming a field effect transistor with halo implant regions 有权
标题翻译：用卤素注入区域形成场效应晶体管的方法
公开(公告)号：US07153731B2
公开(公告)日：2006-12-26
申请号：US10236662
申请日：2002-09-05
申请人： Todd R. Abbott , Zhongze Wang , Jigish D. Trivedi , Chih-Chen Cho
发明人： Todd R. Abbott , Zhongze Wang , Jigish D. Trivedi , Chih-Chen Cho
IPC分类号： H01L21/336 , H01L21/331 , H01L21/76 , H01L21/3205 , H01L21/44
CPC分类号： H01L29/66651 , H01L21/26533 , H01L29/0653 , H01L29/41766 , H01L29/66636
摘要： A method of forming a field effect transistor includes forming a channel region within bulk semiconductive material of a semiconductor substrate. Source/drain regions are formed on opposing sides of the channel region. An insulative dielectric region is formed within the bulk semiconductive material proximately beneath at least one of the source/drain regions. A method of forming a field effect transistor includes providing a semiconductor-on-insulator substrate, said substrate comprising a layer of semiconductive material formed over a layer of insulative material. All of a portion of the semiconductive material layer and all of the insulative material layer directly beneath the portion are removed thereby creating a void in the semiconductive material layer and the insulative material layer. Semiconductive channel material is formed within the void. Opposing source/drain regions are provided laterally proximate the channel material. A gate is formed over the channel material. Integrated circuitry includes a bulk semiconductor substrate. A field effect transistor thereon includes a gate, a channel region in the bulk semiconductor substrate, and source/drain regions within the substrate on opposing sides of the channel region. A field isolation region is formed in the bulk semiconductor substrate and laterally adjoins with one of the source/drain regions. The field isolation region includes a portion which extends beneath at least some of the one source/drain region. Other aspects are contemplated.
摘要翻译：形成场效应晶体管的方法包括在半导体衬底的本体半导体材料内形成沟道区。源极/漏极区域形成在沟道区域的相对侧上。绝缘电介质区域在本体半导体材料内形成在源极/漏极区域中的至少一个附近。形成场效应晶体管的方法包括提供绝缘体上半导体衬底，所述衬底包括在绝缘材料层上形成的半导体材料层。半导体材料层的一部分和直接在该部分正下方的所有绝缘材料层被除去，从而在半导体材料层和绝缘材料层中产生空隙。半导体通道材料形成在空隙内。相邻的源极/漏极区域横向靠近通道材料提供。在通道材料上形成一个栅极。集成电路包括体半导体衬底。其中的场效应晶体管包括栅极，体半导体衬底中的沟道区，以及在沟道区的相对侧上的衬底内的源极/漏极区。在体半导体衬底中形成场隔离区域，并且与源极/漏极区域之一横向邻接。场隔离区域包括在一个源极/漏极区域中的至少一些的下方延伸的部分。考虑其他方面。

4. 发明授权

US07112482B2 Method of forming a field effect transistor 有权
公开(公告)号：US07112482B2
公开(公告)日：2006-09-26
申请号：US10901538
申请日：2004-07-28
申请人： Todd R. Abbott , Zhongze Wang , Jigish D. Trivedi , Chih-Chen Cho
发明人： Todd R. Abbott , Zhongze Wang , Jigish D. Trivedi , Chih-Chen Cho
IPC分类号： H01L21/8238
CPC分类号： H01L29/66651 , H01L21/26533 , H01L29/0653 , H01L29/41766 , H01L29/66636
摘要： A method of forming a field effect transistor includes forming a channel region within bulk semiconductive material of a semiconductor substrate. Source/drain regions are formed on opposing sides of the channel region. An insulative dielectric region is formed within the bulk semiconductive material proximately beneath at least one of the source/drain regions. A method of forming a field effect transistor includes providing a semiconductor-on-insulator substrate, said substrate comprising a layer of semiconductive material formed over a layer of insulative material. All of a portion of the semiconductive material layer and all of the insulative material layer directly beneath the portion are removed thereby creating a void in the semiconductive material layer and the insulative material layer. Semiconductive channel material is formed within the void. Opposing source/drain regions are provided laterally proximate the channel material. A gate is formed over the channel material. Integrated circuitry includes a bulk semiconductor substrate. A field effect transistor thereon includes a gate, a channel region in the bulk semiconductor substrate, and source/drain regions within the substrate on opposing sides of the channel region. A field isolation region is formed in the bulk semiconductor substrate and laterally adjoins with one of the source/drain regions. The field isolation region includes a portion which extends beneath at least some of the one source/drain region. Other aspects are contemplated.

5. 发明授权

US06987291B2 Integrated transistor circuitry 失效
标题翻译：集成晶体管电路
公开(公告)号：US06987291B2
公开(公告)日：2006-01-17
申请号：US10236282
申请日：2002-09-05
申请人： Todd R. Abbott , Zhongze Wang , Jigish D. Trivedi , Chih-Chen Cho
发明人： Todd R. Abbott , Zhongze Wang , Jigish D. Trivedi , Chih-Chen Cho
IPC分类号： H01L31/0328
CPC分类号： H01L29/66651 , H01L21/26533 , H01L29/0653 , H01L29/41766 , H01L29/66636
摘要： Integrated circuitry includes a bulk semiconductor substrate. A field effect transistor thereon includes a gate, a channel region in the bulk semiconductor substrate, and source/drain regions within the substrate on opposing sides of the channel region. A field isolation region is formed in the bulk semiconductor substrate and laterally adjoins with one of the source/drain regions. The field isolation region includes a portion which extends beneath at least some of the one source/drain region. Other aspects are contemplated.
摘要翻译：集成电路包括体半导体衬底。其中的场效应晶体管包括栅极，体半导体衬底中的沟道区，以及在沟道区的相对侧上的衬底内的源极/漏极区。在体半导体衬底中形成场隔离区域，并且与源极/漏极区域之一横向邻接。场隔离区域包括在一个源极/漏极区域中的至少一些的下方延伸的部分。考虑其他方面。

6. 发明授权

US06613617B2 Cross-diffusion resistant dual-polycide semiconductor structure and method 失效
公开(公告)号：US06613617B2
公开(公告)日：2003-09-02
申请号：US10282420
申请日：2002-10-28
申请人： Jigish D. Trivedi , Zhongze Wang , Todd R. Abbott , Chih-Chen Cho
发明人： Jigish D. Trivedi , Zhongze Wang , Todd R. Abbott , Chih-Chen Cho
IPC分类号： H01L2184
CPC分类号： H01L27/11 , H01L27/1104 , Y10S257/903 , Y10S257/904
摘要： A dual-polycide semiconductor structure and method for forming the same having reduced dopant cross-diffusion. A conductive layer is formed over a polysilicon layer having a first region doped with a first dopant and a second region adjoining the first region at an interface doped with a second dopant. A region of discontinuity is then formed in the conductive layer located away from the interface. The conductive layer formed over the polysilicon gate overlaps the interface to provide electrical continuity between the first and second regions of the polysilicon gate, but also includes a region of discontinuity to reduce dopant cross-diffusion.

7. 发明授权

US06962841B2 Suppression of cross diffusion and gate depletion 有权
公开(公告)号：US06962841B2
公开(公告)日：2005-11-08
申请号：US10659081
申请日：2003-09-10
申请人： John D. Trivedi , Zhongze Wang , Chih-Chen Cho , Mike Violette , Todd R. Abbott
发明人： John D. Trivedi , Zhongze Wang , Chih-Chen Cho , Mike Violette , Todd R. Abbott
IPC分类号： G11C11/412 , H01L21/8238 , H01L21/8244 , H01L27/11
CPC分类号： G11C11/412 , H01L21/823842 , H01L21/823871 , H01L21/823878 , H01L27/11 , H01L27/1104
摘要： According to the present invention, an ultrathin buried diffusion barrier layer (UBDBL) is formed over all or part of the doped polysilicon layer of a polysilicide structure composed of the polycrystalline silicon film and an overlying film of a metal, metal silicide, or metal nitride. More specifically, according to one embodiment of the present invention, a memory cell is provided comprising a semiconductor substrate, a P well, an N well, an N type active region, a P type active region, an isolation region, a polysilicide gate electrode structure, and a diffusion barrier layer. The P well is formed in the semiconductor substrate. The N well is formed in the semiconductor substrate adjacent to the P well. The N type active region is defined in the P well and the P type active region is defined in the N well. The isolation region is arranged to isolate the N type active region from the P type active region. The polysilicide gate electrode structure is composed of a polycrystalline silicon film and an overlying metal, metal silicide, or metal nitride film. The polycrystalline silicon film comprises an N+ polysilicon layer formed with the N type active region and a P+ polysilicon layer formed with the P type active region. The diffusion barrier layer is formed in the polysilicide gate electrode structure over a substantial portion of the polycrystalline silicon film between the polycrystalline silicon film and the metal, metal silicide, or metal nitride film.

8. 发明授权

US06812529B2 Suppression of cross diffusion and gate depletion 有权
公开(公告)号：US06812529B2
公开(公告)日：2004-11-02
申请号：US09808864
申请日：2001-03-15
申请人： John D. Trivedi , Zhongze Wang , Chih-Chen Cho , Mike Violette , Todd R. Abbott
发明人： John D. Trivedi , Zhongze Wang , Chih-Chen Cho , Mike Violette , Todd R. Abbott
IPC分类号： H01L2949
CPC分类号： G11C11/412 , H01L21/823842 , H01L21/823871 , H01L21/823878 , H01L27/11 , H01L27/1104
摘要： According to the present invention, an ultrathin buried diffusion barrier layer (UBDBL) is formed over all or part of the doped polysilicon layer of a polysilicide structure composed of the polycrystalline silicon film and an overlying film of a metal, metal silicide, or metal nitride. More specifically, according to one embodiment of the present invention, a memory cell is provided comprising a semiconductor substrate, a P well, an N well, an N type active region, a P type active region, an isolation region, a polysilicide gate electrode structure, and a diffusion barrier layer. The P well is formed in the semiconductor substrate. The N well is formed in the semiconductor substrate adjacent to the P well. The N type active region is defined in the P well and the P type active region is defined in the N well. The isolation region is arranged to isolate the N type active region from the P type active region. The polysilicide gate electrode structure is composed of a polycrystalline silicon film and an overlying metal, metal silicide, or metal nitride film. The polycrystalline silicon film comprises an N+ polysilicon layer formed with the N type active region and a P+ polysilicon layer formed with the P type active region. The diffusion barrier layer is formed in the polysilicide gate electrode structure over a substantial portion of the polycrystalline silicon film between the polycrystalline silicon film and the metal, metal silicide, or metal nitride film.

9. 发明申请

US20050151198A1 Apparatus for increasing SRAM cell capacitance with metal fill 审中-公开
标题翻译：用于通过金属填充增加SRAM单元电容的装置
公开(公告)号：US20050151198A1
公开(公告)日：2005-07-14
申请号：US11057302
申请日：2005-02-11
申请人： Zhongze Wang , Chih-Chen Cho
发明人： Zhongze Wang , Chih-Chen Cho
IPC分类号： G11C11/412 , H01L21/768 , H01L21/8244 , H01L27/11 , H01L29/76
CPC分类号： G11C11/4125 , G11C11/412 , H01L21/76885 , H01L27/11 , H01L27/1104
摘要： A static random access memory cell with metal fill to form capacitors for increasing the capacitance of the memory cell. More specifically, a semiconductor device including a structure having an upper surface and a contact surface formed at the upper surface of the structure. A dielectric material is formed over the contact surface with a first conductive node and a second conductive node extending beyond the dielectric material. Dielectric spacers are formed around the first and second conductive nodes and conductive elements are formed between the dielectric spacers. The conductive elements and spacers form capacitors without implementing additional masking steps.
摘要翻译：具有金属填充的静态随机存取存储器单元以形成用于增加存储单元的电容的电容器。更具体地说，一种半导体器件，包括具有形成在该结构的上表面上的上表面和接触表面的结构。介电材料在接触表面上与第一导电节点和延伸超出电介质材料的第二导电节点形成。电介质隔板围绕第一和第二导电节点形成，并且导电元件形成在电介质间隔件之间。导电元件和间隔件形成电容器而不实施附加的掩蔽步骤。

10. 发明授权

US07169662B2 Methods for making semiconductor structures having high-speed areas and high-density areas 有权
标题翻译：制造具有高速区域和高密度区域的半导体结构的方法
公开(公告)号：US07169662B2
公开(公告)日：2007-01-30
申请号：US10699256
申请日：2003-10-30
申请人： Chih-Chen Cho , Zhongze Wang
发明人： Chih-Chen Cho , Zhongze Wang
IPC分类号： H01L21/8238
CPC分类号： H01L21/76897 , H01L21/76895 , H01L27/105 , H01L27/1052 , H01L27/11
摘要： Methods for making a semiconductor structure are discussed. The methods include forming openings in a high-density area and a high-speed area, and forming a metallization layer simultaneously into the high-density area and the high-speed area. The metallization layer includes a combination of substances and compounds that reduce vertical resistance, reduce horizontal resistance, and inhibit cross-diffusion.
摘要翻译：讨论制造半导体结构的方法。所述方法包括在高密度区域和高速区域中形成开口，并且同时形成金属化层到高密度区域和高速区域中。金属化层包括降低垂直电阻，降低水平电阻和抑制交叉扩散的物质和化合物的组合。

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