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1. 发明申请

US20070211539A1 METHOD FOR RESETTING THRESHOLD VOLTAGE OF NON-VOLATILE MEMORY 审中-公开
标题翻译：用于复位非易失性存储器阈值电压的方法
公开(公告)号：US20070211539A1
公开(公告)日：2007-09-13
申请号：US11531682
申请日：2006-09-13
申请人： Chih-Kai Kang , Hann-Ping Hwang , Chih-Ming Chao , Shi-Hsien Cheng
发明人： Chih-Kai Kang , Hann-Ping Hwang , Chih-Ming Chao , Shi-Hsien Cheng
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C16/0466 , G11C16/14
摘要： A method for resetting threshold voltage of a non-volatile memory is provided. The method is suitable for a non-volatile memory having a plurality of memory cells. Each memory cell includes a gate and a charge trapping layer. The method includes erasing the non-volatile memory by Fowler-Nordheim (FN) tunneling effect until erasure saturation. The non-volatile memory has a uniform saturation threshold voltage.
摘要翻译：提供了一种用于重置非易失性存储器的阈值电压的方法。该方法适用于具有多个存储单元的非易失性存储器。每个存储单元包括栅极和电荷俘获层。该方法包括通过Fowler-Nordheim（FN）隧道效应擦除非易失性存储器直到擦除饱和。非易失性存储器具有均匀的饱和阈值电压。

2. 发明申请

US20070206424A1 METHOD FOR ERASING NON-VOLATILE MEMORY 审中-公开
标题翻译：用于擦除非易失性存储器的方法
公开(公告)号：US20070206424A1
公开(公告)日：2007-09-06
申请号：US11531690
申请日：2006-09-13
申请人： Chao-Wei Kuo , Chih-Ming Chao , Hann-Ping Hwang
发明人： Chao-Wei Kuo , Chih-Ming Chao , Hann-Ping Hwang
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C16/14
摘要： A method for erasing a non-volatile memory is provided. The non-volatile memory includes a first conductive type substrate, a second conductive type well disposed in the first conductive type substrate, a first conductive type well disposed on the second conductive type well, and a memory cell disposed on the first conductive type substrate. The memory cell includes a charge trapping layer and a gate. The erasing method includes the following steps. A first voltage is applied to the gate, a second voltage is applied to the first conductive type substrate, and the second conductive type well is floating. The second voltage is large enough to induce a substrate hot hole effect. The holes are injected into the charge trapping layer by applying the first voltage.
摘要翻译：提供了一种擦除非易失性存储器的方法。非易失性存储器包括第一导电型衬底，布置在第一导电类型衬底中的第二导电类型阱，布置在第二导电类型阱上的第一导电类型阱以及设置在第一导电类型衬底上的存储单元。存储单元包括电荷捕获层和栅极。擦除方法包括以下步骤。向栅极施加第一电压，将第二电压施加到第一导电型衬底，并且第二导电类型阱浮置。第二电压足够大以引起基板热孔效应。通过施加第一电压将空穴注入电荷俘获层。

3. 发明申请

US20070108503A1 NON-VOLATILE MEMORY AND MANUFACTURING METHOD AND OPERATING METHOD THEREOF 审中-公开
标题翻译：非易失性存储器及其制造方法及其工作方法
公开(公告)号：US20070108503A1
公开(公告)日：2007-05-17
申请号：US11308498
申请日：2006-03-30
申请人： Shi-Hsien Chen , Yung-Chung Lee , Hann-Ping Hwang , Saysamone Pittikoun
发明人： Shi-Hsien Chen , Yung-Chung Lee , Hann-Ping Hwang , Saysamone Pittikoun
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11568
摘要： A non-volatile memory is provided. At least two bit lines are disposed in a substrate. The two bit lines are arranged in parallel and extend in a first direction. A plurality of select gate structures is disposed on the substrate between the two bit lines respectively. The select gate structures are arranged in parallel and extend in a first direction. A gap is disposed between each two neighboring select gate structures. A plurality of control gate lines is disposed on the substrate and fills in the gaps between two neighboring select gate structures respectively. The control gate lines are arranged in parallel and extend in a second direction, which crosses the first direction. A plurality of charge storage layers is disposed between the select gate structures and control gate lines respectively.
摘要翻译：提供非易失性存储器。至少两条位线设置在基板中。两条位线平行布置并沿第一方向延伸。多个选择栅极结构分别设置在两个位线之间的衬底上。选择栅极结构平行布置并沿第一方向延伸。在两个相邻的选择栅结构之间设置间隙。多个控制栅极线设置在基板上，分别填充两个相邻的选择栅极结构之间的间隙。控制栅极线平行布置并沿与第一方向交叉的第二方向延伸。多个电荷存储层分别设置在选择栅极结构和控制栅极线之间。

4. 发明申请

US20070108504A1 NON-VOLATILE MEMORY AND MANUFACTURING METHOD AND OPERATING METHOD THEREOF 审中-公开
标题翻译：非易失性存储器及其制造方法及其工作方法
公开(公告)号：US20070108504A1
公开(公告)日：2007-05-17
申请号：US11308507
申请日：2006-03-31
申请人： Yung-Chung Lee , Hann-Ping Hwang , Chin-Chung Wang , Chih-Ming Chao , Saysamone Pittikoun , Chih-Chen Cho
发明人： Yung-Chung Lee , Hann-Ping Hwang , Chin-Chung Wang , Chih-Ming Chao , Saysamone Pittikoun , Chih-Chen Cho
IPC分类号： H01L29/788 , H01L29/76 , H01L21/336
CPC分类号： H01L29/792 , G11C16/0483 , H01L27/115 , H01L27/11568 , H01L29/42344
摘要： A non-volatile memory having a plurality of gate structures, a plurality of charge storage layers and two doped regions is provided. The gate structures are disposed on the substrate and connected in series. The charge storage layers are disposed between every two neighboring gate structures respectively. The gate structures and the charge storage layers form a memory cell column. The two doped regions are disposed in the substrate at both sides of the memory cell column.
摘要翻译：提供具有多个栅极结构，多个电荷存储层和两个掺杂区域的非易失性存储器。栅极结构设置在基板上并串联连接。电荷存储层分别设置在每两个相邻栅极结构之间。栅极结构和电荷存储层形成存储单元列。两个掺杂区域在存储单元列的两侧设置在基板中。

5. 发明申请

US20100052036A1 MEMORY DEVICE AND MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR DEVICE 审中-公开
标题翻译：存储器件及其制造方法和半导体器件
公开(公告)号：US20100052036A1
公开(公告)日：2010-03-04
申请号：US12545054
申请日：2009-08-20
申请人： Cheng-Hong Lee , Chih-Ming Chao , Hann-Ping Hwang , Che-Huai Hung
发明人： Cheng-Hong Lee , Chih-Ming Chao , Hann-Ping Hwang , Che-Huai Hung
IPC分类号： H01L29/788 , H01L21/8239 , H01L29/792
CPC分类号： H01L27/11573
摘要： A semiconductor device disposed on a substrate is provided. The semiconductor device includes two isolation structures, a first conductive layer, a charge trapping layer, a second conductive layer and a gate dielectric layer. The two isolation structures are disposed in the substrate to define an active area. The second conductive layer across the two isolation structures is disposed on the substrate. The first conductive layer is disposed between the two isolation structures and between the second conductive layer and the substrate. The second conductive layer electrically connects with the first conductive layer. The charge trapping layer is disposed on the substrate. The gate dielectric layer is disposed between the first conductive layer and the substrate. An interface between the two isolation structures and the first conductive layer is covered by the charge trapping layer to restrain the kink effect.
摘要翻译：设置在基板上的半导体器件。半导体器件包括两个隔离结构，第一导电层，电荷俘获层，第二导电层和栅极电介质层。两个隔离结构设置在基板中以限定有效区域。穿过两个隔离结构的第二导电层设置在基板上。第一导电层设置在两个隔离结构之间以及第二导电层与衬底之间。第二导电层与第一导电层电连接。电荷捕获层设置在基板上。栅电介质层设置在第一导电层和衬底之间。两个隔离结构和第一导电层之间的界面被电荷俘获层覆盖以抑制扭结效应。

6. 发明申请

US20070090453A1 NON-VOLATILE MEMORY AND MANUFACTURING METHOD AND OPERATING METHOD THEREOF 审中-公开
标题翻译：非易失性存储器及其制造方法及其工作方法
公开(公告)号：US20070090453A1
公开(公告)日：2007-04-26
申请号：US11307804
申请日：2006-02-23
申请人： Yung-Chung Lee , Shi-Shien Chen , Hann-Ping Hwang
发明人： Yung-Chung Lee , Shi-Shien Chen , Hann-Ping Hwang
IPC分类号： H01L29/94
CPC分类号： H01L29/7881 , H01L27/115 , H01L27/11556 , H01L27/11568 , H01L29/792 , H01L29/7926
摘要： A non-volatile memory unit includes a substrate, a conductive layer, a charge storage layer, a first doped regions, two second doped regions, a first bit line and a second bit line. Wherein, there is a trench in the substrate, the conductive layer is disposed in the substrate and filled the trench. The charge storage layer is disposed between the conductive layer and the substrate. The first doped region is disposed in the substrate below the trench, and the second doped regions are disposed in the substrate on the two sides of the trench respectively. Plural control gates are located above the select gates and aligned in parallel and extend in a second direction. The first bit line and the second bit line are disposed on the substrate and electrically connected to the two second doped regions respectively and parallel to each other.
摘要翻译：非易失性存储单元包括衬底，导电层，电荷存储层，第一掺杂区，两个第二掺杂区，第一位线和第二位线。其中，在衬底中存在沟槽，导电层设置在衬底中并填充沟槽。电荷存储层设置在导电层和基板之间。第一掺杂区域设置在沟槽下方的衬底中，并且第二掺杂区域分别设置在沟槽两侧的衬底中。多个控制门位于选择门上方并且平行排列并沿第二方向延伸。第一位线和第二位线设置在基板上并分别电连接到两个第二掺杂区域并且彼此平行。

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