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1. 发明授权

US06791200B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US06791200B2
公开(公告)日：2004-09-14
申请号：US10322626
申请日：2002-12-19
申请人： Koji Nii
发明人： Koji Nii
IPC分类号： H01L2711
CPC分类号： H01L27/1104 , Y10S257/903 , Y10S257/905
摘要： An SRAM includes a plurality of memory cells which are arranged in an extension direction of bit lines, each of which has a long edge and a short edge, an extension direction of the short edge being equal to the extension direction of the bit lines. A distance between polysilicon wirings which are formed in one of the memory cells and which become gates of NMOS transistors arranged in the extension direction of the bit lines, respectively, differs from a distance between the polysilicon wiring and the polysilicon wiring which becomes a gate of an NMOS transistor formed in the other memory cell.
摘要翻译： SRAM包括沿位线的延伸方向布置的多个存储单元，每个位线具有长边和短边，短边的延伸方向等于位线的延伸方向。形成在一个存储单元中并且分别成为位线延伸方向上的NMOS晶体管的栅极的多晶硅布线之间的距离与多晶硅布线和成为栅极的多晶硅布线之间的距离不同形成在另一个存储单元中的NMOS晶体管。

2. 发明授权

US06710465B2 Scalable two transistor memory device 有权
标题翻译：可扩展的两个晶体管存储器件
公开(公告)号：US06710465B2
公开(公告)日：2004-03-23
申请号：US10345161
申请日：2003-01-16
申请人： Seungheon Song , Woosik Kim , Hokyu Kang
发明人： Seungheon Song , Woosik Kim , Hokyu Kang
IPC分类号： H01L2711
CPC分类号： G11C16/0433 , H01L27/115 , H01L27/11521 , H01L29/788 , Y10S257/904
摘要： A Scalable Two-Transistor Memory (STTM) cell array having a 4F2 unit cell area, where F is the minimum feature size. The data lines and the bit lines alternate and are adjacent to each other along the Y-axis direction, and the word lines are laid out along the X-axis direction. Each STTM cell consists of a floating gate MOS sensing transistor at the surface of a semiconductor substrate, with a vertical double sidewall gate multiple tunnel junction barrier programming MOS transistor on top of the sensing transistor. A data line connects all source regions of the programming transistors and a bit line connects all the source/drain regions of the sensing transistors in a column direction. A word line connects all double sidewall gate regions of programming transistors in a row direction. This invention also deals with a column addressing circuit as well as the driving method for the circuit.
摘要翻译：具有4F 2单位单元面积的可扩展双晶体管存储器（STTM）单元阵列，其中F是最小特征尺寸。数据线和位线沿着Y轴方向交替并彼此相邻，并且字线沿着X轴方向布置。每个STTM单元由在半导体衬底的表面处的浮置栅极MOS感测晶体管组成，在感测晶体管顶部具有垂直双侧壁栅极多隧道结屏障编程MOS晶体管。数据线连接编程晶体管的所有源极区域，并且位线沿列方向连接感测晶体管的所有源极/漏极区域。字线将编程晶体管的所有双侧壁栅极区域沿行方向连接。本发明还涉及列寻址电路以及该电路的驱动方法。

3. 发明授权

US06624526B2 Compact SRAM cell incorporating refractory metal-silicon-nitrogen resistive elements and method for fabricating 有权
$Compact SRAM cell incorporating refractory metal-silicon-nitrogen resistive elements and method for fabricating$
标题翻译：含有难熔金属 - 硅 - 氮电阻元件的紧凑SRAM单元及其制造方法
公开(公告)号：US06624526B2
公开(公告)日：2003-09-23
申请号：US09872325
申请日：2001-06-01
申请人： Lawrence Clevenger , Louis Hsu , Li-Kong Wang
发明人： Lawrence Clevenger , Louis Hsu , Li-Kong Wang
IPC分类号： H01L2711
CPC分类号： H01L27/11 , H01L27/1112 , Y10S257/903 , Y10S257/904
摘要： A compact SRAM cell that incorporates refractory metal-silicon-nitrogen resistive elements as its pull-up transistors is described which includes a semi-conducting substrate, a pair of NMOS transfer devices formed vertically on the sidewalls of an etched substrate by a metal conductor providing electrical communication between an n+ region in the substrate and a bitline on top, a pair of pull-down nMOS devices on the substrate connected to ground interconnects, and a pair of vertical high-resistive elements formed of a refractory metal-silicon-nitrogen and function as a load for connecting to Vdd. The invention further describes a method for fabricating such compact SRAM cell.
摘要翻译：描述了一种紧凑的SRAM单元，其包含难熔金属硅 - 氮电阻元件作为其上拉晶体管，其包括半导体衬底，一对NMOS传输器件，其通过金属导体在蚀刻衬底的侧壁上垂直形成，提供衬底中n +区和顶部位线之间的电气通信，连接到接地互连的衬底上的一对下拉nMOS器件以及由难熔金属硅形成的一对垂直高电阻元件 - 并且作为连接到Vdd的负载。本发明还描述了一种用于制造这种紧凑的SRAM单元的方法。

4. 发明授权

US06232670B1 Semiconductor memory device and method of fabricating the same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US06232670B1
公开(公告)日：2001-05-15
申请号：US09361043
申请日：1999-07-26
申请人： Takashi Kumagai , Junichi Karasawa , Kazuo Tanaka , Kunio Watanabe
发明人： Takashi Kumagai , Junichi Karasawa , Kazuo Tanaka , Kunio Watanabe
IPC分类号： H01L2711
CPC分类号： H01L27/1104
摘要： First and second memory cells of an SRAM comprises first, second, and third conductive layers. The first conductive layer is a gate electrode for a first load transistor and a first driver transistor. The second conductive layer diverges from the first conductive layer on a field oxide region and is electrically connected to a second driver transistor active region. The third conductive layer is a gate electrode for a second load transistor and a second driver transistor. The third conductive layer is electrically connected to a first load transistor active region. The pattern of the first, second, and third conductive layers of the second memory cell is a rotated pattern of the first, second, and third conductive layers in the first memory cell at an angle of 180 degrees around an axis perpendicular to the main surface of a semiconductor substrate.
摘要翻译： SRAM的第一和第二存储单元包括第一，第二和第三导电层。第一导电层是用于第一负载晶体管和第一驱动晶体管的栅电极。第二导电层从场氧化物区域上的第一导电层发散，并且电连接到第二驱动器晶体管有源区。第三导电层是用于第二负载晶体管的栅电极和第二驱动晶体管。第三导电层电连接到第一负载晶体管有源区。第二存储单元的第一，第二和第三导电层的图案是第一存储单元中的第一，第二和第三导电层的旋转图案，围绕垂直于主表面的轴以180度的角度的半导体衬底。

5. 发明授权

US06218724B1 Thin film transistor used in semiconductor memory for achieving reduction in power consumption 失效
标题翻译：用于半导体存储器中的薄膜晶体管用于实现功耗的降低
公开(公告)号：US06218724B1
公开(公告)日：2001-04-17
申请号：US08879449
申请日：1997-06-20
申请人： Motomu Ukita , Toshihiko Hirose , Shigeto Maegawa
发明人： Motomu Ukita , Toshihiko Hirose , Shigeto Maegawa
IPC分类号： H01L2711
CPC分类号： G11C5/147 , Y10S257/904
摘要： An SRAM according to the present invention includes a voltage-down circuit and an internal circuit. The voltage-down circuit includes three resistors, two PMOS transistors and an NMOS transistor. One PMOS transistor directly applies an external power supply voltage to the internal circuit. The NMOS transistor applies a voltage obtained by reducing the external power supply voltage by a threshold voltage thereof to the internal circuit. The value of a predetermined voltage as a condition for switching such application of the voltage by the PMOS transistor and application Of the voltage by the NMOS transistor is determined by the resistance ratio of the two resistors. Each of the three resistors is formed by a plurality of resistance elements of one kind. Thus, even if the process parameter varies, the ratio of the resistance values of the two resistors which determines the switching point can be kept constant, thereby preventing variation in switching point.
摘要翻译：根据本发明的SRAM包括降压电路和内部电路。降压电路包括三个电阻，两个PMOS晶体管和一个NMOS晶体管。一个PMOS晶体管直接将外部电源电压施加到内部电路。 NMOS晶体管将通过将外部电源电压降低到其内部电路的阈值电压来获得的电压。作为用于切换由PMOS晶体管施加电压的条件的预定电压的值和由NMOS晶体管施加的电压的值由两个电阻器的电阻比确定。三个电阻器中的每一个由多个一种电阻元件形成。因此，即使过程参数变化，也可以将确定开关点的两个电阻器的电阻值的比率保持为一定，从而防止开关点的变化。

6. 发明授权

US06184588B2 SRAM cell having bit line shorter than word line 有权
标题翻译：具有比字线短的位线的SRAM单元
公开(公告)号：US06184588B2
公开(公告)日：2001-02-06
申请号：US09298840
申请日：1999-04-26
申请人： Han-soo Kim , Kyeong-tae Kim
发明人： Han-soo Kim , Kyeong-tae Kim
IPC分类号： H01L2711
CPC分类号： H01L27/11 , H01L27/1112 , Y10S257/904
摘要： An SRAM cell having a word line shorter than a bit line is provided. First and second driver transistors having first and second gate electrodes parallel to each other are formed on a semiconductor substrate, and a third gate electrode shared by first and second transfer transistors is formed between the first and the second gate electrodes. A word line electrically connected to the third electrode is perpendicular to the first and the second gate electrodes, and a pair of bit lines electrically connected to drain areas of the first and the second transfer transistors are perpendicular to the word line. Also, a pair of ground lines are electrically connected to the source areas of the first and the second driver transistors, and are parallel to the bit lines.
摘要翻译：提供具有比位线短的字线的SRAM单元。具有彼此平行的第一和第二栅电极的第一和第二驱动晶体管形成在半导体衬底上，并且在第一和第二栅电极之间形成由第一和第二转移晶体管共享的第三栅电极。电连接到第三电极的字线垂直于第一和第二栅电极，并且电连接到第一和第二转移晶体管的漏极区域的一对位线垂直于字线。此外，一对接地线与第一和第二驱动晶体管的源极区域电连接，并且与位线平行。

7. 发明授权

US06828689B2 Semiconductor latches and SRAM devices 有权
公开(公告)号：US06828689B2
公开(公告)日：2004-12-07
申请号：US10413810
申请日：2003-04-14
申请人： Raminda U. Madurawe
发明人： Raminda U. Madurawe
IPC分类号： H01L2711
CPC分类号： H01L27/11 , H01L27/0688 , H01L27/1108 , Y10S257/903
摘要： A new Static Random Access Memory (SRAM) cell using Thin Film Transistors (TFT) is disclosed. In a first embodiment, an SRAM cell comprises a strong inverter and a strong access device constructed on a semiconductor substrate layer, and a weak inverter and a weak access device constructed in a semiconductor thin film layer located vertically above the strong devices. The strong devices are used in the data read and write paths, and the weak devices are used for latch feed-back and sector data erase. This first embodiment is used for high density and high speed memory applications. In a second embodiment, an SRAM cell comprises thin film inverters and thin film access devices constructed in a semiconductor thin film layer located substantially above logic transistors. The TFT SRAM cell is buried above the logic gates of an Integrated Circuit to consume no extra Silicon real estate. This second embodiment is used for slow access and Look-Up-Tables type memory applications.

8. 发明授权

US06750555B2 Semiconductor SRAM having linear diffusion regions 有权
标题翻译：具有线性扩散区域的半导体SRAM
公开(公告)号：US06750555B2
公开(公告)日：2004-06-15
申请号：US10263914
申请日：2002-10-03
申请人： Katsuji Satomi , Hiroyuki Yamauchi
发明人： Katsuji Satomi , Hiroyuki Yamauchi
IPC分类号： H01L2711
CPC分类号： H01L27/1104
摘要： A semiconductor memory device has a SRAM memory cell comprising: a first inverter including a first nMOS transistor and a first pMOS transistor; a second inverter including a second nMOS transistor and a second pMOS transistor; a third nMOS transistor; and a fourth nMOS transistor, wherein a first diffusion region forming the first and third nMOS transistors and a second diffusion region forming the second and fourth nMOS transistors, respectively, are arranged in linear shapes without having any bent part, and driving capabilities of the first and second nMOS transistors are higher than those of the third and fourth nMOS transistors.
摘要翻译：半导体存储器件具有SRAM存储单元，其包括：第一反相器，包括第一nMOS晶体管和第一pMOS晶体管; 包括第二nMOS晶体管和第二pMOS晶体管的第二反相器; 第三个nMOS晶体管; 以及第四nMOS晶体管，其中分别形成所述第一和第三nMOS晶体管的第一扩散区域和形成所述第二和第四nMOS晶体管的第二扩散区域被布置成线形，而没有任何弯曲部分，并且所述第一扩散区域的驱动能力并且第二nMOS晶体管高于第三和第四nMOS晶体管的晶体管。

9. 发明授权

US06559510B1 Static random access memory device 失效
标题翻译：静态随机存取存储器
公开(公告)号：US06559510B1
公开(公告)日：2003-05-06
申请号：US09709216
申请日：2000-11-09
申请人： Hiroaki Yokoyama
发明人： Hiroaki Yokoyama
IPC分类号： H01L2711
CPC分类号： H01L27/11 , H01L27/1104 , Y10S257/904 , Y10S257/921
摘要： A Static Random Access Memory (SRAM) device includes at least a transfer transistor, a driving transistor and a load resistor which are commonly connected to a node. A well has a first conductive type, and is placed on a substrate. A first impurity region has a second conductive type opposite to the first conductive type, and is placed in the well. A second impurity region has the first conductive type and has higher impurity concentration than the well, and is placed at a lower portion of the first impurity region. The node is composed of at least the first impurity region and the second impurity region.
摘要翻译：静态随机存取存储器（SRAM）装置至少包括通常连接到节点的传输晶体管，驱动晶体管和负载电阻器。阱具有第一导电类型，并且放置在基板上。第一杂质区具有与第一导电类型相反的第二导电类型，并且放置在阱中。第二杂质区域具有第一导电类型并且具有比阱更高的杂质浓度，并且被放置在第一杂质区域的下部。该节点至少由第一杂质区和第二杂质区构成。

10. 发明授权

US06479905B1 Full CMOS SRAM cell 有权
标题翻译：全CMOS SRAM单元
公开(公告)号：US06479905B1
公开(公告)日：2002-11-12
申请号：US09620666
申请日：2000-07-20
申请人： Jun-eui Song
发明人： Jun-eui Song
IPC分类号： H01L2711
CPC分类号： H01L27/11 , H01L27/1104 , Y10S257/904
摘要： A full CMOS SRAM cell includes first and second active regions formed in a semiconductor substrate. A word line traverses first and second areas of the second active region, and first and second gate electrodes are arranged to be perpendicular to the word line. The first and second gate electrodes are parallel to each other and traverse the first and second active regions, respectively. A power line is electrically connected to a first common source region and is arranged parallel to the word line, the first common source region being the first active region between the first gate electrode and the second gate electrode. A ground line is electrically connected to a second common source region and is arranged parallel to the word line, the second common source region being the second active region between the first gate electrode and the second gate electrode. First and second bit lines are arranged to be perpendicular to the word line and parallel to each other.
摘要翻译：全CMOS SRAM单元包括形成在半导体衬底中的第一和第二有源区。字线穿过第二有源区域的第一和第二区域，并且第一和第二栅电极被布置成垂直于字线。第一和第二栅电极彼此平行并横穿第一和第二有源区。电源线电连接到第一公共源极区域并且平行于字线布置，第一公共源极区域是第一栅极电极和第二栅极电极之间的第一有源区域。接地线电连接到第二公共源极区域并且平行于字线布置，第二公共源极区域是第一栅极电极和第二栅极电极之间的第二有源区域。第一和第二位线被布置成垂直于字线并且彼此平行。

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