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1. 发明申请

US20090166318A1 Method of Fabricating an Integrated Circuit 审中-公开
标题翻译：制造集成电路的方法
公开(公告)号：US20090166318A1
公开(公告)日：2009-07-02
申请号：US11966975
申请日：2007-12-28
申请人： Mihel Seitz , Stephan Wege , Mirko Vogt , Juergen Voelkel
发明人： Mihel Seitz , Stephan Wege , Mirko Vogt , Juergen Voelkel
IPC分类号： H01B13/00 , H01L21/306 , B32B3/00
CPC分类号： H01L21/0332 , Y10T428/24355
摘要： A method of fabricating an integrated circuit includes providing a hard mask that includes at least one first layer and one second layer. An etching step is patterned using the hard mask, and a removal step is performed using an etchant in order to at least partially remove the first layer. The first layer and the second layer are configured in such a way that the first layer is etched by the etchant with a higher etch rate than the second layer.
摘要翻译：一种制造集成电路的方法包括提供包括至少一个第一层和一层第二层的硬掩模。使用硬掩模对蚀刻步骤进行图案化，并且使用蚀刻剂进行去除步骤，以便至少部分地去除第一层。第一层和第二层被配置成使得第一层被蚀刻剂以比第二层更高的蚀刻速率蚀刻。

2. 发明申请

US20050202626A1 Method for fabricating a semiconductor structure 有权
标题翻译：半导体结构的制造方法
公开(公告)号：US20050202626A1
公开(公告)日：2005-09-15
申请号：US11071532
申请日：2005-03-04
申请人： Mihel Seitz , Stephan Wege
发明人： Mihel Seitz , Stephan Wege
IPC分类号： H01L21/308 , H01L21/31 , H01L21/3205 , H01L21/4763 , H01L21/8234 , H01L21/8242 , H01L21/8244 , H01L27/108
CPC分类号： H01L29/66181 , H01L27/1087
摘要： The present invention provides a method for fabricating a semiconductor structure having the steps of: providing a semiconductor substrate (1) made of silicon with a first hard mask layer (10; 10′) made of silicon oxide and an overlying second hard mask layer (15; 15′) made of silicon; providing a masking layer (30; 30′) made of silicon oxide above and laterally with respect to the second hard mask layer (15; 15′) made of silicon and above an uncovered edge region (RB) of the semiconductor substrate (1); providing a photoresist mask (25) above the masking layer (30; 30′) with openings corresponding from trenches (DT) to be formed in the semiconductor substrate (1); opening the masking layer (30; 30′) in a first plasma process using the photoresist mask (25), the edge region (RB) being covered by a shielding device (AR); opening the first hard mask layer (10; 10′) and second hard mask layer (15; 15′) in a second and third plasma process; and forming the trenches (DT) in the semiconductor substrate (1) in a fourth plasma process using the opened first hard mask layer (10; 10′); the edge region (RB) not being covered by the shielding device (AR) in the second to fourth plasma processes.
摘要翻译：本发明提供一种半导体结构的制造方法，其特征在于，具有以下步骤：提供由硅制成的半导体衬底（1），所述半导体衬底（1）由氧化硅制成的第一硬掩模层（10; 10'）和覆盖的第二硬掩模层 15; 15'）由硅制成; 在半导体衬底（1）的未覆盖边缘区域（RB）上方提供相对于由硅制成的第二硬掩模层（15; 15'）上方和侧面的由氧化硅制成的掩模层（30; 30'）， ; 在所述掩模层（30; 30'）上方设置与所述半导体衬底（1）中形成的沟槽（DT）对应的开口的光致抗蚀剂掩模（25）; 在使用光致抗蚀剂掩模（25）的第一等离子体工艺中打开掩模层（30; 30'），边缘区域（RB）被屏蔽装置（AR）覆盖; 在第二和第三等离子体工艺中打开第一硬掩模层（10; 10'）和第二硬掩模层（15; 15'）; 以及使用所述打开的第一硬掩模层（10; 10'）在第四等离子体工艺中在所述半导体衬底（1）中形成所述沟槽（DT）。在第二至第四等离子体处理中边缘区域（RB）不被屏蔽装置（AR）覆盖。

3. 发明授权

US07105404B2 Method for fabricating a semiconductor structure 有权
标题翻译：半导体结构的制造方法
公开(公告)号：US07105404B2
公开(公告)日：2006-09-12
申请号：US11071532
申请日：2005-03-04
申请人： Mihel Seitz , Stephan Wege
发明人： Mihel Seitz , Stephan Wege
IPC分类号： H01L21/8242
CPC分类号： H01L29/66181 , H01L27/1087
摘要： The present invention provides a method for fabricating a semiconductor structure having the steps of: providing a semiconductor substrate (1) made of silicon with a first hard mask layer (10; 10′) made of silicon oxide and an overlying second hard mask layer (15; 15′) made of silicon; providing a masking layer (30; 30′) made of silicon oxide above and laterally with respect to the second hard mask layer (15; 15′) made of silicon and above an uncovered edge region (RB) of the semiconductor substrate (1); providing a photoresist mask (25) above the masking layer (30; 30′) with openings corresponding from trenches (DT) to be formed in the semiconductor substrate (1); opening the masking layer (30; 30′) in a first plasma process using the photoresist mask (25), the edge region (RB) being covered by a shielding device (AR); opening the first hard mask layer (10; 10′) and second hard mask layer (15; 15′) in a second and third plasma process; and forming the trenches (DT) in the semiconductor substrate (1) in a fourth plasma process using the opened first hard mask layer (10; 10′); the edge region (RB) not being covered by the shielding device (AR) in the second to fourth plasma processes.
摘要翻译：本发明提供一种半导体结构的制造方法，其特征在于，具有以下步骤：提供由硅制成的半导体衬底（1），所述半导体衬底（1）由氧化硅制成的第一硬掩模层（10; 10'）和覆盖的第二硬掩模层 15; 15'）由硅制成; 在半导体衬底（1）的未覆盖边缘区域（RB）上方提供相对于由硅制成的第二硬掩模层（15; 15'）上方和侧面的由氧化硅制成的掩模层（30; 30'）， ; 在所述掩模层（30; 30'）上方设置与所述半导体衬底（1）中形成的沟槽（DT）对应的开口的光致抗蚀剂掩模（25）; 在使用光致抗蚀剂掩模（25）的第一等离子体工艺中打开掩模层（30; 30'），边缘区域（RB）被屏蔽装置（AR）覆盖; 在第二和第三等离子体工艺中打开第一硬掩模层（10; 10'）和第二硬掩模层（15; 15'）; 以及使用所述打开的第一硬掩模层（10; 10'）在第四等离子体工艺中在所述半导体衬底（1）中形成所述沟槽（DT）。在第二至第四等离子体处理中边缘区域（RB）不被屏蔽装置（AR）覆盖。

4. 发明授权

US07034352B2 DRAM with very shallow trench isolation 失效
标题翻译： DRAM具有非常浅的沟槽隔离
公开(公告)号：US07034352B2
公开(公告)日：2006-04-25
申请号：US10777332
申请日：2004-02-11
申请人： Mihel Seitz , Venkatachalam C. Jaiprakash
发明人： Mihel Seitz , Venkatachalam C. Jaiprakash
IPC分类号： H01L27/108
CPC分类号： H01L27/10867 , H01L21/76224 , H01L27/10864
摘要： The methods and structures of the present invention involve providing a vertical dynamic random access memory (DRAM) cell device comprising a buried strap which can be laterally constrained, thereby maintaining freedom from cross talk, even at 6F2 scaling, in the absence of adjacent Shallow Trench Isolation (STI). The methods and structures of the present invention involve the further recognition that the STI can therefore be vertically confined, freed of any need to extend down below the level of the buried strap. The reduction of the buried strap to 1F width and the concomitant reduction in the depth of the STI together permit a significantly reduced aspect ratio, permitting critically improved manufacturability.
摘要翻译：本发明的方法和结构包括提供垂直动态随机存取存储器（DRAM）单元装置，其包括可以被横向约束的埋地带，从而即使在6F2缩放下，在没有相邻的浅沟槽的情况下也可以保持免受串扰的自由隔离（STI）。本发明的方法和结构涉及进一步的认识，因此STI可以被垂直地限制，而不需要向下延伸到埋藏带的水平以下。将掩埋带减少到1F宽度并且伴随着STI的深度的降低允许显着减小的纵横比，从而允许严格改进的可制造性。

5. 发明授权

US06960514B2 Pitcher-shaped active area for field effect transistor and method of forming same 失效
标题翻译：投币型场效应晶体管及其形成方法
公开(公告)号：US06960514B2
公开(公告)日：2005-11-01
申请号：US10803395
申请日：2004-03-18
申请人： Jochen Beintner , Rama Divakaruni , Johnathan Faltermeier , Philip L. Flaitz , Oleg Gluschenkov , Carol J. Heenan , Rajarao Jammy , Byeong Kim , Mihel Seitz , Akira Sudo , Yoichi Takegawa
发明人： Jochen Beintner , Rama Divakaruni , Johnathan Faltermeier , Philip L. Flaitz , Oleg Gluschenkov , Carol J. Heenan , Rajarao Jammy , Byeong Kim , Mihel Seitz , Akira Sudo , Yoichi Takegawa
IPC分类号： H01L21/762
CPC分类号： H01L21/76224
摘要： An improved pitcher-shaped active area for a field effect transistor that, for a given gate length, achieves an increase in transistor on-current, a decrease in transistor serial resistance, and a decrease in contact resistance. The pitcher-shaped active area structure includes at least two shallow trench insulator (STI) structures formed into a substrate that defines an active area structure, which includes a widened top portion with a larger width than a bottom portion. An improved fabrication method for forming the improved pitcher-shaped active area is also described that implements a step to form STI structure divots followed by a step to migrate substrate material into at least portions of the divots, thereby forming a widened top portion of the active area structure. The fabrication method of present invention forms the pitcher-shaped active area without the use of lithography, and therefore, is not limited by the smallest ground rules of lithography tooling.
摘要翻译：对于给定的栅极长度，对于晶体管导通电流的增加，晶体管串联电阻的降低和接触电阻的降低，用于场效应晶体管的改进的投池形有源区域。投球形有源区结构包括形成在衬底中的至少两个浅沟槽绝缘体（STI）结构，其限定有源区域结构，其包括宽度比底部宽的加宽顶部部分。还描述了一种用于形成改进的捕鱼器活性区域的改进的制造方法，其实现了形成STI结构图形的步骤，随后是将基板材料迁移到图案的至少部分中的步骤，从而形成活动的加宽顶部区域结构。本发明的制造方法在不使用光刻的情况下形成投手型有源区域，因此不受光刻工具的最小基准规则的限制。

6. 发明授权

US06849496B2 DRAM with vertical transistor and trench capacitor memory cells and method of fabrication 失效
标题翻译： DRAM具有垂直晶体管和沟槽电容器存储单元及其制造方法
公开(公告)号：US06849496B2
公开(公告)日：2005-02-01
申请号：US10617511
申请日：2003-07-11
申请人： Venkatachalam C. Jaiprakash , Mihel Seitz , Norbert Arnold
发明人： Venkatachalam C. Jaiprakash , Mihel Seitz , Norbert Arnold
IPC分类号： H01L21/8242
CPC分类号： H01L27/10867
摘要： A semiconductor Dynamic Random Access Memory (DRAM) cell is fabricated using a vertical access transistor and a storage capacitor formed in a vertical trench. A Shallow Trench Isolation (STI) region is used as a masking region to confine the channel region of the access transistor, the first and second output regions of the access transistor, and a strap region connecting the second output region to the storage capacitor, to a narrow portion of the trench. The so confined second output region of the access transistor has reduced leakage to similar second output regions of adjacent memory cells. Adjacent memory cells can then be placed closer to one another without an increase in leakage and cross-talk between adjacent memory cells.
摘要翻译：使用垂直存取晶体管和形成在垂直沟槽中的存储电容器制造半导体动态随机存取存储器（DRAM）单元。浅沟槽隔离（STI）区域用作屏蔽区域，以将存取晶体管的沟道区域，存取晶体管的第一和第二输出区域以及将第二输出区域连接到存储电容器的带区域限制到沟槽的一小部分。存取晶体管的如此限制的第二输出区域减少了泄漏到相邻存储器单元的类似的第二输出区域。相邻的存储器单元然后可以彼此更靠近地放置，而不会增加相邻存储单元之间的泄漏和串扰。

7. 发明授权

US06706634B1 Control of separation between transfer gate and storage node in vertical DRAM 失效
标题翻译：控制垂直DRAM中传输门和存储节点之间的分离
公开(公告)号：US06706634B1
公开(公告)日：2004-03-16
申请号：US09664825
申请日：2000-09-19
申请人： Mihel Seitz , Andreas Knorr , Irene McStay
发明人： Mihel Seitz , Andreas Knorr , Irene McStay
IPC分类号： H01L21302
CPC分类号： H01L27/10867 , H01L27/10864
摘要： A high density plasma deposition process for eliminating or reducing a zipper-like profile of opened-up voids in a poly trench fill by controlling separation between a transfer gate and storage node in a vertical DRAM, comprising: etching a recess or trench into poly Si of a semiconductor chip; forming a pattern of SiN liner using a mask transfer process for formation of a single sided strap design; removing the SiN liner and etching adjacent collar oxide away from a top part of the trench; depositing a high density plasma (HDP) polysilicon layer in the trench by flowing either SiH4 or SiH4+H2 in an inert ambient; employing a photoresist in the trench and removing the high density plasma polysilicon layer from a top surface of the semiconductor to avoid shorting in the gate conductor either by spinning on resist and subsequent chemical mechanical polishing or chemical mechanical downstream etchback of the polysilicon layer; and stripping the photoresist and depositing a top trench oxide by high density plasma.
摘要翻译：一种高密度等离子体沉积工艺，用于通过控制垂直DRAM中的转移栅极和存储节点之间的分离来消除或减少多沟槽填充物中的开放空隙的拉链状轮廓，包括：将凹槽或沟槽蚀刻成多晶硅形成半导体芯片;使用用于形成单面带设计的掩模转移工艺形成SiN衬垫的图案;去除SiN衬垫并将邻近的环氧化物蚀刻离开沟槽的顶部;沉积高密度等离子体（HDP ）多晶硅层，通过在惰性环境中流过SiH 4或SiH 4 + H 2;在沟槽中使用光致抗蚀剂并从半导体的顶表面去除高密度等离子体多晶硅层，以避免通过旋转在栅极导体中短路在抗蚀剂和随后的化学机械抛光或多晶硅层的化学机械下游回蚀; 并且蚀刻光致抗蚀剂并通过高密度等离子体沉积顶部沟槽氧化物。

8. 发明授权

US06531377B2 Method for high aspect ratio gap fill using sequential HDP-CVD 有权
标题翻译：使用连续HDP-CVD的高纵横比间隙填充方法
公开(公告)号：US06531377B2
公开(公告)日：2003-03-11
申请号：US09904799
申请日：2001-07-13
申请人： Andreas Knorr , Mihel Seitz
发明人： Andreas Knorr , Mihel Seitz
IPC分类号： H01L2100
CPC分类号： H01L21/76229
摘要： A method of providing isolation between element regions of a semiconductor memory device (200). Isolation trenches (211) are filled using several sequential anisotropic insulating material (216/226/230) HPD-CVD deposition processes, with each deposition process being followed by an isotropic etch back to remove the insulating material (216/226/230) from the isolation trench (211) sidewalls. A nitride liner (225) may be deposited after isolation trench (211) formation. A top portion of the nitride liner (225) may be removed prior to the deposition of the top insulating material (230) layer.
摘要翻译：一种在半导体存储器件（200）的元件区域之间提供隔离的方法。使用几种顺序各向异性绝缘材料（216/226/230）HPD-CVD沉积工艺填充绝缘沟槽（211），每个沉积工艺之后是各向同性蚀刻，以从绝缘材料（216/226/230）中除去绝缘材料隔离沟槽（211）侧壁。可以在形成隔离沟槽（211）之后沉积氮化物衬垫（225）。可以在沉积顶部绝缘材料（230）层之前去除氮化物衬垫（225）的顶部部分。

9. 发明授权

US06667223B2 High aspect ratio high density plasma (HDP) oxide gapfill method in a lines and space pattern 有权
标题翻译：高宽比高密度等离子体（HDP）氧化物间隙填充法在线和空间图案中
公开(公告)号：US06667223B2
公开(公告)日：2003-12-23
申请号：US09905357
申请日：2001-07-13
申请人： Mihel Seitz
发明人： Mihel Seitz
IPC分类号： H01L2176
CPC分类号： H01L21/76229
摘要： A method of providing isolation between active areas of memory cells in a memory device having a plurality of isolation trenches (115) separating the active areas, comprising depositing a first insulating material (116) and forming a resist (120) over the first insulating material (116) over at least the trenches (115), leaving a first top portion of the first insulating material (116) exposed. At least a second top portion of the first insulating material (116) is removed, the resist (120) is removed, and a second insulating material (216) is deposited over the wafer (100) to completely fill the isolation trenches (115).
摘要翻译：一种在具有分离有源区域的多个隔离沟槽（115）的存储器件中提供存储器单元的有源区之间的隔离的方法，包括沉积第一绝缘材料（116）并在所述第一绝缘材料上形成抗蚀剂（120）（116）至少在所述沟槽（115）之上，留下所述第一绝缘材料（116）的第一顶部部分露出。去除第一绝缘材料（116）的至少第二顶部部分，去除抗蚀剂（120），并且在晶片（100）上沉积第二绝缘材料（216）以完全填充隔离沟槽（115）。

10. 发明授权

US06294423B1 Method for forming and filling isolation trenches 有权
标题翻译：用于形成和填充隔离沟槽的方法
公开(公告)号：US06294423B1
公开(公告)日：2001-09-25
申请号：US09718211
申请日：2000-11-21
申请人： Rajeev Malik , Mihel Seitz , Andreas Knorr
发明人： Rajeev Malik , Mihel Seitz , Andreas Knorr
IPC分类号： H01L218242
CPC分类号： H01L21/76229 , H01L27/1087
摘要： A method for forming isolation trenches for a semiconductor device forms, in a substrate, a plurality of trenches having different widths including widths above a threshold size and widths below a threshold size. The plurality of trenches have a same first depth. A masking layer is deposited in the plurality of trenches, the masking layer has a thickness sufficient to both line the trenches with the widths above the threshold size and completely fill the trenches with the widths below the threshold size. A portion of the substrate is exposed at a bottom of the trenches with the widths above the threshold size by etching the masking layer. The plurality of trenches is etched to extend the trenches with the widths above the threshold size to different depths.
摘要翻译：用于形成用于半导体器件的隔离沟槽的方法在衬底中形成具有不同宽度的多个沟槽，所述宽度包括高于阈值尺寸的宽度和低于阈值尺寸的宽度。多个沟槽具有相同的第一深度。掩蔽层沉积在多个沟槽中，掩模层具有足够的厚度以使沟槽线宽度高于阈值尺寸，并以宽度低于阈值尺寸完全填充沟槽。通过蚀刻掩模层，将衬底的一部分暴露在沟槽底部，宽度高于阈值大小。多个沟槽被蚀刻以将具有高于阈值尺寸的宽度的沟槽延伸到不同的深度。

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