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1. 发明授权

US07034352B2 DRAM with very shallow trench isolation 失效
标题翻译： DRAM具有非常浅的沟槽隔离
公开(公告)号：US07034352B2
公开(公告)日：2006-04-25
申请号：US10777332
申请日：2004-02-11
申请人： Mihel Seitz , Venkatachalam C. Jaiprakash
发明人： Mihel Seitz , Venkatachalam C. Jaiprakash
IPC分类号： H01L27/108
CPC分类号： H01L27/10867 , H01L21/76224 , H01L27/10864
摘要： The methods and structures of the present invention involve providing a vertical dynamic random access memory (DRAM) cell device comprising a buried strap which can be laterally constrained, thereby maintaining freedom from cross talk, even at 6F2 scaling, in the absence of adjacent Shallow Trench Isolation (STI). The methods and structures of the present invention involve the further recognition that the STI can therefore be vertically confined, freed of any need to extend down below the level of the buried strap. The reduction of the buried strap to 1F width and the concomitant reduction in the depth of the STI together permit a significantly reduced aspect ratio, permitting critically improved manufacturability.
摘要翻译：本发明的方法和结构包括提供垂直动态随机存取存储器（DRAM）单元装置，其包括可以被横向约束的埋地带，从而即使在6F2缩放下，在没有相邻的浅沟槽的情况下也可以保持免受串扰的自由隔离（STI）。本发明的方法和结构涉及进一步的认识，因此STI可以被垂直地限制，而不需要向下延伸到埋藏带的水平以下。将掩埋带减少到1F宽度并且伴随着STI的深度的降低允许显着减小的纵横比，从而允许严格改进的可制造性。

2. 发明授权

US06849496B2 DRAM with vertical transistor and trench capacitor memory cells and method of fabrication 失效
标题翻译： DRAM具有垂直晶体管和沟槽电容器存储单元及其制造方法
公开(公告)号：US06849496B2
公开(公告)日：2005-02-01
申请号：US10617511
申请日：2003-07-11
申请人： Venkatachalam C. Jaiprakash , Mihel Seitz , Norbert Arnold
发明人： Venkatachalam C. Jaiprakash , Mihel Seitz , Norbert Arnold
IPC分类号： H01L21/8242
CPC分类号： H01L27/10867
摘要： A semiconductor Dynamic Random Access Memory (DRAM) cell is fabricated using a vertical access transistor and a storage capacitor formed in a vertical trench. A Shallow Trench Isolation (STI) region is used as a masking region to confine the channel region of the access transistor, the first and second output regions of the access transistor, and a strap region connecting the second output region to the storage capacitor, to a narrow portion of the trench. The so confined second output region of the access transistor has reduced leakage to similar second output regions of adjacent memory cells. Adjacent memory cells can then be placed closer to one another without an increase in leakage and cross-talk between adjacent memory cells.
摘要翻译：使用垂直存取晶体管和形成在垂直沟槽中的存储电容器制造半导体动态随机存取存储器（DRAM）单元。浅沟槽隔离（STI）区域用作屏蔽区域，以将存取晶体管的沟道区域，存取晶体管的第一和第二输出区域以及将第二输出区域连接到存储电容器的带区域限制到沟槽的一小部分。存取晶体管的如此限制的第二输出区域减少了泄漏到相邻存储器单元的类似的第二输出区域。相邻的存储器单元然后可以彼此更靠近地放置，而不会增加相邻存储单元之间的泄漏和串扰。

3. 发明授权

US06621112B2 DRAM with vertical transistor and trench capacitor memory cells and methods of fabrication 失效
标题翻译： DRAM具有垂直晶体管和沟槽电容器存储单元及其制造方法
公开(公告)号：US06621112B2
公开(公告)日：2003-09-16
申请号：US09731343
申请日：2000-12-06
申请人： Venkatachalam C. Jaiprakash , Mihel Seitz , Norbert Arnold
发明人： Venkatachalam C. Jaiprakash , Mihel Seitz , Norbert Arnold
IPC分类号： H01L27108
CPC分类号： H01L27/10867
摘要： A semiconductor Dynamic Random Access Memory (DRAM) cell is fabricated using a vertical access transistor and a storage capacitor formed in a vertical trench. A Shallow Trench Isolation (STI) region is used as a masking region to confine the channel region of the access transistor, the first and second output regions of the access transistor, and a strap region connecting the second output region to the storage capacitor, to a narrow portion of the trench. The so confined second output region of the access transistor has reduced leakage to similar second output regions of adjacent memory cells. Adjacent memory cells can then be placed closer to one another without an increase in leakage and cross-talk between adjacent memory cells.
摘要翻译：使用垂直存取晶体管和形成在垂直沟槽中的存储电容器制造半导体动态随机存取存储器（DRAM）单元。浅沟槽隔离（STI）区域用作屏蔽区域，以将存取晶体管的沟道区域，存取晶体管的第一和第二输出区域以及将第二输出区域连接到存储电容器的带区域限制到沟槽的一小部分。存取晶体管的如此限制的第二输出区域减少了泄漏到相邻存储器单元的类似的第二输出区域。相邻的存储器单元然后可以彼此更靠近地放置，而不会增加相邻存储单元之间的泄漏和串扰。

4. 发明授权

US06509226B1 Process for protecting array top oxide 有权
标题翻译：保护阵列顶部氧化物的方法
公开(公告)号：US06509226B1
公开(公告)日：2003-01-21
申请号：US09670741
申请日：2000-09-27
申请人： Venkatachalam C. Jaiprakash , Jack Mandelman , Ramachandra Divakaruni , Rajeev Malik , Mihel Seitz
发明人： Venkatachalam C. Jaiprakash , Jack Mandelman , Ramachandra Divakaruni , Rajeev Malik , Mihel Seitz
IPC分类号： H01L218242
CPC分类号： H01L27/10861
摘要： Processing of a DRAM device containing vertical MOSFET arrays proceeds through planarization of the array gate conductor (GC) polysilicon of the vertical MOSFET to the top surface of the top oxide. A thin polysilicon layer is deposited over the planarized surface and an active area (M) pad nitride and tetraethyl orthosilicate (TEOS) stack is deposited. The M mask is used to open the pad layer to the silicon surface, and shallow trench isolation (STI) etching is used to form isolation trenches. An AA oxidation is performed, the isolation trenches are filled with high density plasma (HDP) oxide and planarized to the top surface of the AA pad nitride. Following isolation trench (IT) planarization, the AA pad nitride is stripped, with the thin silicon layer serving as an etch stop protecting the underlying top oxide. The etch support (ES) nitride liner is deposited, and the ES mask is patterned to open the support areas. The ES nitride, thin polysilicon layer and top oxide are etched from the exposed areas. A sacrificial oxidation is applied along with well implants, support gate oxidation and support gate polysilicon deposition. Using the etch array (EA) mask, the support gate polysilicon is opened in the array. The ES nitride is removed selective to the underlying silicon layer, protecting the top oxide. The gate stack is deposited and patterned and the process continues to completion.
摘要翻译：包含垂直MOSFET阵列的DRAM器件的处理通过将垂直MOSFET的阵列栅极导体（GC）多晶硅平坦化到顶部氧化物的顶表面进行。在平坦化表面上沉积薄多晶硅层，并沉积有源区（M）衬垫氮化物和原硅酸四乙酯（TEOS）堆叠。 M掩模用于将焊盘层打开到硅表面，并且使用浅沟槽隔离（STI）蚀刻来形成隔离沟槽。执行AA氧化，隔离沟槽填充有高密度等离子体（HDP）氧化物，并且平坦化到AA衬垫氮化物的顶表面。在隔离沟槽（IT）平坦化之后，剥离AA衬垫氮化物，薄硅层用作保护底层氧化物的蚀刻停止层。沉积蚀刻载体（ES）氮化物衬垫，并且将ES掩模图案化以打开支撑区域。从暴露的区域蚀刻ES氮化物，薄多晶硅层和顶部氧化物。牺牲氧化与井注入一起施加，支持栅极氧化和支撑栅极多晶硅沉积。使用蚀刻阵列（EA）掩模，在阵列中打开支撑栅极多晶硅。对于下层硅层选择性地除去ES氮化物，保护顶部氧化物。沉积栅极堆叠并图案化，并且该工艺继续完成。

5. 发明授权

US07928523B2 Non-volatile electromechanical field effect devices and circuits using same and methods of forming same 有权
标题翻译：非易失性机电场效应器件和使用其的电路及其形成方法
公开(公告)号：US07928523B2
公开(公告)日：2011-04-19
申请号：US12512428
申请日：2009-07-30
申请人： Claude L. Bertin , Thomas Rueckes , Brent M. Segal , Bernhard Vogeli , Darren K. Brock , Venkatachalam C. Jaiprakash
发明人： Claude L. Bertin , Thomas Rueckes , Brent M. Segal , Bernhard Vogeli , Darren K. Brock , Venkatachalam C. Jaiprakash
IPC分类号： H01L29/82
CPC分类号： H01L29/78 , B82Y10/00 , B82Y99/00 , G11C7/065 , G11C13/025 , G11C16/0416 , G11C17/16 , G11C17/165 , G11C23/00 , G11C2213/16 , G11C2213/17 , G11C2213/79 , H01H1/0094 , H01L27/10 , H01L27/1052 , H01L27/112 , H01L27/11206 , H01L27/115 , H01L27/286 , H01L29/0665 , H01L29/0673 , H01L29/42324 , H01L51/0048 , H01L51/0052 , H01L51/0508 , Y10S977/708 , Y10S977/724 , Y10S977/742 , Y10S977/762 , Y10S977/936 , Y10S977/938 , Y10S977/94 , Y10S977/943
摘要： Under one aspect, a field effect device includes a gate, a source, and a drain, with a conductive channel between the source and the drain; and a nanotube switch having a corresponding control terminal, said nanotube switch being positioned to control electrical conduction through said conductive channel. Under another aspect, a field effect device includes a gate having a corresponding gate terminal; a source having a corresponding source terminal; a drain having a corresponding drain terminal; a control terminal; and a nanotube switching element positioned between one of the gate, source, and drain and its corresponding terminal and switchable, in response to electrical stimuli at the control terminal and at least one of the gate, source, and drain terminals, between a first non-volatile state that enables current flow between the source and the drain and a second non-volatile state that disables current flow between the source and the drain.
摘要翻译：在一个方面，场效应器件包括栅极，源极和漏极，源极和漏极之间具有导电沟道; 以及纳米管开关，其具有相应的控制端子，所述纳米管开关被定位成控制通过所述导电通道的导电。另一方面，场效应器件包括具有相应栅极端子的栅极; 具有相应源端的源; 具有相应的漏极端子的漏极; 一个控制终端; 以及纳米管开关元件，其位于所述栅极，源极和漏极中的一个与其相应的端子之间，并且响应于所述控制端子和所述栅极，源极和漏极端子中的至少一个，在第一非极性使得能够在源极和漏极之间流动的第一非易失性状态和禁止源极和漏极之间的电流的第二非易失性状态。

6. 发明授权

US07911831B2 Nanotube-on-gate FET structures and applications 有权
标题翻译：纳米管栅极FET结构和应用
公开(公告)号：US07911831B2
公开(公告)日：2011-03-22
申请号：US11939316
申请日：2007-11-13
申请人： Thomas Rueckes , Brent M. Segal , Bernhard Vogeli , Darren K. Brock , Venkatachalam C. Jaiprakash , Claude L. Bertin
发明人： Thomas Rueckes , Brent M. Segal , Bernhard Vogeli , Darren K. Brock , Venkatachalam C. Jaiprakash , Claude L. Bertin
IPC分类号： G11C11/50
CPC分类号： G11C13/025 , B82Y10/00 , G11C23/00 , G11C2213/17 , H01L27/112 , H01L27/11233 , H01L27/115 , H01L27/11521 , H01L51/0048 , H01L51/0052
摘要： Under one aspect, non-volatile transistor device includes a source and drain with a channel in between; a gate structure made of a semiconductive or conductive material disposed over an insulator over the channel; a control gate made of a semiconductive or conductive material; and an electromechanically-deflectable nanotube switching element in fixed contact with one of the gate structure and the control gate structure and is not in fixed contact with the other of the gate structure and the control gate structure. The device has a network of inherent capacitances, including an inherent capacitance of an undeflected nanotube switching element in relation to the gate structure. The network is such that the nanotube switching element is deflectable into contact with the other of the gate structure and the control gate structure in response to signals being applied to the control gate and one of the source region and drain region.
摘要翻译：在一个方面，非易失性晶体管器件包括源极和漏极之间的沟道; 由半导体或导电材料制成的栅极结构，设置在通道上方的绝缘体上; 由半导体或导电材料制成的控制门; 以及与栅极结构和控制栅极结构中的一个固定接触并且不与栅极结构和控制栅极结构中的另一个固定接触的机电偏转的纳米管开关元件。该器件具有固有电容的网络，包括相对于栅极结构的未折射的纳米管开关元件的固有电容。网络使得纳米管开关元件响应于施加到控制栅极和源极区域和漏极区域之一的信号而偏转成与栅极结构和控制栅极结构中的另一个接触。

7. 发明授权

US07274078B2 Devices having vertically-disposed nanofabric articles and methods of making the same 有权
公开(公告)号：US07274078B2
公开(公告)日：2007-09-25
申请号：US11158544
申请日：2005-06-22
申请人： Venkatachalam C. Jaiprakash , Jonathan W. Ward , Thomas Rueckes , Brent M. Segal
发明人： Venkatachalam C. Jaiprakash , Jonathan W. Ward , Thomas Rueckes , Brent M. Segal
IPC分类号： H01L27/14
CPC分类号： G11C13/025 , B81B2203/0338 , B81B2203/04 , B81C1/00142 , B81C2201/0109 , B82Y10/00 , B82Y30/00 , B82Y40/00 , C01B32/162 , C01B2202/02 , C01B2202/22 , G11C11/56 , G11C13/0033 , G11C23/00 , G11C2213/16 , G11C2213/77 , G11C2213/81 , H01H1/0094 , H01L21/76838 , H01L51/0048 , H01L2221/1094 , Y10S977/943
摘要： Electro-mechanical switches and memory cells using vertically-disposed nanofabric articles and methods of making the same are described. An electro-mechanical device, includes a structure having a major horizontal surface and a channel formed therein. A conductive trace is in the channel; and a nanotube article vertically suspended in the channel, in spaced relation to a vertical wall of the channel. The article is electro-mechanically deflectable in a horizontal direction toward the conductive trace. Under certain embodiments, the vertically suspended extent of the nanotube article is defined by a thin film process. Under certain embodiments, the vertically suspended extent of the nanotube article is about 50 nanometers or less. Under certain embodiments, the nanotube article is clamped with a conducting material disposed in porous spaces between some nanotubes of the nanotube article. Under certain embodiments, the nanotube article is formed from a porous nanofabric. Under certain embodiments, the nanotube article is electromechanically deflectable into contact with the conductive trace and the contact is either a volatile state or non-volatile state depending on the device construction. Under certain embodiments, the vertically oriented device is arranged into various forms of three-trace devices. Under certain embodiments, the channel may be used for multiple independent devices, or for devices that share a common electrode.

8. 发明授权

US07015092B2 Methods for forming vertical gate transistors providing improved isolation and alignment of vertical gate contacts 失效
标题翻译：用于形成垂直栅极晶体管的方法，其提供改进的垂直栅极触点的隔离和对准
公开(公告)号：US07015092B2
公开(公告)日：2006-03-21
申请号：US10740026
申请日：2003-12-18
申请人： Venkatachalam C. Jaiprakash , Norbert Arnold
发明人： Venkatachalam C. Jaiprakash , Norbert Arnold
IPC分类号： H01L21/8242
CPC分类号： H01L29/66666 , H01L27/10864 , H01L27/10876 , H01L27/10891
摘要： Methods and devices that provide improved isolation and alignment of gate conductors or gate contacts of vertical transistors in deep trench memory cells. A method for forming a vertical gate contact of a vertical transistor includes an oxide spacer formation process that prevents defects, such as shorts caused by voids filled with polysilicon, resulting from etching processes that are performed during fabrication of a vertical transistor, and enables formation of well-defined contact plugs for gate contacts, providing improved alignment structures.
摘要翻译：提供深沟槽存储单元中垂直晶体管的栅极导体或栅极触点的改进的隔离和对准的方法和装置。用于形成垂直晶体管的垂直栅极接触的方法包括氧化物间隔物形成工艺，其防止由垂直晶体管制造期间进行的蚀刻工艺导致的缺陷，例如由填充有多晶硅的空隙引起的短路，并且能够形成用于门触点的良好定义的接触插头，提供改进的对准结构。

9. 发明授权

US06960818B1 Recessed shallow trench isolation structure nitride liner and method for making same 失效
标题翻译：凹槽浅沟隔离结构氮化物衬垫及其制造方法
公开(公告)号：US06960818B1
公开(公告)日：2005-11-01
申请号：US09000626
申请日：1997-12-30
申请人： Rajesh Rengarajan , Venkatachalam C. Jaiprakash
发明人： Rajesh Rengarajan , Venkatachalam C. Jaiprakash
IPC分类号： H01L21/76 , H01L21/762 , H01L21/8242 , H01L29/00
CPC分类号： H01L27/10861 , H01L21/76224 , Y10S148/05
摘要： A method for reducing hot carrier reliability problems within an integrated circuit device. The method includes forming a shallow trench isolation structure incorporated with the device by filling a trench with a photoresist plug and removing a portion of the photoresist plug to a level below the depth of a channel also incorporated with the device. A nitride liner disposed within the trench under the photoresist plug is then recessed to a level substantially equal to the level of the photoresist material, which is then removed. The method further includes the deposition of oxide fill within the trench, thereby encapsulating the recessed nitride liner.
摘要翻译：一种降低集成电路装置内热载体可靠性问题的方法。该方法包括通过用光致抗蚀剂插塞填充沟槽并且将光致抗蚀剂插塞的一部分移除到还与器件结合的通道的深度的水平面下，形成并入器件的浅沟槽隔离结构。然后将设置在光致抗蚀剂插塞下方的沟槽内的氮化物衬垫凹入到基本上等于光致抗蚀剂材料的水平的水平，然后将其除去。该方法还包括在沟槽内沉积氧化物填充物，从而封装凹陷的氮化物衬垫。

10. 发明授权

US6124141A Non-destructive method and device for measuring the depth of a buried interface 失效
标题翻译：用于测量埋入界面深度的非破坏性方法和装置
公开(公告)号：US6124141A
公开(公告)日：2000-09-26
申请号：US4074
申请日：1998-01-07
申请人： K. Paul Muller , Venkatachalam C. Jaiprakash
发明人： K. Paul Muller , Venkatachalam C. Jaiprakash
IPC分类号： G01B11/02 , G01R31/265 , H01L21/334 , H01L21/66 , G01R31/26
CPC分类号： H01L29/66181 , G01R31/2656 , H01L22/12
摘要： The depth at which the top surface of a buried interface is located is non-destructively determined by FTIR.
摘要翻译：掩埋界面顶表面的深度由FTIR非破坏性决定。

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