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1. 发明授权

US06706634B1 Control of separation between transfer gate and storage node in vertical DRAM 失效
标题翻译：控制垂直DRAM中传输门和存储节点之间的分离
公开(公告)号：US06706634B1
公开(公告)日：2004-03-16
申请号：US09664825
申请日：2000-09-19
申请人： Mihel Seitz , Andreas Knorr , Irene McStay
发明人： Mihel Seitz , Andreas Knorr , Irene McStay
IPC分类号： H01L21302
CPC分类号： H01L27/10867 , H01L27/10864
摘要： A high density plasma deposition process for eliminating or reducing a zipper-like profile of opened-up voids in a poly trench fill by controlling separation between a transfer gate and storage node in a vertical DRAM, comprising: etching a recess or trench into poly Si of a semiconductor chip; forming a pattern of SiN liner using a mask transfer process for formation of a single sided strap design; removing the SiN liner and etching adjacent collar oxide away from a top part of the trench; depositing a high density plasma (HDP) polysilicon layer in the trench by flowing either SiH4 or SiH4+H2 in an inert ambient; employing a photoresist in the trench and removing the high density plasma polysilicon layer from a top surface of the semiconductor to avoid shorting in the gate conductor either by spinning on resist and subsequent chemical mechanical polishing or chemical mechanical downstream etchback of the polysilicon layer; and stripping the photoresist and depositing a top trench oxide by high density plasma.
摘要翻译：一种高密度等离子体沉积工艺，用于通过控制垂直DRAM中的转移栅极和存储节点之间的分离来消除或减少多沟槽填充物中的开放空隙的拉链状轮廓，包括：将凹槽或沟槽蚀刻成多晶硅形成半导体芯片;使用用于形成单面带设计的掩模转移工艺形成SiN衬垫的图案;去除SiN衬垫并将邻近的环氧化物蚀刻离开沟槽的顶部;沉积高密度等离子体（HDP ）多晶硅层，通过在惰性环境中流过SiH 4或SiH 4 + H 2;在沟槽中使用光致抗蚀剂并从半导体的顶表面去除高密度等离子体多晶硅层，以避免通过旋转在栅极导体中短路在抗蚀剂和随后的化学机械抛光或多晶硅层的化学机械下游回蚀; 并且蚀刻光致抗蚀剂并通过高密度等离子体沉积顶部沟槽氧化物。

2. 发明授权

US06555430B1 Process flow for capacitance enhancement in a DRAM trench 失效
标题翻译： DRAM沟槽中电容增强的工艺流程
公开(公告)号：US06555430B1
公开(公告)日：2003-04-29
申请号：US09723420
申请日：2000-11-28
申请人： Michael P. Chudzik , Johnathan Faltermeier , Rajarao Jammy , Stephan Kudelka , Irene McStay , Kenneth T. Settlemyer, Jr. , Helmut Horst Tews
发明人： Michael P. Chudzik , Johnathan Faltermeier , Rajarao Jammy , Stephan Kudelka , Irene McStay , Kenneth T. Settlemyer, Jr. , Helmut Horst Tews
IPC分类号： H01L218242
CPC分类号： H01L27/1087 , H01L28/84 , Y10S438/964
摘要： Methods forming a trench region of a trench capacitor structure having increase surface area are provided. One method includes the steps of forming a discontinuous polysilicon layer on exposed walls of a lower trench region, the discontinuous polysilicon layer having gaps therein which expose portions of said substrate; oxidizing the lower trench region such that the exposed portions of said substrate provided by the gaps in the discontinuous polysilicon layer are oxidized into oxide material which forms a smooth and wavy layer with the discontinuous polysilicon layer; and etching said oxide material so as to form smooth hemispherical grooves on the walls of the trench region.
摘要翻译：提供了形成具有增加的表面积的沟槽电容器结构的沟槽区域的方法。一种方法包括以下步骤：在下沟槽区域的暴露的壁上形成不连续的多晶硅层，所述不连续的多晶硅层在其中具有暴露所述衬底的部分的间隙; 氧化下沟槽区域，使得由不连续多晶硅层中的间隙提供的所述衬底的暴露部分被氧化成与不连续的多晶硅层形成平滑波浪层的氧化物材料; 并蚀刻所述氧化物材料，以在沟槽区域的壁上形成平滑的半球状凹槽。

3. 发明授权

US06458647B1 Process flow for sacrificial collar with poly mask 有权
标题翻译：具有聚面罩的牺牲套管的工艺流程
公开(公告)号：US06458647B1
公开(公告)日：2002-10-01
申请号：US09940761
申请日：2001-08-27
申请人： Helmut Horst Tews , Stephan Kudelka , Irene McStay
发明人： Helmut Horst Tews , Stephan Kudelka , Irene McStay
IPC分类号： H01L218242
CPC分类号： H01L29/66181 , H01L27/1087 , H01L27/11507
摘要： A process for forming a sacrificial collar (116) on the top portion of a deep trench (114). A nitride layer (116) is deposited within the trench (114). A semiconductor layer (120) is deposited over the nitride layer (116). A top portion of the semiconductor layer (120) is doped to form doped semiconductor layer (124). Undoped portions (120) of the semiconductor layer are removed, and the doped semiconductor layer (124) is used to pattern the nitride layer (116), removing the lower portion of nitride layer (116) from within deep trenches (114) and leaving a sacrificial collar (116) at the top of the trenches (114).
摘要翻译：一种用于在深沟槽（114）的顶部上形成牺牲套环（116）的工艺。氮化物层（116）沉积在沟槽（114）内。半导体层（120）沉积在氮化物层（116）上。掺杂半导体层（120）的顶部以形成掺杂半导体层（124）。去除半导体层的未掺杂部分（120），并且使用掺杂半导体层（124）对氮化物层（116）进行图案化，从深沟槽（114）中去除氮化物层（116）的下部并离开在所述沟槽（114）的顶部处的牺牲套环（116）。

4. 发明授权

US06709947B1 Method of area enhancement in capacitor plates 失效
标题翻译：电容器板面积增加方法
公开(公告)号：US06709947B1
公开(公告)日：2004-03-23
申请号：US10314548
申请日：2002-12-06
申请人： Porshia S. Wrschka , Irene McStay
发明人： Porshia S. Wrschka , Irene McStay
IPC分类号： H01L2120
CPC分类号： H01L28/84 , Y10S438/964
摘要： A method and structure for increasing the area and capacitance of both trench and planar integrated circuit capacitors uses Si nodules deposited on a thin dielectric seeding layer that is absorbed during subsequent thermal processing, thereby avoiding a high resistance layer in the capacitor.
摘要翻译：用于增加沟槽和平面集成电路电容器的面积和电容的方法和结构使用沉积在薄电介质晶种层上的Si结节，其在随后的热处理期间被吸收，从而避免了电容器中的高电阻层。

5. 发明授权

US06498061B2 Negative ion implant mask formation for self-aligned, sublithographic resolution patterning for single-sided vertical device formation 失效
标题翻译：用于单面垂直器件形成的自对准，亚光刻分辨率图案的负离子注入掩模形成
公开(公告)号：US06498061B2
公开(公告)日：2002-12-24
申请号：US09730674
申请日：2000-12-06
申请人： Rama Divakaruni , Stephan Kudelka , Helmut Tews , Irene McStay , Kil-Ho Lee , Uwe Schroeder
发明人： Rama Divakaruni , Stephan Kudelka , Helmut Tews , Irene McStay , Kil-Ho Lee , Uwe Schroeder
IPC分类号： H01L218242
CPC分类号： H01L27/10867
摘要： A process for fabricating a single-sided semiconductor deep trench structure filled with polysilicon trench fill material includes the following steps. Form a thin film, silicon nitride, barrier layer over the trench fill material. Deposit a thin film of an amorphous silicon masking layer over the barrier layer. Perform an angled implant into portions of the amorphous silicon masking layer which are not in the shadow of the deep trench. Strip the undoped portions of the amorphous silicon masking layer from the deep trench. Then strip the newly exposed portions of barrier layer exposing a part of the trench fill polysilicon surface and leaving the doped, remainder of the amorphous silicon masking layer exposed. Counterdope the exposed part of the trench fill material. Oxidize exposed portions of the polysilicon trench fill material, and then strip the remainder of the masking layer.
摘要翻译：用于制造填充有多晶硅沟槽填充材料的单面半导体深沟槽结构的工艺包括以下步骤。在沟槽填充材料上形成薄膜，氮化硅，阻挡层。在阻挡层上沉积非晶硅掩模层的薄膜。对非深度沟槽阴影的非晶硅掩模层的部分进行成角度的注入。从深沟槽剥离非晶硅掩模层的未掺杂部分。然后剥离暴露部分沟槽填充多晶硅表面的势垒层的新暴露部分，并且使非晶硅掩模层的掺杂剩余部分露出。反映出暴露部分的沟槽填充材料。氧化多晶硅沟槽填充材料的暴露部分，然后剥离掩模层的其余部分。

6. 发明申请

US20060001162A1 Nitride and polysilicon interface with titanium layer 审中-公开
标题翻译：氮化物和多晶硅界面与钛层
公开(公告)号：US20060001162A1
公开(公告)日：2006-01-05
申请号：US11084724
申请日：2005-03-18
申请人： Ronald Schutz , Werner Robl , Rajeev Malik , Lawrence Clevenger , Oleg Gluschenkov , Cyril Cabral , Roy Iggulden , Yun-Yu Wang , Keith Wong , Irene McStay
发明人： Ronald Schutz , Werner Robl , Rajeev Malik , Lawrence Clevenger , Oleg Gluschenkov , Cyril Cabral , Roy Iggulden , Yun-Yu Wang , Keith Wong , Irene McStay
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L21/7685 , H01L21/28052 , H01L21/28061 , H01L21/76838 , H01L21/76855 , H01L21/823828 , H01L21/823842 , H01L29/4941 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/78 , H01L2221/1078
摘要： A conductive structure in an integrated circuit (12), and a method of forming the structure, is provided that includes a polysilicon layer (30), a thin layer containing titanium over the polysilicon, a tungsten nitride layer (34) over the titanium-containing layer and a tungsten layer over the tungsten nitride layer. The structure also includes a silicon nitride interfacial region (38) between the polysilicon layer and the titanium-containing layer. The structure withstands high-temperature processing without substantial formation of metal silicides in the polysilicon layer (30) and the tungsten layer (32), and provides low interface resistance between the tungsten layer and the polysilicon layer.
摘要翻译：提供集成电路（12）中的导电结构和形成该结构的方法，其包括多晶硅层（30），在多晶硅上含有钛的薄层，在钛 - 钛层上的氮化钨层（34）并且在氮化钨层上形成钨层。该结构还包括在多晶硅层和含钛层之间的氮化硅界面区域（38）。该结构经受高温处理，而在多晶硅层（30）和钨层（32）中基本不形成金属硅化物，并且在钨层和多晶硅层之间提供低的界面电阻。

7. 发明授权

US06905944B2 Sacrificial collar method for improved deep trench processing 失效
标题翻译：壕沟法改善深沟槽加工
公开(公告)号：US06905944B2
公开(公告)日：2005-06-14
申请号：US10249798
申请日：2003-05-08
申请人： Michael Patrick Chudzik , Irene McStay , Helmut Horst Tews , Porshia Shane Wrschka
发明人： Michael Patrick Chudzik , Irene McStay , Helmut Horst Tews , Porshia Shane Wrschka
IPC分类号： H01L21/76 , H01L21/8242
CPC分类号： H01L27/1087
摘要： A method for fabricating a deep trench etched into a semiconductor substrate is provided by the present invention. The trench is divided into an upper portion and a lower portion and the method allows for the lower portion to be processed differently from the upper portion. After the trench is etched into the semiconductor substrate, a nitride layer is formed over a sidewall of the trench. A layer of oxide is then formed over the nitride layer. A filler material is then deposited and recessed to cover the oxide layer in the lower portion of the trench, followed by the removal of the oxide layer from the upper portion of the trench above the filler material. Once the oxide layer is removed from the upper portion of the trench, the filler material can also be removed, while allowing the oxide layer and the nitride layer to remain in the lower portion of the trench. Silicon is selectively deposited on the exposed nitride layer in the upper portion of the trench. The oxide layer and the nitride layer is then removed from the lower portion. Finally, the lower portion of the trench is processed selectively to nitride, e.g. by one or more capacitor forming processes, and then the upper portion of the trench is processed.
摘要翻译：通过本发明提供了蚀刻成半导体衬底的深沟槽的制造方法。沟槽被分成上部和下部，并且该方法允许下部被加工成与上部不同。在沟槽被蚀刻到半导体衬底中之后，在沟槽的侧壁上形成氮化物层。然后在氮化物层上形成一层氧化物。然后将填料材料沉积并凹入以覆盖沟槽下部的氧化物层，然后从填料材料上方的沟槽上部除去氧化物层。一旦从沟槽的上部去除氧化物层，也可以去除填充材料，同时允许氧化物层和氮化物层保留在沟槽的下部。选择性地将硅沉积在沟槽上部的暴露的氮化物层上。然后从下部去除氧化物层和氮化物层。最后，沟槽的下部被选择性地加工成氮化物，例如。通过一个或多个电容器形成工艺，然后处理沟槽的上部。

8. 发明授权

US06620724B1 Low resistivity deep trench fill for DRAM and EDRAM applications 有权
标题翻译：用于DRAM和EDRAM应用的低电阻深沟槽填充
公开(公告)号：US06620724B1
公开(公告)日：2003-09-16
申请号：US10142518
申请日：2002-05-09
申请人： Uwe Schroeder , Helmut Horst Tews , Irene McStay , Manfred Hauf , Matthias Goldbach , Bernhard Sell , Harald Seidl , Dirk Schumann , Rajarao Jammy , Joseph F. Shepard, Jr. , Jean-Marc Rousseau
发明人： Uwe Schroeder , Helmut Horst Tews , Irene McStay , Manfred Hauf , Matthias Goldbach , Bernhard Sell , Harald Seidl , Dirk Schumann , Rajarao Jammy , Joseph F. Shepard, Jr. , Jean-Marc Rousseau
IPC分类号： H01L214763
CPC分类号： H01L28/60 , H01L27/10861
摘要： Semiconductor devices having deep trenches with fill material therein having low resistivity are provided along with methods of fabricating such semiconductor devices.
摘要翻译：提供其具有低电阻率的具有低填充材料的深沟槽的半导体器件以及制造这种半导体器件的方法。

9. 发明授权

US06613642B2 Method for surface roughness enhancement in semiconductor capacitor manufacturing 失效
标题翻译：半导体电容器制造中表面粗糙度增强的方法
公开(公告)号：US06613642B2
公开(公告)日：2003-09-02
申请号：US10016075
申请日：2001-12-13
申请人： Stephen Rahn , Irene McStay , Helmut Horst Tews , Uwe Schroeder , Stephan Kudelka , Rajarao Jammy
发明人： Stephen Rahn , Irene McStay , Helmut Horst Tews , Uwe Schroeder , Stephan Kudelka , Rajarao Jammy
IPC分类号： H01L2120
CPC分类号： H01L27/1087 , H01L28/84 , H01L28/90
摘要： A method for increasing the surface area of an original surface in a semiconductor device is disclosed. In an exemplary embodiment of the invention, the method includes forming a layered mask upon the original surface, the layered mask including a masking layer thereatop having a varying thickness. An isotropic etch is then applied to the layered mask, which isotropic etch further removes exposed portions of the original surface as the layered mask is removed. Thereby, the isotropic etch enhances the non-uniformity of the masking layer and creates a non-uniformity in planarity of the original surface.
摘要翻译：公开了一种用于增加半导体器件中原始表面的表面积的方法。在本发明的示例性实施例中，该方法包括在原始表面上形成分层掩模，该分层掩模包括具有变化厚度的掩模层。然后将各向同性蚀刻施加到分层掩模，其中各向同性蚀刻在去除层状掩模时进一步去除原始表面的暴露部分。因此，各向同性蚀刻增强了掩模层的不均匀性并且产生了原始表面的平坦度的不均匀性。

10. 发明授权

US06559002B1 Rough oxide hard mask for DT surface area enhancement for DT DRAM 失效
标题翻译：用于DT DRAM的DT表面积增强的粗糙氧化物硬掩模
公开(公告)号：US06559002B1
公开(公告)日：2003-05-06
申请号：US10032041
申请日：2001-12-31
申请人： Stephan Kudelka , Helmut Horst Tews , Stephen Rahn , Irene McStay , Uwe Schroeder
发明人： Stephan Kudelka , Helmut Horst Tews , Stephen Rahn , Irene McStay , Uwe Schroeder
IPC分类号： H01L218242
CPC分类号： H01L27/1087 , H01L21/0337 , H01L21/3086 , H01L21/31144 , H01L21/32139 , H01L28/84 , Y10S438/964
摘要： In a process for making a DT DRAM structure, the improvement of providing a surface area enhanced DT below the collar region and node capacitance that does not shrink with decreasing groundrule/cell size, comprising: a) providing a semiconductor substrate having a collar region and an adjacent region below the collar region, the collar region having SiO deposited thereon; b) depositing a SiN liner on said collar region and on the region below the collar; c) depositing a layer of a-Si on the SiN liner to form a micromask; d) subjecting the structure from step c) to an anneal/oxidation step under a wet environment at a sufficient temperature to form a plurality of oxide dot hardmasks; e) subjecting the SiN liner to an etch selective to SiO; f) subjecting the structure from step e) to a Si transfer etch using a chemical dry etch (CDE) selective to SiO to create rough Si surface; g) stripping SiO and the SiN; and forming a node and collar deposition.
摘要翻译：在制造DT DRAM结构的过程中，提高在轴环区域之下提供的表面积增强的DT和不随着降低的底层/单元尺寸而缩小的节点电容，包括：a）提供具有轴环区域和在轴环区域下方的相邻区域，其上沉积有SiO的轴环区域; b）在所述轴环区域和轴环下方的区域上沉积SiN衬垫; c）在SiN衬套上沉积a-Si层以形成微型掩模; d）使所述步骤c）的结构在潮湿环境下在足够的温度下进行退火/氧化步骤，以形成多个氧化物点硬掩模; e）使所述SiN衬底对SiO选择性蚀刻; f）使用对SiO选择性的化学干蚀刻（CDE）来产生粗糙的Si表面的步骤e）到Si转移蚀刻的结构; g）剥离SiO和SiN; 并形成一个节点和项圈沉积。

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