专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20110220805A1 FET RADIATION MONITOR 有权
标题翻译： FET辐射监测器
公开(公告)号：US20110220805A1
公开(公告)日：2011-09-15
申请号：US12719962
申请日：2010-03-09
申请人： Michael Gordon , Steven Koester , Kenneth Rodbell , Jeng-Bang Yau
发明人： Michael Gordon , Steven Koester , Kenneth Rodbell , Jeng-Bang Yau
IPC分类号： G01T1/24 , H01L31/08
CPC分类号： H01L31/119
摘要： A semiconductor device includes a semiconductor substrate; a buried insulator layer disposed on the semiconductor substrate, the buried insulator layer configured to retain an amount of charge in a plurality of charge traps in response to a radiation exposure by the semiconductor device; a semiconductor layer disposed on the buried insulating layer; a second insulator layer disposed on the semiconductor layer; a gate conducting layer disposed on the second insulator layer; and one or more side contacts electrically connected to the semiconductor layer. A method for radiation monitoring, the method includes applying a backgate voltage to a radiation monitor, the radiation monitor comprising a field effect transistor (FET); exposing the radiation monitor to radiation; determining a change in a threshold voltage of the radiation monitor; and determining an amount of radiation exposure based on the change in threshold voltage.
摘要翻译：半导体器件包括半导体衬底; 设置在所述半导体衬底上的掩埋绝缘体层，所述掩埋绝缘体层被配置为响应于所述半导体器件的辐射暴露而将多个电荷量保持在多个电荷阱中; 设置在所述掩埋绝缘层上的半导体层; 设置在所述半导体层上的第二绝缘体层; 设置在所述第二绝缘体层上的栅极导电层; 以及与半导体层电连接的一个或多个侧触点。一种用于辐射监测的方法，所述方法包括将背栅电压施加到辐射监测器，所述辐射监测器包括场效应晶体管（FET）; 将辐射监测仪暴露于辐射; 确定辐射监测器的阈值电压的变化; 以及基于阈值电压的变化确定辐射暴露量。

2. 发明授权

US08080805B2 FET radiation monitor 有权
标题翻译： FET辐射监测器
公开(公告)号：US08080805B2
公开(公告)日：2011-12-20
申请号：US12719962
申请日：2010-03-09
申请人： Michael Gordon , Steven Koester , Kenneth Rodbell , Jeng-Bang Yau
发明人： Michael Gordon , Steven Koester , Kenneth Rodbell , Jeng-Bang Yau
IPC分类号： H01L27/146
CPC分类号： H01L31/119
摘要： A semiconductor device includes a semiconductor substrate; a buried insulator layer disposed on the semiconductor substrate, the buried insulator layer configured to retain an amount of charge in a plurality of charge traps in response to a radiation exposure by the semiconductor device; a semiconductor layer disposed on the buried insulating layer; a second insulator layer disposed on the semiconductor layer; a gate conducting layer disposed on the second insulator layer; and one or more side contacts electrically connected to the semiconductor layer. A method for radiation monitoring, the method includes applying a backgate voltage to a radiation monitor, the radiation monitor comprising a field effect transistor (FET); exposing the radiation monitor to radiation; determining a change in a threshold voltage of the radiation monitor; and determining an amount of radiation exposure based on the change in threshold voltage.
摘要翻译：半导体器件包括半导体衬底; 设置在所述半导体衬底上的掩埋绝缘体层，所述掩埋绝缘体层被配置为响应于所述半导体器件的辐射暴露而将多个电荷量保持在多个电荷阱中; 设置在所述掩埋绝缘层上的半导体层; 设置在所述半导体层上的第二绝缘体层; 设置在所述第二绝缘体层上的栅极导电层; 以及与半导体层电连接的一个或多个侧触点。一种用于辐射监测的方法，所述方法包括将背栅电压施加到辐射监测器，所述辐射监测器包括场效应晶体管（FET）; 将辐射监测仪暴露于辐射; 确定辐射监测器的阈值电压的变化; 以及基于阈值电压的变化确定辐射暴露量。

3. 发明申请

US20070013073A1 Method and structure for reduction of soft error rates in integrated circuits 有权
标题翻译：降低集成电路中软错误率的方法和结构
公开(公告)号：US20070013073A1
公开(公告)日：2007-01-18
申请号：US11183647
申请日：2005-07-18
申请人： Cyril Cabral , Michael Gordon , Kenneth Rodbell
发明人： Cyril Cabral , Michael Gordon , Kenneth Rodbell
IPC分类号： H01L23/52 , H01L23/48 , H01L29/40
CPC分类号： H01L23/556 , H01L21/76801 , H01L21/76834 , H01L21/76838 , H01L23/5329 , H01L23/53295 , H01L23/585 , H01L24/03 , H01L24/05 , H01L24/12 , H01L24/16 , H01L24/45 , H01L24/48 , H01L2224/0401 , H01L2224/04042 , H01L2224/05006 , H01L2224/05554 , H01L2224/05572 , H01L2224/05599 , H01L2224/13007 , H01L2224/13022 , H01L2224/131 , H01L2224/13111 , H01L2224/16 , H01L2224/451 , H01L2224/48227 , H01L2224/48465 , H01L2224/85399 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/0102 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01055 , H01L2924/01057 , H01L2924/01063 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/01084 , H01L2924/01092 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/10253 , H01L2924/1305 , H01L2924/1306 , H01L2924/14 , H01L2924/15174 , H01L2924/15312 , H01L2924/15787 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30107 , H01L2924/3025 , H01L2224/45099 , H01L2924/00 , H01L2224/05552
摘要： A structure and a method for reduction of soft error rates in integrated circuits. The structure including: a semiconductor substrate; and a stack of one or more wiring levels stacked from a lowermost wiring level to an uppermost wiring level, the lowermost wiring level nearer the semiconductor substrate than the uppermost wiring level; and an alpha particle blocking layer on a top surface of the uppermost wiring level of the one or more wiring levels, the blocking layer comprising metal wires and a dielectric material, the blocking layer having a combination of a thickness of the blocking layer and a volume percent of metal wires in the blocking layer sufficient to stop a predetermined percentage of alpha particles of a selected energy or less striking the blocking layer from penetrating into the stack of one or more wiring levels or the substrate.
摘要翻译：降低集成电路中软错误率的结构和方法。该结构包括：半导体衬底; 以及从最下布线电平堆叠到最上布线电平的一个或多个布线电平的堆叠，比最上布线电平更靠近半导体基板的最下布线电平; 以及在所述一个或多个布线层的最上布线层的顶表面上的α粒子阻挡层，所述阻挡层包括金属线和介电材料，所述阻挡层具有阻挡层的厚度和体积阻挡层中的金属线的百分比足以阻止预定百分比的选定能量的α粒子或更少的击穿阻挡层的金属线穿透到一个或多个布线层或衬底的堆叠中。

4. 发明申请

US20050143945A1 Automatic exchange of degraders in accelerated testing of computer chips 失效
标题翻译：自动交换降解器加速电脑芯片测试
公开(公告)号：US20050143945A1
公开(公告)日：2005-06-30
申请号：US10734694
申请日：2003-12-12
申请人： Carl Bohnenkamp , Ethan Cannon , Ethan Cascio , Michael Gordon , Kenneth Rodbell , Theodore Zabel
发明人： Carl Bohnenkamp , Ethan Cannon , Ethan Cascio , Michael Gordon , Kenneth Rodbell , Theodore Zabel
IPC分类号： G06F19/00
CPC分类号： H01L21/68764 , H01L21/67213 , H01L21/68771
摘要： Issues that are addressed in accordance with at least one presently preferred embodiment of the present invention, are: improvements upon the time it takes to physically swap degraders (done previously by hand); the safety involved in doing so, since the degraders become highly radioactive; possible improved energy resolution and beam stability if the accelerator can be left running continuously; and in-situ monitoring of beam current, beam position and stability. Particularly contemplated are methods and arrangements for changing degraders automatically, not manually, and in a safe manner.
摘要翻译：根据本发明的至少一个目前优选的实施例解决的问题是：在物理交换降解器（先前由手工完成）所花费的时间上的改进; 这样做的安全性，因为降解物变得高度放射性; 如果加速器可以连续运行，可能改善能量分辨率和光束稳定性; 并对射束电流，光束位置和稳定性进行现场监测。特别考虑的是自动而不是手动地以安全的方式改变降解器的方法和装置。

5. 发明申请

US20050250319A1 Stabilization of Ni monosilicide thin films in CMOS devices using implantation of ions before silicidation 失效
标题翻译：在硅化物中使用离子注入，在CMOS器件中稳定Ni单硅化物薄膜
公开(公告)号：US20050250319A1
公开(公告)日：2005-11-10
申请号：US10838377
申请日：2004-05-04
申请人： Roy Carruthers , Cedrik Coia , Christophe Detavernier , Christian Lavoie , Kenneth Rodbell
发明人： Roy Carruthers , Cedrik Coia , Christophe Detavernier , Christian Lavoie , Kenneth Rodbell
IPC分类号： H01L21/28 , H01L21/285 , H01L21/336 , H01L21/44
CPC分类号： H01L21/28052 , H01L21/28518 , H01L29/665
摘要： A method for forming a stabilized metal silicide film, e.g., contact (source/drain or gate), that does not substantially agglomerate during subsequent thermal treatments, is provided. In the present invention, ions that are capable of attaching to defects within the Si-containing layer are implanted into the Si-containing layer prior to formation of metal silicide. The implanted ions stabilize the film, because the implants were found to substantially prevent agglomeration or at least delay agglomeration to much higher temperatures than in cases in which no implants were used.
摘要翻译：提供了一种用于形成稳定的金属硅化物膜的方法，例如接触（源极/漏极或栅极），其在随后的热处理期间基本上不附聚。在本发明中，在形成金属硅化物之前，将能够附着到含Si层内的缺陷的离子注入到含Si层中。植入的离子稳定膜，因为发现植入物基本上防止结块或至少延迟聚集到比没有使用植入物的情况下更高的温度。

6. 发明授权

US07186166B2 Fiber embedded polishing pad 失效
标题翻译：光纤嵌入式抛光垫
公开(公告)号：US07186166B2
公开(公告)日：2007-03-06
申请号：US11271744
申请日：2005-11-14
申请人： Shyng-Tsong Chen , Kenneth Davis , Oscar Kai Chi Hsu , Kenneth Rodbell , Jean Vangsness
发明人： Shyng-Tsong Chen , Kenneth Davis , Oscar Kai Chi Hsu , Kenneth Rodbell , Jean Vangsness
IPC分类号： B24B1/00
CPC分类号： B24D3/28 , B24B37/22 , B24B37/24 , B24B37/26 , B24D11/008 , B24D18/00 , B24D18/0009
摘要： A polishing pad having a body comprising fibers embedded in a matrix polymer formed by a reaction of polymer precursors. The loose fibers define and the precursors were mixed first with curatives, then mold into a pad form. The pad may include a thin layer of free fibers at its polishing surface. A segment of at least a portion of the free fibers are embedded in the adjacent body of the polymer and fibers.
摘要翻译：一种抛光垫，其具有包含嵌入在通过聚合物前体的反应形成的基质聚合物中的纤维的主体。松散的纤维定义并且前体与固化剂混合，然后模制成垫形式。衬垫在其抛光表面可以包括薄层的自由纤维。至少一部分自由纤维的片段嵌入在聚合物和纤维的相邻体中。

7. 发明申请

US20060071338A1 Homogeneous Copper Interconnects for BEOL 审中-公开
标题翻译： BEOL的均匀铜互连
公开(公告)号：US20060071338A1
公开(公告)日：2006-04-06
申请号：US10711700
申请日：2004-09-30
申请人： Kevin Petrarca , Mahadevaiyer Krishnan , Michael Lofaro , Kenneth Rodbell
发明人： Kevin Petrarca , Mahadevaiyer Krishnan , Michael Lofaro , Kenneth Rodbell
IPC分类号： H01L23/52
CPC分类号： H01L21/76873 , H01L21/2855 , H01L21/7684 , H01L21/76877
摘要： Defects on the edge of copper interconnects for back end of the line semiconductor devices are alleviated by an interconnect that comprises an impure copper seed layer. The impure copper seed layer covers a barrier layer, which covers an insulating layer that has an opening. Electroplated copper fills the opening in the insulating layer. Through a chemical mechanical polish, the barrier layer, the impure an impure copper seed layer derived from an electroplated copper bath copper seed layer, and the electroplated copper are planarized to the insulating layer.
摘要翻译：通过包括不纯铜种子层的互连可以减轻线半导体器件后端的铜互连边缘的缺陷。不纯铜种子层覆盖阻挡层，其覆盖具有开口的绝缘层。电镀铜填充绝缘层中的开口。通过化学机械抛光，阻挡层，不纯的由电镀铜浴铜籽晶层衍生的铜籽晶层和电镀铜平坦化到绝缘层。

8. 发明申请

US20060017169A1 Electroplated interconnection structures on integrated circuit chips 审中-公开
标题翻译：集成电路芯片上的电镀互连结构
公开(公告)号：US20060017169A1
公开(公告)日：2006-01-26
申请号：US11168559
申请日：2005-06-29
申请人： Panayotis Andricacos , Hariklia Deligianni , John Dukovic , Daniel Edelstein , Wilma Horkans , Chao-Kun Hu , Jeffrey Hurd , Kenneth Rodbell , Cyprian Uzoh , Kwong-Hon Wong
发明人： Panayotis Andricacos , Hariklia Deligianni , John Dukovic , Daniel Edelstein , Wilma Horkans , Chao-Kun Hu , Jeffrey Hurd , Kenneth Rodbell , Cyprian Uzoh , Kwong-Hon Wong
IPC分类号： H01L23/48 , H01L21/44
CPC分类号： C25D3/38 , C25D5/022 , H01L21/2885 , H01L21/76877 , H01L21/76885
摘要： A process is described for the fabrication of submicton interconnect structures for integrated circuit chips. Void-free and seamless conductors are obtained by electroplating Cu from baths that contain additives and are conventionally used to deposit level, bright, ductile, and low-stress Cu metal. The capability of this method to superfill features without leaving voids or seams is unique and superior to that of other deposition approaches. The electromigration resistance of structures making use of CU electroplated in this manner is superior to the electromigration resistance of AlCu structures or structures fabricated using Cu deposited by methods other than electroplating.
摘要翻译：描述了用于集成电路芯片的亚微米互连结构的制造的过程。通过从包含添加剂的浴中电镀Cu获得无空隙和无缝导体，并且通常用于沉积水平，光亮，延展性和低应力Cu金属。这种方法在不留下空隙或接缝的情况下超滤特征的能力是独一无二的，优于其他沉积方法。以这种方式电镀Cu的结构的电迁移阻力优于AlCu结构或使用不是电镀方法沉积的Cu制造的结构的电迁移电阻。

9. 发明申请

US20050199502A1 Method for electroplating on resistive substrates 审中-公开
标题翻译：电阻基板电镀方法
公开(公告)号：US20050199502A1
公开(公告)日：2005-09-15
申请号：US11123117
申请日：2005-05-06
申请人： Panayotis Andricacos , Hariklia Deligianni , Wilma Horkans , Keith Kwietniak , Michael Lane , Sandra Malhotra , Fenton McFeely , Conal Murray , Kenneth Rodbell , Philippe Vereecken
发明人： Panayotis Andricacos , Hariklia Deligianni , Wilma Horkans , Keith Kwietniak , Michael Lane , Sandra Malhotra , Fenton McFeely , Conal Murray , Kenneth Rodbell , Philippe Vereecken
IPC分类号： C25D5/18 , C25D7/12 , C25D5/02
CPC分类号： C25D5/18 , C25D7/12 , Y10S428/926 , Y10T428/12493 , Y10T428/12528 , Y10T428/12771 , Y10T428/12778 , Y10T428/12903
摘要： A conductive material is electroplated onto a platable resistive metal barrier layer(s) employing a plating bath optionally comprising a super filling additive and a suppressor, and by changing the current or voltage as a function of the area of plated metal. A structure is also provided that comprises a substrate, a platable metal barrier layer(s) located on the substrate and a relatively continuous uniform electroplated layer of a conductive material located on the platable resistive metal barrier layer.
摘要翻译：导电材料电镀在可镀敷的电阻金属阻挡层上，该层使用任选地包含超填充添加剂和抑制剂的电镀槽，并且通过改变作为电镀金属面积的函数的电流或电压。还提供了一种结构，其包括衬底，位于衬底上的可镀金属阻挡层和位于可镀电阻金属阻挡层上的导电材料的相对连续的均匀电镀层。

10. 发明申请

US20070045844A1 Alpha particle shields in chip packaging 审中-公开
标题翻译： Alpha颗粒屏蔽芯片封装
公开(公告)号：US20070045844A1
公开(公告)日：2007-03-01
申请号：US11211116
申请日：2005-08-24
申请人： Paul Andry , Cyril Cabral , Kenneth Rodbell , Robert Wisnieff
发明人： Paul Andry , Cyril Cabral , Kenneth Rodbell , Robert Wisnieff
IPC分类号： H01L23/48
CPC分类号： H01L23/556 , H01L21/304 , H01L21/481 , H01L24/11 , H01L24/29 , H01L24/81 , H01L24/83 , H01L2224/16 , H01L2224/16113 , H01L2224/16225 , H01L2224/16227 , H01L2224/29111 , H01L2224/73204 , H01L2224/81801 , H01L2224/83801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/04953 , H01L2924/14 , H01L2924/15311 , H01L2924/15787 , H01L2924/19041 , H01L2924/19043 , H01L2924/2064 , H01L2924/3025 , H01L2224/13111 , H01L2924/00014
摘要： A structure and a method for forming the same. The structure includes an integrated circuit comprising N chip electric pads, wherein N is a positive integer, and wherein the N chip electric pads are electrically connected to a plurality of devices on the integrated circuit. The structure further includes N solder bumps corresponding to the N chip electric pads. A semiconductor interposing shield is sandwiched between the integrated circuit and the N solder bumps. The structure further includes N electric conductors (i) passing through the semiconductor interposing shield and (ii) electrically connecting the N solder bumps to the N chip electric pads.
摘要翻译：一种结构及其形成方法。该结构包括一个包括N个芯片电极焊盘的集成电路，其中N是正整数，并且其中N个芯片电极焊盘电连接到集成电路上的多个器件。该结构还包括对应于N个芯片电焊盘的N个焊料凸块。半导体插入式屏蔽夹在集成电路和N个焊料凸块之间。该结构还包括通过半导体插入屏蔽的N个导体（i）和（ii）将N个焊料凸块电连接到N个芯片电极焊盘。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式