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1. 发明申请

US20110220805A1 FET RADIATION MONITOR 有权
标题翻译： FET辐射监测器
公开(公告)号：US20110220805A1
公开(公告)日：2011-09-15
申请号：US12719962
申请日：2010-03-09
申请人： Michael Gordon , Steven Koester , Kenneth Rodbell , Jeng-Bang Yau
发明人： Michael Gordon , Steven Koester , Kenneth Rodbell , Jeng-Bang Yau
IPC分类号： G01T1/24 , H01L31/08
CPC分类号： H01L31/119
摘要： A semiconductor device includes a semiconductor substrate; a buried insulator layer disposed on the semiconductor substrate, the buried insulator layer configured to retain an amount of charge in a plurality of charge traps in response to a radiation exposure by the semiconductor device; a semiconductor layer disposed on the buried insulating layer; a second insulator layer disposed on the semiconductor layer; a gate conducting layer disposed on the second insulator layer; and one or more side contacts electrically connected to the semiconductor layer. A method for radiation monitoring, the method includes applying a backgate voltage to a radiation monitor, the radiation monitor comprising a field effect transistor (FET); exposing the radiation monitor to radiation; determining a change in a threshold voltage of the radiation monitor; and determining an amount of radiation exposure based on the change in threshold voltage.
摘要翻译：半导体器件包括半导体衬底; 设置在所述半导体衬底上的掩埋绝缘体层，所述掩埋绝缘体层被配置为响应于所述半导体器件的辐射暴露而将多个电荷量保持在多个电荷阱中; 设置在所述掩埋绝缘层上的半导体层; 设置在所述半导体层上的第二绝缘体层; 设置在所述第二绝缘体层上的栅极导电层; 以及与半导体层电连接的一个或多个侧触点。一种用于辐射监测的方法，所述方法包括将背栅电压施加到辐射监测器，所述辐射监测器包括场效应晶体管（FET）; 将辐射监测仪暴露于辐射; 确定辐射监测器的阈值电压的变化; 以及基于阈值电压的变化确定辐射暴露量。

2. 发明授权

US08080805B2 FET radiation monitor 有权
标题翻译： FET辐射监测器
公开(公告)号：US08080805B2
公开(公告)日：2011-12-20
申请号：US12719962
申请日：2010-03-09
申请人： Michael Gordon , Steven Koester , Kenneth Rodbell , Jeng-Bang Yau
发明人： Michael Gordon , Steven Koester , Kenneth Rodbell , Jeng-Bang Yau
IPC分类号： H01L27/146
CPC分类号： H01L31/119
摘要： A semiconductor device includes a semiconductor substrate; a buried insulator layer disposed on the semiconductor substrate, the buried insulator layer configured to retain an amount of charge in a plurality of charge traps in response to a radiation exposure by the semiconductor device; a semiconductor layer disposed on the buried insulating layer; a second insulator layer disposed on the semiconductor layer; a gate conducting layer disposed on the second insulator layer; and one or more side contacts electrically connected to the semiconductor layer. A method for radiation monitoring, the method includes applying a backgate voltage to a radiation monitor, the radiation monitor comprising a field effect transistor (FET); exposing the radiation monitor to radiation; determining a change in a threshold voltage of the radiation monitor; and determining an amount of radiation exposure based on the change in threshold voltage.
摘要翻译：半导体器件包括半导体衬底; 设置在所述半导体衬底上的掩埋绝缘体层，所述掩埋绝缘体层被配置为响应于所述半导体器件的辐射暴露而将多个电荷量保持在多个电荷阱中; 设置在所述掩埋绝缘层上的半导体层; 设置在所述半导体层上的第二绝缘体层; 设置在所述第二绝缘体层上的栅极导电层; 以及与半导体层电连接的一个或多个侧触点。一种用于辐射监测的方法，所述方法包括将背栅电压施加到辐射监测器，所述辐射监测器包括场效应晶体管（FET）; 将辐射监测仪暴露于辐射; 确定辐射监测器的阈值电压的变化; 以及基于阈值电压的变化确定辐射暴露量。

3. 发明申请

US20140027871A1 CHARGE SENSORS USING INVERTED LATERAL BIPOLAR JUNCTION TRANSISTORS 有权
标题翻译：充电传感器使用反转的双极双极晶体管
公开(公告)号：US20140027871A1
公开(公告)日：2014-01-30
申请号：US13561671
申请日：2012-07-30
申请人： Jin Cai , Tak H. Ning , Jeng-Bang Yau , Sufi Zafar
发明人： Jin Cai , Tak H. Ning , Jeng-Bang Yau , Sufi Zafar
IPC分类号： H01L27/14
CPC分类号： G01T1/247 , G01N27/403 , G01T3/08 , H01L27/14 , H01L27/14681 , H01L31/022408 , H01L31/035272 , H01L31/1105 , H01L31/115 , H01L31/118
摘要： A sensor includes a collector, an emitter and a base-region barrier formed as an inverted bipolar junction transistor having a base substrate forming a base electrode to activate the inverted bipolar junction transistor. A level surface is formed by the collector, the emitter and the base-region barrier opposite the base substrate such that when the level surface is exposed to charge, the charge is measured during operation of the bipolar junction transistor.
摘要翻译：传感器包括集电极，发射极和形成为反相双极结型晶体管的基极区势垒，其具有形成基极的基极以激活反相双极结型晶体管。由集电极，发射极和基极区域与基底基板相对的方式形成电平表面，使得当电平表面暴露于电荷时，在双极结晶体管的操作期间测量电荷。

4. 发明申请

US20130015912A1 SOI CMOS STRUCTURE HAVING PROGRAMMABLE FLOATING BACKPLATE 审中-公开
标题翻译：具有可编程浮动背板的SOI CMOS结构
公开(公告)号：US20130015912A1
公开(公告)日：2013-01-17
申请号：US13612036
申请日：2012-09-12
申请人： Jin Cai , Robert H. Dennard , Ali Khakifirooz , Tak H. Ning , Jeng-Bang Yau
发明人： Jin Cai , Robert H. Dennard , Ali Khakifirooz , Tak H. Ning , Jeng-Bang Yau
IPC分类号： G05F3/02
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/7841
摘要： SOI CMOS structures having at least one programmable electrically floating backplate are provided. Each electrically floating backplate is individually programmable. Programming can be performed by injecting electrons into each conductive floating backplate. Erasure of the programming can be accomplished by tunneling the electrons out of the floating backplate. At least one of two means can accomplish programming of the electrically floating backgate. The two means include Fowler-Nordheim tunneling, and hot electron injection using an SOI pFET. Hot electron injection using pFET can be done at much lower voltage than injection by tunneling electron injection.
摘要翻译：提供具有至少一个可编程电浮动背板的SOI CMOS结构。每个电浮动背板均可单独编程。可以通过将电子注入每个导电浮动背板来进行编程。编程的擦除可以通过将电子穿过浮动背板来实现。两个装置中的至少一个可以完成电浮动背栅的编程。这两种方法包括Fowler-Nordheim隧道和使用SOI pFET的热电子注入。使用pFET的热电子注入可以通过隧道电子注入在比注入低得多的电压下进行。

5. 发明申请

US20120326129A1 METAL-FREE INTEGRATED CIRCUITS COMPRISING GRAPHENE AND CARBON NANOTUBES 有权
标题翻译：包含石墨和碳纳米管的无金属集成电路
公开(公告)号：US20120326129A1
公开(公告)日：2012-12-27
申请号：US13604254
申请日：2012-09-05
申请人： Yu-Ming Lin , Jeng-Bang Yau
发明人： Yu-Ming Lin , Jeng-Bang Yau
IPC分类号： H01L29/78
CPC分类号： H01L29/1606 , B82Y10/00 , H01L27/124 , H01L29/0665 , H01L29/45 , H01L29/4908 , H01L29/66742 , H01L29/7781 , H01L29/78618 , H01L29/78684
摘要： An integrated circuit includes a graphene layer, the graphene layer comprising a region of undoped graphene, the undoped graphene comprising a channel of a transistor, and a region of doped graphene, the doped graphene comprising a contact of the transistor; and a gate of the transistor, the gate comprising a carbon nanotube film. A method of fabricating an integrated circuit comprising graphene and carbon nanotubes, includes forming a graphene layer; doping a portion of the graphene layer, resulting in doped graphene and undoped graphene; forming a carbon nanotube film; and etching the carbon nanotube film to form a gate of a transistor, wherein the transistor further comprises a channel comprising the undoped graphene and a contact comprising the doped graphene. A transistor includes a gate, the gate comprising a carbon nanotube film; a channel, the channel comprising undoped graphene; and a contact, the contact comprising doped graphene.
摘要翻译：集成电路包括石墨烯层，所述石墨烯层包括未掺杂的石墨烯的区域，所述未掺杂的石墨烯包括晶体管的沟道和掺杂的石墨烯的区域，所述掺杂的石墨烯包括所述晶体管的接触; 和晶体管的栅极，所述栅极包括碳纳米管膜。一种制造包括石墨烯和碳纳米管的集成电路的方法，包括形成石墨烯层; 掺杂一部分石墨烯层，导致掺杂的石墨烯和未掺杂的石墨烯; 形成碳纳米管膜; 以及蚀刻所述碳纳米管膜以形成晶体管的栅极，其中所述晶体管还包括包含所述未掺杂的石墨烯的沟道和包含所述掺杂石墨烯的接触。晶体管包括栅极，栅极包括碳纳米管膜; 通道，通道包括未掺杂的石墨烯; 和触点，所述触点包括掺杂的石墨烯。

6. 发明申请

US20110171792A1 BACK-GATED FULLY DEPLETED SOI TRANSISTOR 有权
标题翻译：背面放置完全绝缘的SOI晶体管
公开(公告)号：US20110171792A1
公开(公告)日：2011-07-14
申请号：US12684225
申请日：2010-01-08
申请人： Leland Chang , Brian L. Ji , Arvind Kumar , Amlan Majumdar , Katherine Saenger , Leathen Shi , Jeng-Bang Yau
发明人： Leland Chang , Brian L. Ji , Arvind Kumar , Amlan Majumdar , Katherine Saenger , Leathen Shi , Jeng-Bang Yau
IPC分类号： H01L21/336
CPC分类号： H01L21/2652 , G03F9/7084 , H01L21/26506 , H01L21/2654 , H01L21/26553 , H01L21/2658 , H01L21/6835 , H01L23/544 , H01L29/78648 , H01L2221/68318 , H01L2221/68363 , H01L2221/68377 , H01L2223/54426 , H01L2224/80006 , H01L2224/8013 , H01L2224/802 , H01L2924/01019 , H01L2924/12044 , H01L2924/13091
摘要： A fully depleted semiconductor-on-insulator (FDSOI) transistor structure includes a back gate electrode having a limited thickness and aligned to a front gate electrode. The back gate electrode is formed in a first substrate by ion implantation of dopants through a first oxide cap layer. Global alignment markers are formed in the first substrate to enable alignment of the front gate electrode to the back gate electrode. The global alignment markers enable preparation of a virtually flat substrate on the first substrate so that the first substrate can be bonded to a second substrate in a reliable manner.
摘要翻译：完全耗尽的绝缘体上半导体（FDSOI）晶体管结构包括具有有限厚度并与前栅电极对准的背栅电极。背栅极通过第一氧化物覆盖层通过离子注入掺杂剂形成在第一衬底中。在第一衬底中形成全局对准标记，以使前栅电极与背栅电极对准。全局校准标记使得能够在第一衬底上制备实质上平坦的衬底，使得第一衬底可以以可靠的方式结合到第二衬底。

7. 发明申请

US20110115021A1 ISOLATION STRUCTURES FOR SOI DEVICES WITH ULTRATHIN SOI AND ULTRATHIN BOX 有权
标题翻译：具有超薄SOI和ULTRATHIN BOX的SOI器件的隔离结构
公开(公告)号：US20110115021A1
公开(公告)日：2011-05-19
申请号：US12618871
申请日：2009-11-16
申请人： Robert H. Dennard , Marwan H. Khater , Leathen Shi , Jeng-Bang Yau
发明人： Robert H. Dennard , Marwan H. Khater , Leathen Shi , Jeng-Bang Yau
IPC分类号： H01L29/786 , H01L29/06 , H01L21/762
CPC分类号： H01L21/76264 , H01L21/76232
摘要： Shallow trenches are formed around a vertical stack of a buried insulator portion and a top semiconductor portion. A dielectric material layer is deposited directly on sidewalls of the top semiconductor portion. Shallow trench isolation structures are formed by filling the shallow trenches with a dielectric material such as silicon oxide. After planarization, the top semiconductor portion is laterally contacted and surrounded by the dielectric material layer. The dielectric material layer prevents exposure of the handle substrate underneath the buried insulator portion during wet etches, thereby ensuring electrical isolation between the handle substrate and gate electrodes subsequently formed on the top semiconductor portion.
摘要翻译：浅埋沟形成在埋入绝缘体部分和顶部半导体部分的垂直堆叠周围。介电材料层直接沉积在顶部半导体部分的侧壁上。通过用诸如氧化硅的介电材料填充浅沟槽来形成浅沟槽隔离结构。在平坦化之后，顶部半导体部分被电介质材料层横向接触并包围。介电材料层防止在湿蚀刻期间在掩埋绝缘体部分下面的手柄基板的暴露，从而确保手柄基板和随后形成在顶部半导体部分上的栅电极之间的电隔离。

8. 发明申请

US20100176482A1 LOW COST FABRICATION OF DOUBLE BOX BACK GATE SILICON-ON-INSULATOR WAFERS WITH SUBSEQUENT SELF ALIGNED SHALLOW TRENCH ISOLATION 审中-公开
标题翻译：具有后续自对准的双盒背盖的低成本制造硅绝缘体波纹
公开(公告)号：US20100176482A1
公开(公告)日：2010-07-15
申请号：US12352077
申请日：2009-01-12
申请人： Robert H. Dennard , David R. Greenberg , Amlan Majumdar , Leathen Shi , Jeng-Bang Yau
发明人： Robert H. Dennard , David R. Greenberg , Amlan Majumdar , Leathen Shi , Jeng-Bang Yau
IPC分类号： H01L27/12 , H01L21/762 , H01L29/06
CPC分类号： H01L21/84 , H01L21/76254 , H01L21/76275 , H01L21/76283 , H01L27/1203
摘要： A semiconductor substrate structure for manufacturing integrated circuit devices includes a bulk substrate; a lower insulating layer formed on the bulk substrate, the lower insulating layer formed from a pair of separate insulation layers having a bonding interface therebetween; an electrically conductive layer formed on the lower insulating layer; an insulator with etch stop characteristics formed on the electrically conductive layer; an upper insulating layer formed on the etch stop layer; and a semiconductor layer formed on the upper insulating layer. A scheme of subsequently building a dual-depth shallow trench isolation with the deeper STI in the back gate layer self-aligned to the shallower STI in the active region in such a semiconductor substrate is also disclosed.
摘要翻译：用于制造集成电路器件的半导体衬底结构包括块状衬底; 形成在所述本体基板上的下绝缘层，所述下绝缘层由一对具有接合界面的分离的绝缘层形成; 形成在下绝缘层上的导电层; 在所述导电层上形成具有蚀刻停止特性的绝缘体; 形成在所述蚀刻停止层上的上绝缘层; 以及形成在上绝缘层上的半导体层。还公开了一种随后构建双深度浅沟槽隔离的方案，其中在与这种半导体衬底中的有源区域中较浅的STI自对准的背栅层中的较深STI相比较。

9. 发明授权

US07684147B2 Magnetoelectronic devices based on colossal magnetoresistive thin films 有权
标题翻译：基于巨磁阻薄膜的磁电子器件
公开(公告)号：US07684147B2
公开(公告)日：2010-03-23
申请号：US10582813
申请日：2004-12-15
申请人： Charles Ahn , Lior Klein , Yosef Basson , Xia Hong , Jeng-Bang Yau
发明人： Charles Ahn , Lior Klein , Yosef Basson , Xia Hong , Jeng-Bang Yau
IPC分类号： G11B5/37 , G11B5/127 , H01L29/82
CPC分类号： G01R33/093 , B82Y25/00 , G01R33/07 , G01R33/09 , G11C11/18 , H01F1/407 , H01F10/1933 , H01L43/06
摘要： The present invention is directed to the use of perovskite manganite thin films and other magnetic films that exhibit both planar Hall effect and biaxial magnetic anisotropy to form the active area in magnetic sensor devices and in magnetic bit cells used in magnetoresistive random access memory (MRAM) devices. The manganite thin films of the invention are ferromagnetic manganites of the formula R1-xAxMnO3, wherein R is a rare-earth metal, A is an alkaline earth metal, and x is generally between about 0.15 and about 0.5.
摘要翻译：本发明涉及使用表现出平面霍尔效应和双轴磁各向异性两者的钙钛矿亚锰酸盐薄膜和其它磁性膜来形成磁传感器装置和磁阻随机存取存储器（MRAM）中使用的磁位元件中的有效面积的方法，设备。本发明的亚锰酸盐薄膜是式R1-xAxMnO3的铁磁锰矿，其中R是稀土金属，A是碱土金属，x通常在约0.15和约0.5之间。

10. 发明授权

US08803131B2 Metal-free integrated circuits comprising graphene and carbon nanotubes 有权
标题翻译：包含石墨烯和碳纳米管的无金属集成电路
公开(公告)号：US08803131B2
公开(公告)日：2014-08-12
申请号：US13604254
申请日：2012-09-05
申请人： Yu-Ming Lin , Jeng-Bang Yau
发明人： Yu-Ming Lin , Jeng-Bang Yau
IPC分类号： H01L29/78
CPC分类号： H01L29/1606 , B82Y10/00 , H01L27/124 , H01L29/0665 , H01L29/45 , H01L29/4908 , H01L29/66742 , H01L29/7781 , H01L29/78618 , H01L29/78684
摘要： An integrated circuit includes a graphene layer, the graphene layer comprising a region of undoped graphene, the undoped graphene comprising a channel of a transistor, and a region of doped graphene, the doped graphene comprising a contact of the transistor; and a gate of the transistor, the gate comprising a carbon nanotube film. A method of fabricating an integrated circuit comprising graphene and carbon nanotubes, includes forming a graphene layer; doping a portion of the graphene layer, resulting in doped graphene and undoped graphene; forming a carbon nanotube film; and etching the carbon nanotube film to form a gate of a transistor, wherein the transistor further comprises a channel comprising the undoped graphene and a contact comprising the doped graphene. A transistor includes a gate, the gate comprising a carbon nanotube film; a channel, the channel comprising undoped graphene; and a contact, the contact comprising doped graphene.
摘要翻译：集成电路包括石墨烯层，所述石墨烯层包括未掺杂的石墨烯的区域，所述未掺杂的石墨烯包括晶体管的沟道和掺杂的石墨烯的区域，所述掺杂的石墨烯包括所述晶体管的接触; 和晶体管的栅极，所述栅极包括碳纳米管膜。一种制造包括石墨烯和碳纳米管的集成电路的方法，包括形成石墨烯层; 掺杂一部分石墨烯层，导致掺杂的石墨烯和未掺杂的石墨烯; 形成碳纳米管膜; 以及蚀刻所述碳纳米管膜以形成晶体管的栅极，其中所述晶体管还包括包含所述未掺杂的石墨烯的沟道和包含所述掺杂石墨烯的接触。晶体管包括栅极，栅极包括碳纳米管膜; 通道，通道包括未掺杂的石墨烯; 和触点，所述触点包括掺杂的石墨烯。

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