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1. 发明申请

US20140015564A1 SINGLE EVENT TRANSIENT AND UPSET MITIGATION FOR SILICON-ON-INSULATOR CMOS TECHNOLOGY 有权
标题翻译：绝缘体绝缘体CMOS技术的单次事件瞬态和电流缓解
公开(公告)号：US20140015564A1
公开(公告)日：2014-01-16
申请号：US13550462
申请日：2012-07-16
申请人： Ethan Cannon , Salim Rabaa , Josh Mackler
发明人： Ethan Cannon , Salim Rabaa , Josh Mackler
IPC分类号： H03K19/003 , H01L21/82
CPC分类号： H03K19/20 , H03K19/00338
摘要： A circuit and methods for mitigating radiation-induced Single Event Effects (SEE) in Silicon-on-Insulator (SOI) Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuits are presented. A primary logic output is generated from a primary logic gate in response to an input. A redundant logic output is generated from a redundant logic gate that duplicates the primary logic output in response to the input if an SEE is not present. An interleaved C-gate output is generated from an interleaved C-gate that emulates an inverter output when the primary logic output and the redundant logic output match, and does not changes its output when the primary logic output and the redundant logic output do not match during the SEE.
摘要翻译：介绍了一种用于减轻绝缘体上硅（SOI）互补金属氧化物半导体（CMOS）集成电路中的辐射诱发单事件效应（SEE）的电路和方法。响应于输入，从主逻辑门产生主逻辑输出。如果不存在SEE，则从冗余逻辑门产生冗余逻辑输出，该逻辑门复制主逻辑输出以响应输入。当主逻辑输出和冗余逻辑输出匹配时，交错C门输出从仿真反相器输出的交错C门产生，当主逻辑输出与冗余逻辑输出不匹配时，不会改变其输出在SEE期间。

2. 发明申请

US20060163635A1 CAPACITOR BELOW THE BURIED OXIDE OF SOI CMOS TECHNOLOGIES FOR PROTECTION AGAINST SOFT ERRORS 失效
标题翻译： SOI CMOS技术的BIOI氧化物电容器防止软错误
公开(公告)号：US20060163635A1
公开(公告)日：2006-07-27
申请号：US10905906
申请日：2005-01-26
申请人： John Aitken , Ethan Cannon , Philip Oldiges , Alvin Strong
发明人： John Aitken , Ethan Cannon , Philip Oldiges , Alvin Strong
IPC分类号： H01L29/76
CPC分类号： H01L27/1203 , H01L29/92
摘要： Disclosed is a semiconductor structure that incorporates a capacitor for reducing the soft error rate of a device within the structure. The multi-layer semiconductor structure includes an insulator-filled deep trench isolation structure that is formed through an active silicon layer, a first insulator layer, and a first bulk layer and extends to a second insulator layer. The resulting isolated portion of the first bulk layer defines the first capacitor plate. A portion of the second insulator layer that is adjacent the first capacitor plate functions as the capacitor dielectric. Either the silicon substrate or a portion of a second bulk layer that is isolated by a third insulator layer and another deep trench isolation structure can function as the second capacitor plate. A first capacitor contact couples, either directly or via a wire array, the first capacitor plate to a circuit node of the device in order to increase the critical charge, Qcrit, of the circuit node.
摘要翻译：公开了一种包含用于降低结构内的器件的软错误率的电容器的半导体结构。多层半导体结构包括通过有源硅层，第一绝缘体层和第一体层形成并延伸到第二绝缘体层的绝缘体填充的深沟槽隔离结构。所形成的第一体层的隔离部分限定第一电容器板。与第一电容器板相邻的第二绝缘体层的一部分用作电容器电介质。硅衬底或由第三绝缘体层和另一个深沟槽隔离结构隔离的第二体层的一部分可以用作第二电容器板。第一电容器触点直接地或经由线阵列将第一电容器板耦合到器件的电路节点，以便增加电路节点的临界电荷Qcrit。

3. 发明申请

US20070252088A1 MONITORING IONIZING RADIATION IN SILICON-ON INSULATOR INTEGRATED CIRCUITS 有权
标题翻译：监测硅绝缘子集成电路中的离子化辐射
公开(公告)号：US20070252088A1
公开(公告)日：2007-11-01
申请号：US11380736
申请日：2006-04-28
申请人： Wagdi Abadeer , Ethan Cannon , Dennis Cox , William Tonti
发明人： Wagdi Abadeer , Ethan Cannon , Dennis Cox , William Tonti
IPC分类号： G01T1/02
CPC分类号： G01T1/244
摘要： A method, device and system for monitoring ionizing radiation. The method including: collecting an ionizing radiation induced charge collected by the depletion region of a diode formed in a silicon layer below an oxide layer buried below a surface of a silicon substrate; and coupling a cathode of the diode to a precharged node of a clocked logic circuit such that the ionizing radiation induced charge collected by a depletion region of the diode will discharge the precharged node and change an output state of the clocked logic circuit.
摘要翻译：一种用于监测电离辐射的方法，装置和系统。该方法包括：收集由埋在硅衬底表面下方的氧化物层下面的硅层中形成的二极管的耗尽区收集的电离辐射感应电荷; 以及将二极管的阴极耦合到时钟逻辑电路的预充电节点，使得由二极管的耗尽区收集的电离辐射感应电荷将放电预充电节点并改变时钟逻辑电路的输出状态。

4. 发明申请

US20070187778A1 SHALLOW TRENCH ISOLATION STRUCTURE FOR SHIELDING TRAPPED CHARGE IN A SEMICONDUCTOR DEVICE 失效
标题翻译：用于半导体器件中的屏蔽带电充电的低温隔离结构
公开(公告)号：US20070187778A1
公开(公告)日：2007-08-16
申请号：US11276132
申请日：2006-02-15
申请人： Ethan Cannon , Shunhua Chang , Toshiharu Furukawa , David Horak , Charles Koburger
发明人： Ethan Cannon , Shunhua Chang , Toshiharu Furukawa , David Horak , Charles Koburger
IPC分类号： H01L29/76
CPC分类号： H01L21/76224 , H01L29/7833
摘要： A semiconductor structure and associated method for forming the semiconductor structure. The semiconductor structure comprises a first field effect transistor (FET), a second FET, and a shallow trench isolation (STI) structure. The first FET comprises a channel region formed from a portion of a silicon substrate, a gate dielectric formed over the channel region, and a gate electrode comprising a bottom surface in direct physical contact with the gate dielectric. A top surface of the channel region is located within a first plane and the bottom surface of the gate electrode is located within a second plane. The STI structure comprises a conductive STI fill structure. A top surface of the conductive STI fill structure is above the first plane by a first distance D1 and is above the second plane by a second distance D2 that is less than D1.
摘要翻译：一种用于形成半导体结构的半导体结构和相关方法。半导体结构包括第一场效应晶体管（FET），第二FET和浅沟槽隔离（STI）结构。第一FET包括由硅衬底的一部分形成的沟道区，在沟道区上形成的栅极电介质和包括与栅极电介质直接物理接触的底表面的栅电极。沟道区的顶表面位于第一平面内，栅电极的底表面位于第二平面内。 STI结构包括导电STI填充结构。导电STI填充结构的顶表面在第一平面上方高于第一距离D 1，并且在第二平面上方高于第二平面的第二距离D 2 2 < D 1 。

5. 发明申请

US20080116529A1 SHALLOW TRENCH ISOLATION STRUCTURE FOR SHIELDING TRAPPED CHARGE IN A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：用于半导体器件中的屏蔽带电充电的低温隔离结构
公开(公告)号：US20080116529A1
公开(公告)日：2008-05-22
申请号：US12022202
申请日：2008-01-30
申请人： Ethan Cannon , Shunhua Chang , Toshiharu Furukawa , David Horak , Charles Koburger
发明人： Ethan Cannon , Shunhua Chang , Toshiharu Furukawa , David Horak , Charles Koburger
IPC分类号： H01L27/088
CPC分类号： H01L21/76224 , H01L29/7833
摘要： A semiconductor structure comprising a first field effect transistor (FET), a second FET, and a shallow trench isolation (STI) structure. The first FET comprises a channel region formed from a portion of a silicon substrate, a gate dielectric formed over the channel region, and a gate electrode comprising a bottom surface in direct physical contact with the gate dielectric. A top surface of the channel region is located within a first plane and the bottom surface of the gate electrode is located within a second plane. The STI structure comprises a conductive STI fill structure. A top surface of the conductive STI fill structure is above the first plane by a first distance D1 and is above the second plane by a second distance D2 that is less than D1.
摘要翻译：一种包括第一场效应晶体管（FET），第二FET和浅沟槽隔离（STI）结构的半导体结构。第一FET包括由硅衬底的一部分形成的沟道区，在沟道区上形成的栅极电介质和包括与栅极电介质直接物理接触的底表面的栅电极。沟道区的顶表面位于第一平面内，栅电极的底表面位于第二平面内。 STI结构包括导电STI填充结构。导电STI填充结构的顶表面在第一平面上方高于第一距离D 1，并且在第二平面上方高于第二平面的第二距离D 2 2 < D 1 。

6. 发明申请

US20070158779A1 Methods and semiconductor structures for latch-up suppression using a buried damage layer 审中-公开
标题翻译：使用掩埋损伤层进行闩锁抑制的方法和半导体结构
公开(公告)号：US20070158779A1
公开(公告)日：2007-07-12
申请号：US11330688
申请日：2006-01-12
申请人： Ethan Cannon , Toshiharu Furukawa , Robert Gauthier , David Horak , Jack Mandelman , William Tonti
发明人： Ethan Cannon , Toshiharu Furukawa , Robert Gauthier , David Horak , Jack Mandelman , William Tonti
IPC分类号： H01L29/00
CPC分类号： H01L21/26506 , H01L21/26513 , H01L21/2658 , H01L21/823892 , H01L27/0921
摘要： Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The structure comprises a damage layer formed in a substrate, a first doped well formed in the substrate, and a second doped well formed in the substrate proximate to the first doped well. The damage layer extends within the substrate to intersect the first and second doped wells. The damage layer may be formed by ion implantation followed by growth of an epitaxial layer to segregate the active device regions from the damage layer.
摘要翻译：用于抑制大量CMOS器件中的闩锁的半导体结构和方法。该结构包括形成在衬底中的损伤层，在衬底中形成的第一掺杂阱，以及在靠近第一掺杂阱的衬底中形成的第二掺杂阱。损伤层在衬底内延伸以与第一和第二掺杂阱相交。可以通过离子注入形成损伤层，随后生长外延层以使有源器件区域与损伤层分离。

7. 发明申请

US20050143945A1 Automatic exchange of degraders in accelerated testing of computer chips 失效
标题翻译：自动交换降解器加速电脑芯片测试
公开(公告)号：US20050143945A1
公开(公告)日：2005-06-30
申请号：US10734694
申请日：2003-12-12
申请人： Carl Bohnenkamp , Ethan Cannon , Ethan Cascio , Michael Gordon , Kenneth Rodbell , Theodore Zabel
发明人： Carl Bohnenkamp , Ethan Cannon , Ethan Cascio , Michael Gordon , Kenneth Rodbell , Theodore Zabel
IPC分类号： G06F19/00
CPC分类号： H01L21/68764 , H01L21/67213 , H01L21/68771
摘要： Issues that are addressed in accordance with at least one presently preferred embodiment of the present invention, are: improvements upon the time it takes to physically swap degraders (done previously by hand); the safety involved in doing so, since the degraders become highly radioactive; possible improved energy resolution and beam stability if the accelerator can be left running continuously; and in-situ monitoring of beam current, beam position and stability. Particularly contemplated are methods and arrangements for changing degraders automatically, not manually, and in a safe manner.
摘要翻译：根据本发明的至少一个目前优选的实施例解决的问题是：在物理交换降解器（先前由手工完成）所花费的时间上的改进; 这样做的安全性，因为降解物变得高度放射性; 如果加速器可以连续运行，可能改善能量分辨率和光束稳定性; 并对射束电流，光束位置和稳定性进行现场监测。特别考虑的是自动而不是手动地以安全的方式改变降解器的方法和装置。

8. 发明授权

US08847621B2 Single event transient and upset mitigation for silicon-on-insulator CMOS technology 有权
标题翻译：绝缘体上硅CMOS技术的单事件瞬态和失真减轻
公开(公告)号：US08847621B2
公开(公告)日：2014-09-30
申请号：US13550462
申请日：2012-07-16
申请人： Ethan Cannon , Salim Rabaa , Josh Mackler
发明人： Ethan Cannon , Salim Rabaa , Josh Mackler
IPC分类号： H03K19/003 , H01L21/70
CPC分类号： H03K19/20 , H03K19/00338
摘要： A circuit and methods for mitigating radiation-induced Single Event Effects (SEE) in Silicon-on-Insulator (SOI) Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuits are presented. A primary logic output is generated from a primary logic gate in response to an input. A redundant logic output is generated from a redundant logic gate that duplicates the primary logic output in response to the input if an SEE is not present. An interleaved C-gate output is generated from an interleaved C-gate that emulates an inverter output when the primary logic output and the redundant logic output match, and does not changes its output when the primary logic output and the redundant logic output do not match during the SEE.
摘要翻译：介绍了一种用于减轻绝缘体上硅（SOI）互补金属氧化物半导体（CMOS）集成电路中的辐射诱发单事件效应（SEE）的电路和方法。响应于输入，从主逻辑门产生主逻辑输出。如果不存在SEE，则从冗余逻辑门产生冗余逻辑输出，该逻辑门复制主逻辑输出以响应输入。当主逻辑输出和冗余逻辑输出匹配时，交错C门输出从仿真反相器输出的交错C门产生，当主逻辑输出与冗余逻辑输出不匹配时，不会改变其输出在SEE期间。

9. 发明申请

US20070194403A1 Methods for fabricating semiconductor device structures with reduced susceptibility to latch-up and semiconductor device structures formed by the methods 审中-公开
标题翻译：用于制造具有降低的对闩锁敏感性的半导体器件结构和通过该方法形成的半导体器件结构的方法
公开(公告)号：US20070194403A1
公开(公告)日：2007-08-23
申请号：US11360345
申请日：2006-02-23
申请人： Ethan Cannon , Toshiharu Furukawa , Mark Hakey , David Horak , Charles Koburger , Jimmy Kontos , Jack Mandelman , William Tonti
发明人： Ethan Cannon , Toshiharu Furukawa , Mark Hakey , David Horak , Charles Koburger , Jimmy Kontos , Jack Mandelman , William Tonti
IPC分类号： H01L21/76
CPC分类号： H01L27/0921 , H01L21/76229 , H01L21/823878
摘要： Semiconductor methods and device structures for suppressing latch-up in bulk CMOS devices. The method comprises forming a trench in the semiconductor material of the substrate with first sidewalls disposed between a pair of doped wells, also defined in the semiconductor material of the substrate. The method further comprises forming an etch mask in the trench to partially mask the base of the trench, followed by removing the semiconductor material of the substrate exposed across the partially masked base to define narrowed second sidewalls that deepen the trench. The deepened trench is filled with a dielectric material to define a trench isolation region for devices built in the doped wells. The dielectric material filling the deepened extension of the trench enhances latch-up suppression.
摘要翻译：用于抑制大量CMOS器件中的闩锁的半导体方法和器件结构。该方法包括在衬底的半导体材料中形成沟槽，其第一侧壁设置在也在衬底的半导体材料中定义的一对掺杂阱之间。该方法还包括在沟槽中形成蚀刻掩模以部分地掩蔽沟槽的基底，随后去除暴露在部分屏蔽的基底上的衬底的半导体材料，以限定加深沟槽的变窄的第二侧壁。加深的沟槽填充有介电材料以限定用于内置于掺杂阱中的器件的沟槽隔离区域。填充沟槽加深的介质材料增强了闩锁抑制。

10. 发明申请

US20070272961A1 CAPACITOR BELOW THE BURIED OXIDE OF SOI CMOS TECHNOLOGIES FOR PROTECTION AGAINST SOFT ERRORS 有权
标题翻译： SOI CMOS技术的BIOI氧化物电容器防止软错误
公开(公告)号：US20070272961A1
公开(公告)日：2007-11-29
申请号：US11838931
申请日：2007-08-15
申请人： John Aitken , Ethan Cannon , Philip Oldiges , Alvin Strong
发明人： John Aitken , Ethan Cannon , Philip Oldiges , Alvin Strong
IPC分类号： H01L27/108
CPC分类号： H01L27/1203 , H01L29/92
摘要： Disclosed is a semiconductor structure that incorporates a capacitor for reducing the soft error rate of a device within the structure. The multi-layer semiconductor structure includes an insulator-filled deep trench isolation structure that is formed through an active silicon layer, a first insulator layer, and a first bulk layer and extends to a second insulator layer. The resulting isolated portion of the first bulk layer defines the first capacitor plate. A portion of the second insulator layer that is adjacent the first capacitor plate functions as the capacitor dielectric. Either the silicon substrate or a portion of a second bulk layer that is isolated by a third insulator layer and another deep trench isolation structure can function as the second capacitor plate. A first capacitor contact couples, either directly or via a wire array, the first capacitor plate to a circuit node of the device in order to increase the critical charge, Qcrit, of the circuit node.
摘要翻译：公开了一种包含用于降低结构内的器件的软错误率的电容器的半导体结构。多层半导体结构包括通过有源硅层，第一绝缘体层和第一体层形成并延伸到第二绝缘体层的绝缘体填充的深沟槽隔离结构。所形成的第一体层的隔离部分限定第一电容器板。与第一电容器板相邻的第二绝缘体层的一部分用作电容器电介质。硅衬底或由第三绝缘体层和另一个深沟槽隔离结构隔离的第二体层的一部分可以用作第二电容器板。第一电容器触点直接地或经由线阵列将第一电容器板耦合到器件的电路节点，以便增加电路节点的临界电荷Qcrit。

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