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    • 1. 发明授权
    • Metal-free integrated circuits comprising graphene and carbon nanotubes
    • 包含石墨烯和碳纳米管的无金属集成电路
    • US08803131B2
    • 2014-08-12
    • US13604254
    • 2012-09-05
    • Yu-Ming LinJeng-Bang Yau
    • Yu-Ming LinJeng-Bang Yau
    • H01L29/78
    • H01L29/1606B82Y10/00H01L27/124H01L29/0665H01L29/45H01L29/4908H01L29/66742H01L29/7781H01L29/78618H01L29/78684
    • An integrated circuit includes a graphene layer, the graphene layer comprising a region of undoped graphene, the undoped graphene comprising a channel of a transistor, and a region of doped graphene, the doped graphene comprising a contact of the transistor; and a gate of the transistor, the gate comprising a carbon nanotube film. A method of fabricating an integrated circuit comprising graphene and carbon nanotubes, includes forming a graphene layer; doping a portion of the graphene layer, resulting in doped graphene and undoped graphene; forming a carbon nanotube film; and etching the carbon nanotube film to form a gate of a transistor, wherein the transistor further comprises a channel comprising the undoped graphene and a contact comprising the doped graphene. A transistor includes a gate, the gate comprising a carbon nanotube film; a channel, the channel comprising undoped graphene; and a contact, the contact comprising doped graphene.
    • 集成电路包括石墨烯层,所述石墨烯层包括未掺杂的石墨烯的区域,所述未掺杂的石墨烯包括晶体管的沟道和掺杂的石墨烯的区域,所述掺杂的石墨烯包括所述晶体管的接触; 和晶体管的栅极,所述栅极包括碳纳米管膜。 一种制造包括石墨烯和碳纳米管的集成电路的方法,包括形成石墨烯层; 掺杂一部分石墨烯层,导致掺杂的石墨烯和未掺杂的石墨烯; 形成碳纳米管膜; 以及蚀刻所述碳纳米管膜以形成晶体管的栅极,其中所述晶体管还包括包含所述未掺杂的石墨烯的沟道和包含所述掺杂石墨烯的接触。 晶体管包括栅极,栅极包括碳纳米管膜; 通道,通道包括未掺杂的石墨烯; 和触点,所述触点包括掺杂的石墨烯。
    • 4. 发明申请
    • METAL-FREE INTEGRATED CIRCUITS COMPRISING GRAPHENE AND CARBON NANOTUBES
    • 包含石墨和碳纳米管的无金属集成电路
    • US20120326129A1
    • 2012-12-27
    • US13604254
    • 2012-09-05
    • Yu-Ming LinJeng-Bang Yau
    • Yu-Ming LinJeng-Bang Yau
    • H01L29/78
    • H01L29/1606B82Y10/00H01L27/124H01L29/0665H01L29/45H01L29/4908H01L29/66742H01L29/7781H01L29/78618H01L29/78684
    • An integrated circuit includes a graphene layer, the graphene layer comprising a region of undoped graphene, the undoped graphene comprising a channel of a transistor, and a region of doped graphene, the doped graphene comprising a contact of the transistor; and a gate of the transistor, the gate comprising a carbon nanotube film. A method of fabricating an integrated circuit comprising graphene and carbon nanotubes, includes forming a graphene layer; doping a portion of the graphene layer, resulting in doped graphene and undoped graphene; forming a carbon nanotube film; and etching the carbon nanotube film to form a gate of a transistor, wherein the transistor further comprises a channel comprising the undoped graphene and a contact comprising the doped graphene. A transistor includes a gate, the gate comprising a carbon nanotube film; a channel, the channel comprising undoped graphene; and a contact, the contact comprising doped graphene.
    • 集成电路包括石墨烯层,所述石墨烯层包括未掺杂的石墨烯的区域,所述未掺杂的石墨烯包括晶体管的沟道和掺杂的石墨烯的区域,所述掺杂的石墨烯包括所述晶体管的接触; 和晶体管的栅极,所述栅极包括碳纳米管膜。 一种制造包括石墨烯和碳纳米管的集成电路的方法,包括形成石墨烯层; 掺杂一部分石墨烯层,导致掺杂的石墨烯和未掺杂的石墨烯; 形成碳纳米管膜; 以及蚀刻所述碳纳米管膜以形成晶体管的栅极,其中所述晶体管还包括包含所述未掺杂的石墨烯的沟道和包含所述掺杂石墨烯的接触。 晶体管包括栅极,栅极包括碳纳米管膜; 通道,通道包括未掺杂的石墨烯; 和触点,所述触点包括掺杂的石墨烯。
    • 5. 发明授权
    • Fabrication of graphene nanoelectronic devices on SOI structures
    • 在SOI结构上制造石墨烯纳米电子器件
    • US08673703B2
    • 2014-03-18
    • US12620320
    • 2009-11-17
    • Yu-Ming LinJeng-Bang Yau
    • Yu-Ming LinJeng-Bang Yau
    • H01L21/84
    • H01L29/1606H01L29/66742H01L29/7781H01L29/78687
    • A semiconductor-on-insulator structure and a method of forming the silicon-on-insulator structure including an integrated graphene layer are disclosed. In an embodiment, the method comprises processing a silicon material to form a buried oxide layer within the silicon material, a silicon substrate below the buried oxide, and a silicon-on-insulator layer on the buried oxide. A graphene layer is transferred onto the silicon-on-insulator layer. Source and drain regions are formed in the silicon-on-insulator layer, and a gate is formed above the graphene. In one embodiment, the processing includes growing a respective oxide layer on each of first and second silicon sections, and joining these silicon sections together via the oxide layers to form the silicon material. The processing, in an embodiment, further includes removing a portion of the first silicon section, leaving a residual silicon layer on the bonded oxide, and the graphene layer is positioned on this residual silicon layer.
    • 公开了一种绝缘体上半导体结构和一种形成包括一体化石墨烯层的绝缘体上硅结构的方法。 在一个实施例中,该方法包括处理硅材料以在硅材料内形成掩埋氧化物层,在掩埋氧化物之下形成硅衬底,以及在掩埋氧化物上形成绝缘体上硅层。 将石墨烯层转移到绝缘体上硅层上。 源极和漏极区域形成在绝缘体上硅层中,并且在石墨烯上方形成栅极。 在一个实施例中,该处理包括在第一和第二硅部分中的每一个上生长相应的氧化物层,并且经由氧化物层将这些硅部分连接在一起以形成硅材料。 在一个实施例中,所述处理还包括去除所述第一硅部分的一部分,在所述键合的氧化物上留下残留的硅层,并且所述石墨烯层位于所述剩余硅层上。