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1. 发明授权

US09015376B2 Method for infrastructure messaging 有权
标题翻译：基础设施信息的方法
公开(公告)号：US09015376B2
公开(公告)日：2015-04-21
申请号：US13459212
申请日：2012-04-29
申请人： Michael A. Denio , Brian Karguth , Akila Subramaniam , Charles Fuoco
发明人： Michael A. Denio , Brian Karguth , Akila Subramaniam , Charles Fuoco
IPC分类号： G06F3/00 , G06F15/16 , G06F9/54
CPC分类号： G06F9/546 , G06F2209/548
摘要： A low overhead method to handle inter process and peer to peer communication. A queue manager is used to create a list of messages with minimal configuration overhead. A hardware queue can be connected to another software task owned by the same core or a different processor core, or connected to a hardware DMA peripheral. There is no limitation on how many messages can be queued between the producer and consumer cores. The low latency interrupt generation to the processor cores is handled by an accumulator inside the QMSS which can be configured to generate interrupts based on a programmable threshold of descriptors in a queue. The accumulator thus removes the polling overhead from software and boosts performance by doing the descriptor pops and message transfer in the background.
摘要翻译：一种低开销的处理流程和对等通信的方法。队列管理器用于以最少的配置开销创建消息列表。硬件队列可以连接到由同一核心或不同处理器内核拥有的另一个软件任务，或连接到硬件DMA外设。在生产者和消费者核心之间排队的邮件数量没有限制。处理器内核的低延迟中断产生由QMSS内的累加器来处理，该累加器可以配置为基于队列中描述符的可编程阈值产生中断。因此，累加器消除了软件的轮询开销，并通过在后台执行描述符弹出和消息传输来提高性能。

2. 发明申请

US20130290984A1 Method for Infrastructure Messaging 有权
标题翻译：基础设施消息传递方法
公开(公告)号：US20130290984A1
公开(公告)日：2013-10-31
申请号：US13459212
申请日：2012-04-29
申请人： Michael A. Denio , Brian Karguth , Akila Subramaniam , Charles Fuoco
发明人： Michael A. Denio , Brian Karguth , Akila Subramaniam , Charles Fuoco
IPC分类号： G06F9/46
CPC分类号： G06F9/546 , G06F2209/548
摘要： A low overhead method to handle inter process and peer to peer communication. A queue manager is used to create a list of messages with minimal configuration overhead. A hardware queue can be connected to another software task owned by the same core or a different processor core, or connected to a hardware DMA peripheral. There is no limitation on how many messages can be queued between the producer and consumer cores. The low latency interrupt generation to the processor cores is handled by an accumulator inside the QMSS which can be configured to generate interrupts based on a programmable threshold of descriptors in a queue. The accumulator thus removes the polling overhead from software and boosts performance by doing the descriptor pops and message transfer in the background.
摘要翻译：一种低开销的处理流程和对等通信的方法。队列管理器用于以最少的配置开销创建消息列表。硬件队列可以连接到由同一核心或不同处理器内核拥有的另一个软件任务，或连接到硬件DMA外设。在生产者和消费者核心之间排队的邮件数量没有限制。处理器内核的低延迟中断产生由QMSS内的累加器来处理，该累加器可以配置为基于队列中描述符的可编程阈值产生中断。因此，累加器消除了软件的轮询开销，并通过在后台执行描述符弹出和消息传输来提高性能。

3. 发明授权

US07096301B2 Communications interface for enabling extension of an internal common bus architecture (CBA) 有权
标题翻译：用于扩展内部公共总线架构（CBA）的通信接口
公开(公告)号：US07096301B2
公开(公告)日：2006-08-22
申请号：US10382679
申请日：2003-03-06
申请人： Denis R. Beaudoin , Brian Karguth , James H. Kennedy
发明人： Denis R. Beaudoin , Brian Karguth , James H. Kennedy
IPC分类号： G06F1/00
CPC分类号： G06F13/426 , G06F13/26 , H04L69/08
摘要： A serial communications interface is described that enables the extension of an internal Communications Bus Architecture (CBA) bus segment to one or more external devices. The interface accomplishes this function by serializing bus transactions in one device, transferring the serial transaction between devices via one interface port, and de-serializing the transaction in the external device. The general features include low pin count (as few as three signals), simple packet based transfer protocol for memory mapped access, symmetric operation, simple block code formatting, supports both host to peripheral and peer to peer transactions, and support multiple outstanding transactions.
摘要翻译：描述了能够将内部通信总线架构（CBA）总线段扩展到一个或多个外部设备的串行通信接口。该接口通过串行化一个设备中的总线事务，通过一个接口端口在设备之间传输串行事务以及在外部设备中反序列化事务来完成此功能。一般功能包括低引脚数（少至三个信号），用于存储器映射访问的简单的基于分组的传输协议，对称操作，简单的块代码格式化，支持主机到外设和对等交易，并支持多个未完成的事务。

4. 发明申请

US20060136635A1 Very little multi master bus 审中-公开
标题翻译：很少的多主车
公开(公告)号：US20060136635A1
公开(公告)日：2006-06-22
申请号：US11020830
申请日：2004-12-22
申请人： Denis Beaudoin , Christopher Tracy , Brian Karguth
发明人： Denis Beaudoin , Christopher Tracy , Brian Karguth
IPC分类号： G06F13/00
CPC分类号： G06F13/374
摘要： A method and an apparatus for communication among multiple devices on a data bus with relatively few connections to the bus and reduced logic for enumeration, arbitration, and data flow control is described. A Very Little Multi Master Bus (VLMMB) couples various devices in a bit-rotated manner. When one or more devices seek ownership (control) of the bus, that device raises its assigned bus request line to a predetermined logic (e.g., “1” or “0”). Because there are as many bus request lines as devices, each device can “see” the devices requesting the ownership of the bus. If multiple devices request ownership, the requesting devices determine which one gains ownership by a hierarchical, round-robin, or similar logical decision.
摘要翻译：描述了一种用于在数据总线上的多个设备之间进行通信的方法和装置，其中与总线的连接相对较少，并且用于枚举，仲裁和数据流控制的减少的逻辑。非常小的多主总线（VLMMB）以位旋转的方式耦合各种设备。当一个或多个设备寻求总线的所有权（控制）时，该设备将其分配的总线请求线提升到预定逻辑（例如，“1”或“0”）。因为有与设备一样多的总线请求线路，每个设备都可以“查看”请求总线所有权的设备。如果多个设备请求所有权，则请求设备确定哪个通过分级，循环或类似的逻辑决策来获得所有权。

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