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1. 发明授权

US06556575B1 Broadcast traffic reduction in a communications network 有权
标题翻译：通信网络中的广播流量减少
公开(公告)号：US06556575B1
公开(公告)日：2003-04-29
申请号：US09338446
申请日：1999-06-22
申请人： Michael A. Denio , Denis R. Beaudoin
发明人： Michael A. Denio , Denis R. Beaudoin
IPC分类号： H04L1256
CPC分类号： H04L12/4616
摘要： The present invention includes a method and system for routing broadcast packets in a network (250) using a switching device (200) which is operable to interconnect sub-portions (202, 204) of the network (250). Each network (250) sub-portion (202, 204) is connected to at least one of a plurality of switch ports (232, 236, 240, 244) on the switching device (200). The switching device (200) is further operable to forward certain ones of the broadcast packets between the sub-portions (202, 204) of the network (250) via the switch ports (232, 236, 240, 244) in accordance with a forwarding algorithm and to forward all other of the broadcast packets to a processor (320). The processor (320) is communicatively connected to the switching device (200) and is operable to forward the other ones of the broadcast packets in accordance with a set of pre-defined broadcast routing heuristics.
摘要翻译：本发明包括一种使用可操作以互连网络（250）的子部分（202,204）的交换设备（200）在网络（250）中路由广播分组的方法和系统。每个网络（250）子部分（202,204）连接到交换设备（200）上的多个交换机端口（232,236,240,244）中的至少一个。交换设备（200）还可操作以经由交换机端口（232,236,240,244）在网络（250）的子部分（202,204）之间转发某些广播分组，根据转发算法并将所有其他广播分组转发到处理器（320）。处理器（320）通信地连接到交换设备（200），并且可操作以根据一组预定义的广播路由启发法转发其他广播分组。

2. 发明授权

US07020723B2 Method of allowing multiple, hardware embedded configurations to be recognized by an operating system 有权
标题翻译：允许操作系统识别多个硬件嵌入式配置的方法
公开(公告)号：US07020723B2
公开(公告)日：2006-03-28
申请号：US10421566
申请日：2003-04-23
申请人： Denis R. Beaudoin , Gregory Guyotte , Michael J. Hanrahan , William S. Egr
发明人： Denis R. Beaudoin , Gregory Guyotte , Michael J. Hanrahan , William S. Egr
IPC分类号： G06F13/10 , G06F13/38
CPC分类号： G06F13/4072
摘要： A communications system for enabling extension of an internal common bus architecture (CBA) segment of a first root physical device to an internal CBA bus segment of one or more remote external physical device includes the first root physical device having a first serial communications interface module in the root device coupled between said internal CBA bus segment and an input and output port of the root device for serializing bus transactions from the first device to the output port of the root device and deserializing data received from at the input port to the internal CBA bus segment of the first device. The remote external physical device includes a second serial communications interface module coupled between the internal CBA bus segment and an input and output port of the remote device for serializing bus transactions from the remote device to the output port of the remote device and deserializing data received at the input port to the internal CBA bus segment of said remote device. The modules are coupled to each other by an external cabling. An enumerator in the root device obtains knowledge of the remote hardware module and accompanying register set by abstracting these details and automatically configuring the remote module in the system.
摘要翻译：用于使第一根物理设备的内部公共总线架构（CBA）段扩展到一个或多个远程外部物理设备的内部CBA总线段的通信系统包括具有第一串行通信接口模块的第一根物理设备所述根设备耦合在所述内部CBA总线段和根设备的输入和输出端口之间，用于将从第一设备到根设备的输出端口的总线事务串行化，并且将从输入端口接收的数据反序列化为内部CBA总线第一个设备的段。远程外部物理设备包括耦合在内部CBA总线段和远程设备的输入和输出端口之间的第二串行通信接口模块，用于将从远程设备到远程设备的输出端口的总线事务串行化，并且反序列化在所述远程设备的内部CBA总线段的输入端口。模块通过外部电缆相互耦合。根设备中的枚举器通过抽象出这些细节并自动配置系统中的远程模块，获得远程硬件模块和附带注册集的知识。

3. 发明授权

US06690668B1 Modular interconnection of network switches 有权
标题翻译：网络交换机的模块化互连
公开(公告)号：US06690668B1
公开(公告)日：2004-02-10
申请号：US09410287
申请日：1999-09-30
申请人： Andre Szczepanek , Denis R. Beaudoin , Iain Robertson
发明人： Andre Szczepanek , Denis R. Beaudoin , Iain Robertson
IPC分类号： H04L1256
CPC分类号： H04L49/351 , H04L49/101 , H04L49/352 , H04L49/45 , H04L49/506 , H04L49/90 , H04L49/901 , H04L49/9047
摘要： Network switching systems (10, 110, 210, 310, 410) for use in an Ethernet network are disclosed. Each of the switching systems includes switch devices (20) supporting multiple (e.g., eight) local ports, and one gigabit high-speed port; each of the high-speed ports are full-duplex ports. Each switching system also includes a gigabit switch device (30) having two full-duplex gigabit ports. According to one aspect of the invention, the switches (20, 30) are connected in a ring using their respective gigabit ports, with each of the switches (20, 30) having a Ring ID value. Upon receipt of a message packet at one of its local ports, the switches (20) attach a pretag with the Ring ID value upon the packet, and begin forwarding the packet around the ring until the destination address is registered with one of the switches (20, 30), or until the packet returns to the original switch (20) which, upon detecting its own Ring ID value, filters or discards the packet. According to another aspect of the invention, switches (20) have their gigabit ports connected to a crossbar-matrix switch (100); pretags added by the switches to their received packets indicate the crossbar ports to which the packets are addressed. According to another aspect of the invention, each of the switches (20, 30) applies flow control over the gigabit ports in response to a message occupying more buffer space than remaining buffers; this permits buffer space to be utilized when traffic permits, without allowing a small minority of channels to adversely affect others.
摘要翻译：公开了一种用于以太网的网络交换系统（10,110,210,310,410）。每个交换系统包括支持多个（例如八个）本地端口和一个千兆位高速端口的交换设备（20）每个高速端口都是全双工端口。每个交换系统还包括具有两个全双工千兆端口的千兆交换设备（30）。根据本发明的一个方面，开关（20,30）使用它们各自的千兆端口以环形连接，每个开关（20,30）具有环ID值。在其一个本地端口上接收到消息分组时，交换机（20）在分组上附加具有Ring ID值的预加号，并开始转发该分组在环周围，直到目的地址被注册到其中一个交换机（或者直到分组返回到原始交换机（20），该原始交换机（20）在检测到其自己的Ring ID值时，过滤或丢弃该分组。根据本发明的另一方面，开关（20）的千兆端口连接到交叉开关矩阵开关（100）; 由交换机添加到他们接收的分组的预加号指示分组被寻址到的交叉口端口。根据本发明的另一方面，每个开关（20,30）响应于占用比剩余缓冲器更多的缓冲器空间的消息，对千兆位端口进行流量控制; 这允许在交通许可时利用缓冲区空间，而不允许少量渠道对其他渠道产生不利影响。

4. 发明授权

US06621818B1 Ring configuration for network switches 有权
标题翻译：网络交换机的环形配置
公开(公告)号：US06621818B1
公开(公告)日：2003-09-16
申请号：US09410206
申请日：1999-09-30
申请人： Andre Szczepanek , Denis R. Beaudoin , Iain Robertson
发明人： Andre Szczepanek , Denis R. Beaudoin , Iain Robertson
IPC分类号： H04L1256
CPC分类号： H04L49/351 , H04L12/42 , H04L47/10 , H04L47/26 , H04L47/30 , H04L49/101 , H04L49/3009 , H04L49/352
摘要： Network switching systems (10, 110, 210, 310, 410) for use in an Ethernet network are disclosed. Each of the switching systems includes switch devices (20) supporting multiple (e.g., eight) local ports, and one gigabit high-speed port; each of the high-speed ports are full-duplex ports. Each switching system also includes a gigabit switch device (30) having two full-duplex gigabit ports. According to one aspect of the invention, the switches (20, 30) are connected in a ring using their respective gigabit ports, with each of the switches (20, 30) having a Ring ID value. Upon receipt of a message packet at one of its local ports, the switches. (20) attach a pretag with the Ring ID value upon the packet, and begin forwarding the packet around the ring until the destination address is registered with one of the switches (20, 30), or until the packet returns to the original switch (20) which, upon detecting its own Ring ID value, filters or discards the packet. According to another aspect of the invention, switches (20) have their gigabit ports connected to a crossbar-matrix switch (100); pretags added by the switches to their received packets indicate the crossbar ports to which the packets are addressed. According to another aspect of the invention, each of the switches (20, 30) applies flow control over the gigabit ports in response to a message occupying more buffer space than remaining buffers; this permits buffer space to be utilized when traffic permits, without allowing a small minority of channels to adversely affect others.
摘要翻译：公开了一种用于以太网的网络交换系统（10,110,210,310,410）。每个交换系统包括支持多个（例如八个）本地端口和一个千兆位高速端口的交换设备（20）每个高速端口都是全双工端口。每个交换系统还包括具有两个全双工千兆端口的千兆交换设备（30）。根据本发明的一个方面，开关（20,30）使用它们各自的千兆端口以环形连接，每个开关（20,30）具有环ID值。在其本地端口之一接收到消息分组时，交换机。（20）在分组上附加具有Ring ID值的预加号码，并且开始转发环上的分组，直到目的地址被注册到其中一个交换机（20,30），或者直到分组返回到原始交换机 20），在检测到自己的Ring ID值后，过滤或丢弃该数据包。根据本发明的另一方面，开关（20）的千兆端口连接到交叉开关矩阵开关（100）; 由交换机添加到他们接收的分组的预加号指示分组被寻址到的交叉口端口。根据本发明的另一方面，每个开关（20,30）响应于占用比剩余缓冲器更多的缓冲器空间的消息，对千兆位端口进行流量控制; 这允许在交通许可时利用缓冲区空间，而不允许少量渠道对其他渠道产生不利影响。

5. 发明授权

US07644135B2 Method of improving communications data throughput on embedded systems and reducing the load on the operating system and central processing unit 有权
标题翻译：提高嵌入式系统通信数据吞吐量，减少操作系统和中央处理单元负载的方法
公开(公告)号：US07644135B2
公开(公告)日：2010-01-05
申请号：US10972956
申请日：2004-10-25
申请人： Michael J. Hanrahan , Denis R. Beaudoin
发明人： Michael J. Hanrahan , Denis R. Beaudoin
IPC分类号： G06F15/16 , G06F15/173 , G06F15/177
CPC分类号： H04L45/00 , H04L45/60 , H04L49/90 , H04L69/12
摘要： A method is provided for dramatically improving communications data throughput on embedded systems and reducing the load on the operating system and central processing unit by moving the network protocol logic nearer to the underlying communication hardware, and utilizing the communication processor hardware abstraction layer (CPHAL) concepts. This movement of the network protocol logic allows leveraging the CPHAL data structures, which are tightly bound to the communication packets being processed. The decision making is made just above the CPHAL layer; and the CPHAL data structure is preserved. Copying data is avoided by manipulating of pointers within the CPHAL buffer.
摘要翻译：提供了一种方法，用于通过将网络协议逻辑更靠近底层通信硬件，并利用通信处理器硬件抽象层（CPHAL）概念，显着提高嵌入式系统上的通信数据吞吐量，并降低操作系统和中央处理单元的负担。网络协议逻辑的这种移动允许利用紧密结合到正在处理的通信分组的CPHAL数据结构。决策在CPHAL层之上; 并保留CPHAL数据结构。通过处理CPHAL缓冲区中的指针来避免复制数据。

6. 发明授权

US07027447B2 Communications interface between clock domains with minimal latency 有权
标题翻译：时钟域之间的通信接口，延迟最小
公开(公告)号：US07027447B2
公开(公告)日：2006-04-11
申请号：US09755825
申请日：2001-01-05
申请人： Iain Robertson , Andre Szczepanek , Denis R. Beaudoin
发明人： Iain Robertson , Andre Szczepanek , Denis R. Beaudoin
IPC分类号： H04L12/42
CPC分类号： H04L7/0012 , H04L7/005
摘要： A network switch system (10) is disclosed, in which a plurality of switch fabric devices (20) are interconnected according to a ring arrangement, each of the switch fabric devices (20) including therein switch interfaces (22) coupled to corresponding network switches (14, 16). Each switch fabric device includes a plurality of ring paths (24), each of which is associated with a receive ring interface (26R) and a transmit ring interface (26X). Each ring path (24) includes a circular buffer (44) having a plurality of entries, each of which is associated with valid logic (50). The valid logic (50) for each entry presents valid signals on valid lines (WV, RV) to the receive and transmit domains of the ring path (24), and receives signals on write and read word request lines (WRW, RDW) therefrom. Control of the access to the circular buffer (44) is made according to the write and read word request lines (WRW, RDW) for the corresponding entries of the circular buffer (44) to which write pointers and read pointers point. The write word request line (WRW) sets the valid lines (WV, RV) for the corresponding entry in each of the two clock domains, while the read word request line (RDW) resets these valid lines (WV, RV) for that entry. Differences in clock frequency between the receive and transmit clock domains are thus compensated, with a minimum latency.
摘要翻译：公开了一种网络交换机系统（10），其中多个交换结构设备（20）根据环形布置互连，每个交换结构设备（20）包括其中耦合到相应网络交换机的交换接口（22）（14,16）。每个交换结构设备包括多个环路（24），每个环路与接收环接口（26R）和发射环接口（26X）相关联。每个环路（24）包括具有多个条目的循环缓冲器（44），每个条目与有效逻辑（50）相关联。每个条目的有效逻辑（50）在有效的线路（WV，RV）上呈现环路径（24）的接收和发射域的有效信号，并且从写入和读取字请求线（WRW，RDW）接收信号。根据写指针和读指针指向的循环缓冲器（44）的对应条目的写和读字请求行（WRW，RDW），对对循环缓冲器（44）的访问进行控制。写字请求行（WRW）为两个时钟域中的每个时钟域中的相应条目设置有效行（WV，RV），而读字请求行（RDW）为这个条目复位这些有效行（WV，RV）。因此，接收时钟和发送时钟域之间的时钟频率的差异将以最小的延迟进行补偿。

7. 发明授权

US5717932A Data transfer interrupt pacing 失效
标题翻译：数据传输中断起搏
公开(公告)号：US5717932A
公开(公告)日：1998-02-10
申请号：US334511
申请日：1994-11-04
申请人： Andre Szczepanek , Denis R. Beaudoin
发明人： Andre Szczepanek , Denis R. Beaudoin
IPC分类号： G06F13/24 , G06F13/00
CPC分类号： G06F13/24 , G06F2213/2404
摘要： A communications network adapter of the type coupling a computer, in which the computer includes a microprocessor, main memory and a system bus, that controls host interrupts in a manner to improve system performance. The adapter includes a buffer memory for storing data to be transferred between the bus an the network, and a transfer controller that controls the transfer of data between the main memory and the buffer memory and between the network and the buffer memory. The adapter also includes an interrupt controller that monitors predetermined events relating to data transfer between the computer and the network, and that causes the sending of interrupt signals to the microprocessor. Interrupt signals cause the microprocessor to initiate processing associated with the transfer of data between the computer and the network. According to one aspect of the invention the adapter includes an interrupt pacing timer that prevents the sending of interrupts to the microprocessor from the adapter for predetermined time after an interrupt acknowledgement signal is received from the microprocessor. According to another aspect of the invention an interrupt threshold counter is provided that prevents the sending of interrupts to the microprocessor until a predetermined plurality of frames are transmitted.
摘要翻译：一种耦合计算机的通信网络适配器，其中计算机包括微处理器，主存储器和系统总线，其以提高系统性能的方式来控制主机中断。适配器包括用于存储要在总线与网络之间传送的数据的缓冲存储器，以及控制主存储器和缓冲存储器之间以及网络与缓冲存储器之间的数据传送的传输控制器。适配器还包括中断控制器，其监视与计算机和网络之间的数据传输相关的预定事件，并且导致向微处理器发送中断信号。中断信号使微处理器发起与计算机和网络之间的数据传输相关的处理。根据本发明的一个方面，适配器包括中断起搏定时器，其在从微处理器接收到中断确认信号之后的预定时间内防止从适配器向微处理器发送中断。根据本发明的另一方面，提供了一种中断阈值计数器，其防止向微处理器发送中断，直到发送预定的多个帧。

8. 发明授权

US06400715B1 Network address matching circuit and method 失效
标题翻译：网络地址匹配电路及方法
公开(公告)号：US06400715B1
公开(公告)日：2002-06-04
申请号：US08715684
申请日：1996-09-18
申请人： Denis R. Beaudoin , Jose M. Menendez
发明人： Denis R. Beaudoin , Jose M. Menendez
IPC分类号： H04L1256
CPC分类号： H04L49/25 , H04L49/254 , H04L49/351
摘要： A communications system with a circuit having a plurality of communications ports capable of multispeed operation and operable in a first mode that includes address resolution and in a second mode that excludes address resolution and includes a first memory, a plurality of protocol handlers, a bus connected to the protocol handlers, a second memory connected to the bus and a memory controller connected to the bus and the second memory for selectively comparing addresses, transferring data between the protocol handlers and the second memory, and transferring data between the second memory and the first memory. A first embodiment is a local area network controller having a first circuit with a plurality of communications ports capable of multispeed operation and operable in a first mode that includes address resolution and in a second mode that excludes address resolution, and an address lookup circuit interconnected with the first circuit. An integrated circuit having a plurality of protocol handlers, a bus connected to the protocol handlers, a memory connected to the bus, and a memory controller connected to the bus and the memory for selectively comparing addresses, transferring data between the protocol handlers and the memory, and transferring between the memory and an external memory is provided. The address matching circuit has a memory for containing addresses arranged in a linked list, a first state machine for creating and updating the linked list of addresses, a second state machine for provided routing information for a selected address based upon the linked list of addresses and a bus watcher circuit for monitoring data traffic on a bus to detect addresses. An alternative address matching circuit is also provided.
摘要翻译：一种具有电路的通信系统，其具有能够进行多速操作的多个通信端口，并且可在包括地址解析的第一模式中操作，并且在第二模式中排除地址解析，并且包括第一存储器，多个协议处理器，总线连接到协议处理器，连接到总线的第二存储器和连接到总线的存储器控制器和第二存储器，用于选择性地比较地址，在协议处理器和第二存储器之间传送数据，以及在第二存储器和第一存储器之间传送数据记忆。第一实施例是具有第一电路的局域网控制器，该第一电路具有能够进行多速操作的多个通信端口，并且可以在包括地址解析的第一模式和在排除地址解析的第二模式中操作，以及与第一个电路。具有多个协议处理器的集成电路，连接到协议处理器的总线，连接到总线的存储器以及连接到总线和存储器的存储器控制器，用于选择性地比较地址，在协议处理器和存储器之间传送数据，并且提供在存储器和外部存储器之间的转移。地址匹配电路具有用于包含链接列表中布置的地址的存储器，用于创建和更新链接的地址列表的第一状态机，用于根据链接的地址列表为所选地址提供的路由信息的第二状态机，以及总线监视器电路，用于监视总线上的数据流量以检测地址。还提供了另一种地址匹配电路。

9. 发明授权

US5404450A Communications processor system with control of downloaded tasks 失效
标题翻译：具有控制下载任务的通讯处理器系统
公开(公告)号：US5404450A
公开(公告)日：1995-04-04
申请号：US24893
申请日：1993-03-01
申请人： Andre Szczepanek , Denis R. Beaudoin
发明人： Andre Szczepanek , Denis R. Beaudoin
IPC分类号： G06F9/445 , H04Q3/545 , G06F15/16
CPC分类号： H04Q3/54516 , G06F9/445 , H04Q2213/1305 , H04Q2213/13109 , H04Q2213/13376
摘要： A communications processor system 10b that permits communications task code to be safely downloaded from a host system. Direct access to local memory 15b of the communications processor system 10b is permitted only during a downloading process while system 10b in a reset state. This downloading process is implemented with a special control register. In user mode, the system 10b controls access to local memory 15b by downloaded task code. Specifically, access is prohibited with respect to privileged memory areas, and is limited to a relatively small predetermined range of addresses with respect to other memory areas. This memory protection process is implemented with a special status register and a number of mapping registers.
摘要翻译：允许从主机系统安全地下载通信任务代码的通信处理器系统10b。只有在下载过程中才允许对通信处理器系统10b的本地存储器15b的直接访问，同时系统10b处于复位状态。该下载过程由特殊控制寄存器实现。在用户模式下，系统10b通过下载的任务代码控制对本地存储器15b的访问。具体地说，就特权存储区域而言，禁止访问，并且被限制在相对于其他存储区域的相对较小的预定地址范围。该存储器保护过程由特殊的状态寄存器和多个映射寄存器来实现。

10. 发明授权

US07096301B2 Communications interface for enabling extension of an internal common bus architecture (CBA) 有权
标题翻译：用于扩展内部公共总线架构（CBA）的通信接口
公开(公告)号：US07096301B2
公开(公告)日：2006-08-22
申请号：US10382679
申请日：2003-03-06
申请人： Denis R. Beaudoin , Brian Karguth , James H. Kennedy
发明人： Denis R. Beaudoin , Brian Karguth , James H. Kennedy
IPC分类号： G06F1/00
CPC分类号： G06F13/426 , G06F13/26 , H04L69/08
摘要： A serial communications interface is described that enables the extension of an internal Communications Bus Architecture (CBA) bus segment to one or more external devices. The interface accomplishes this function by serializing bus transactions in one device, transferring the serial transaction between devices via one interface port, and de-serializing the transaction in the external device. The general features include low pin count (as few as three signals), simple packet based transfer protocol for memory mapped access, symmetric operation, simple block code formatting, supports both host to peripheral and peer to peer transactions, and support multiple outstanding transactions.
摘要翻译：描述了能够将内部通信总线架构（CBA）总线段扩展到一个或多个外部设备的串行通信接口。该接口通过串行化一个设备中的总线事务，通过一个接口端口在设备之间传输串行事务以及在外部设备中反序列化事务来完成此功能。一般功能包括低引脚数（少至三个信号），用于存储器映射访问的简单的基于分组的传输协议，对称操作，简单的块代码格式化，支持主机到外设和对等交易，并支持多个未完成的事务。

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