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1. 发明申请

US20130290984A1 Method for Infrastructure Messaging 有权
标题翻译：基础设施消息传递方法
公开(公告)号：US20130290984A1
公开(公告)日：2013-10-31
申请号：US13459212
申请日：2012-04-29
申请人： Michael A. Denio , Brian Karguth , Akila Subramaniam , Charles Fuoco
发明人： Michael A. Denio , Brian Karguth , Akila Subramaniam , Charles Fuoco
IPC分类号： G06F9/46
CPC分类号： G06F9/546 , G06F2209/548
摘要： A low overhead method to handle inter process and peer to peer communication. A queue manager is used to create a list of messages with minimal configuration overhead. A hardware queue can be connected to another software task owned by the same core or a different processor core, or connected to a hardware DMA peripheral. There is no limitation on how many messages can be queued between the producer and consumer cores. The low latency interrupt generation to the processor cores is handled by an accumulator inside the QMSS which can be configured to generate interrupts based on a programmable threshold of descriptors in a queue. The accumulator thus removes the polling overhead from software and boosts performance by doing the descriptor pops and message transfer in the background.
摘要翻译：一种低开销的处理流程和对等通信的方法。队列管理器用于以最少的配置开销创建消息列表。硬件队列可以连接到由同一核心或不同处理器内核拥有的另一个软件任务，或连接到硬件DMA外设。在生产者和消费者核心之间排队的邮件数量没有限制。处理器内核的低延迟中断产生由QMSS内的累加器来处理，该累加器可以配置为基于队列中描述符的可编程阈值产生中断。因此，累加器消除了软件的轮询开销，并通过在后台执行描述符弹出和消息传输来提高性能。

2. 发明授权

US09015376B2 Method for infrastructure messaging 有权
标题翻译：基础设施信息的方法
公开(公告)号：US09015376B2
公开(公告)日：2015-04-21
申请号：US13459212
申请日：2012-04-29
申请人： Michael A. Denio , Brian Karguth , Akila Subramaniam , Charles Fuoco
发明人： Michael A. Denio , Brian Karguth , Akila Subramaniam , Charles Fuoco
IPC分类号： G06F3/00 , G06F15/16 , G06F9/54
CPC分类号： G06F9/546 , G06F2209/548
摘要： A low overhead method to handle inter process and peer to peer communication. A queue manager is used to create a list of messages with minimal configuration overhead. A hardware queue can be connected to another software task owned by the same core or a different processor core, or connected to a hardware DMA peripheral. There is no limitation on how many messages can be queued between the producer and consumer cores. The low latency interrupt generation to the processor cores is handled by an accumulator inside the QMSS which can be configured to generate interrupts based on a programmable threshold of descriptors in a queue. The accumulator thus removes the polling overhead from software and boosts performance by doing the descriptor pops and message transfer in the background.
摘要翻译：一种低开销的处理流程和对等通信的方法。队列管理器用于以最少的配置开销创建消息列表。硬件队列可以连接到由同一核心或不同处理器内核拥有的另一个软件任务，或连接到硬件DMA外设。在生产者和消费者核心之间排队的邮件数量没有限制。处理器内核的低延迟中断产生由QMSS内的累加器来处理，该累加器可以配置为基于队列中描述符的可编程阈值产生中断。因此，累加器消除了软件的轮询开销，并通过在后台执行描述符弹出和消息传输来提高性能。

3. 发明授权

US08542693B2 Managing free packet descriptors in packet-based communications 有权
标题翻译：在基于分组的通信中管理自由的分组描述符
公开(公告)号：US08542693B2
公开(公告)日：2013-09-24
申请号：US12181831
申请日：2008-07-29
申请人： Maneesh Soni , Brian J. Karguth , Michael A. Denio
发明人： Maneesh Soni , Brian J. Karguth , Michael A. Denio
IPC分类号： H04L12/28
CPC分类号： H04L49/901 , H04L47/50 , H04L49/90 , H04L49/9073
摘要： A network element including a processor with logic for managing packet queues including a queue of free packet descriptors. Upon the transmission of a packet by a host application, the packet descriptor for the transmitted packet is added to the free packet descriptor queue. If the new free packet descriptor resides in on-chip memory, relative to queue manager logic, it is added to the head of the free packet descriptor queue; if the new free packet descriptor resides in external memory, it is added to the tail of the free packet descriptor queue. Upon a packet descriptor being requested to be associated with valid data to be added to an active packet queue, the queue manager logic pops the packet descriptor currently at the head of the free descriptor queue. Packet descriptors in on-chip memory are preferentially used relative to packet descriptors in external memory.
摘要翻译：一种网元，包括具有用于管理分组队列的逻辑的处理器，包括空闲分组描述符队列。在由主机应用发送分组时，将所发送的分组的分组描述符添加到空闲分组描述符队列。如果新的空闲分组描述符驻留在片上存储器中，相对于队列管理器逻辑，它被添加到空闲分组描述符队列的头部; 如果新的空闲分组描述符驻留在外部存储器中，则将其添加到空闲分组描述符队列的尾部。在要求将分组描述符与要添加到活动分组队列的有效数据相关联时，队列管理器逻辑弹出当前在空闲描述符队列的头部的分组描述符。相对于外部存储器中的分组描述符优先使用片上存储器中的分组描述符。

4. 发明授权

US5269021A Multiprocessor software interface for a graphics processor subsystem employing partially linked dynamic load modules which are downloaded and fully linked at run time 失效
标题翻译：使用部分链接的动态加载模块的图形处理器子系统的多处理器软件接口，这些模块在运行时被下载并完全链接
公开(公告)号：US5269021A
公开(公告)日：1993-12-07
申请号：US420409
申请日：1989-10-12
申请人： Michael A. Denio , William S. Egr , Douglas C. Crawford , Michael D. Asal , Graham Short , James G. Littleton , Jerry R. Van Aken
发明人： Michael A. Denio , William S. Egr , Douglas C. Crawford , Michael D. Asal , Graham Short , James G. Littleton , Jerry R. Van Aken
IPC分类号： G06F9/40 , G06F9/445 , G06F15/16
CPC分类号： G06F9/4425 , G06F9/44521
摘要： An interface for use with a multiprocessor computer system, having a host processor system and a graphics processor system. The interface permits extended functions to be developed on the host system or on another system, and subsequently loaded to the graphics processor system. The interface comprises software residing on both the host system side and the graphics system side, which operates at run time to permit the function to be called from a main program running on the host. The function's arguments are passed to the graphics system so that the function is executed by the graphics processor.
摘要翻译：一种与多处理器计算机系统一起使用的接口，具有主处理器系统和图形处理器系统。该接口允许在主机系统或另一个系统上开发扩展功能，并随后加载到图形处理器系统。该接口包括驻留在主机系统侧和图形系统侧的软件，其在运行时操作以允许从主机上运行的主程序调用该功能。该函数的参数传递给图形系统，以使该函数由图形处理器执行。

5. 发明授权

US08059670B2 Hardware queue management with distributed linking information 有权
标题翻译：具有分布式链接信息的硬件队列管理
公开(公告)号：US08059670B2
公开(公告)日：2011-11-15
申请号：US12181802
申请日：2008-07-29
申请人： Maneesh Soni , Brian J. Karguth , Michael A. Denio
发明人： Maneesh Soni , Brian J. Karguth , Michael A. Denio
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L49/901 , H04L49/90
摘要： A network element including a processor with logic for managing packet queues by way of packet descriptor index values that are mapped to addresses in the memory space of the packet descriptors. A linking memory is implemented in the same integrated circuit as the processor, and has entries corresponding to the descriptor index values. Each entry can store the next descriptor index in a packet queue, to form a linked list of packet descriptors. Queue manager logic receives push and pop requests from host applications, and updates the linking memory to maintain the queue. The queue manager logic also maintains a queue control register for each queue, including head and tail descriptor index values.
摘要翻译：一种网元，包括具有逻辑的处理器，用于通过映射到分组描述符的存储器空间中的地址的分组描述符索引值来管理分组队列。链接存储器在与处理器相同的集成电路中实现，并具有对应于描述符索引值的条目。每个条目可以将下一个描述符索引存储在分组队列中，以形成分组描述符的链表。队列管理器逻辑从主机应用程序接收推送和弹出请求，并更新链接内存以维护队列。队列管理器逻辑还为每个队列维护一个队列控制寄存器，包括头部和尾部描述符索引值。

6. 发明申请

US20090034549A1 Managing Free Packet Descriptors in Packet-Based Communications 有权
标题翻译：在基于分组的通信中管理自由分组描述符
公开(公告)号：US20090034549A1
公开(公告)日：2009-02-05
申请号：US12181831
申请日：2008-07-29
申请人： Maneesh Soni , Brian J. Karguth , Michael A. Denio
发明人： Maneesh Soni , Brian J. Karguth , Michael A. Denio
IPC分类号： H04L12/56
CPC分类号： H04L49/901 , H04L47/50 , H04L49/90 , H04L49/9073
摘要： A network element including a processor with logic for managing packet queues including a queue of free packet descriptors. Upon the transmission of a packet by a host application, the packet descriptor for the transmitted packet is added to the free packet descriptor queue. If the new free packet descriptor resides in on-chip memory, relative to queue manager logic, it is added to the head of the free packet descriptor queue; if the new free packet descriptor resides in external memory, it is added to the tail of the free packet descriptor queue. Upon a packet descriptor being requested, by a host application, to be associated with valid data to be added to an active packet queue, the queue manager logic pops the packet descriptor currently at the head of the free descriptor queue. In this manner, packet descriptors in on-chip memory are preferentially used relative to packet descriptors in external memory, thus improving system performance.
摘要翻译：一种网元，包括具有用于管理分组队列的逻辑的处理器，包括空闲分组描述符队列。在由主机应用发送分组时，将所发送的分组的分组描述符添加到空闲分组描述符队列。如果新的空闲分组描述符驻留在片上存储器中，相对于队列管理器逻辑，它被添加到空闲分组描述符队列的头部; 如果新的空闲分组描述符驻留在外部存储器中，则将其添加到空闲分组描述符队列的尾部。在由主机应用请求与要加入到活动分组队列的有效数据相关联的分组描述符时，队列管理器逻辑弹出当前位于空闲描述符队列头部的分组描述符。以这种方式，相对于外部存储器中的分组描述符优先使用片上存储器中的分组描述符，从而提高系统性能。

7. 发明授权

US5638424A Telephone voice mail delivery system 失效
标题翻译：电话语音邮件传送系统
公开(公告)号：US5638424A
公开(公告)日：1997-06-10
申请号：US610079
申请日：1996-02-29
申请人： Michael A. Denio , James G. Littleton
发明人： Michael A. Denio , James G. Littleton
IPC分类号： H04M1/65 , H04M3/533 , H04M1/64
CPC分类号： H04M1/6505 , H04M3/533
摘要： Apparatus and a method are disclosed for establishing communication between a sending system and a receiving system. Upon initiation of the communication, the sending system sequentially monitors the receiving system for a response from one of a human interface, a non-cooperating system or a cooperating system. If a response from a human interface within the receiving system is received by the sending system, the sending system transmits a message to a human. If a response is not received from a human interface but is received from a non-cooperating system within the receiving system, the sending system transmits a message to an answering machine. If a response is not received from a human interface or a non-cooperating system, but is received from a cooperating system within the receiving system, information is exchanged between the sending system and the cooperating system in an attempt to establish communication.
摘要翻译：公开了用于建立发送系统和接收系统之间的通信的装置和方法。在通信开始时，发送系统从人机接口，非协作系统或协作系统之一顺序地监视接收系统的响应。如果发送系统接收到来自接收系统内的人机接口的响应，则发送系统向人发送消息。如果没有从人机界面接收到响应，但是从接收系统内的非协作系统接收到响应，则发送系统向应答机发送消息。如果没有从人机接口或非协作系统接收到响应，但是从接收系统内的协作系统接收到响应，则在发送系统和协作系统之间交换信息以试图建立通信。

8. 发明授权

US5404519A System for extending software calls to functions on another processor by means of a communications buffer 失效
标题翻译：用于通过通信缓冲区将软件调用扩展到另一个处理器上的功能的系统
公开(公告)号：US5404519A
公开(公告)日：1995-04-04
申请号：US25910
申请日：1993-03-03
申请人： Michael A. Denio
发明人： Michael A. Denio
IPC分类号： G06F9/46 , G06F9/40
CPC分类号： G06F9/544 , G06F9/547
摘要： A method is provided for adding extended functions to a multiprocessor system, specifically, functions that may be called from programming running on a first processor and executed by a second processor. A set of generic entry point commands is provided. Each extended function is associated with an entry point command, that is appropriate for the function's argument format and return requirements, if any. Each entry point command invokes a communications routine that handles the transfer of argument data and return values, if any, between processors.
摘要翻译：提供了一种用于将扩展功能添加到多处理器系统的方法，具体地，可以从在第一处理器上运行并由第二处理器执行的编程调用的函数。提供了一组通用入口点命令。每个扩展函数都与入口点命令相关联，适用于函数的参数格式和返回要求（如果有）。每个入口点命令调用处理参数数据传输和处理器之间的返回值（如果有的话）的通信例程。

9. 发明授权

US5355485A First processor for dividing long argument data into packets and storing total packet count and packets in shared buffer for subsequent execution by second processor 失效
标题翻译：第一个处理器用于将长参数数据分成数据包，并将总数据包数和数据包存储在共享缓冲区中，以供后续处理器执行
公开(公告)号：US5355485A
公开(公告)日：1994-10-11
申请号：US25901
申请日：1993-03-03
申请人： Michael A. Denio , James G. Littleton
发明人： Michael A. Denio , James G. Littleton
IPC分类号： G06F15/16 , G06F9/38 , G06F9/42 , G06F9/54 , G06F15/17 , G06F15/177 , G06F13/00
CPC分类号： G06F9/3879 , G06F15/17 , G06F9/4426
摘要： A method is provided for adding extended functions to a multiprocessor system, specifically, functions that may be called from programming running on a first processor and executed by a second processor. The function may have an argument that requires a large amount of argument data. Each extended function is associated with a special entry point command, which is in turn, associated with a communications routine that handles the transfer of the large argument data from the first processor to the second processor in bursts.
摘要翻译：提供了一种用于将扩展功能添加到多处理器系统的方法，具体地，可以从在第一处理器上运行并由第二处理器执行的编程调用的函数。该函数可能有一个需要大量参数数据的参数。每个扩展功能都与一个特殊的入口点命令相关联，特殊的入口点命令又与处理从第一个处理器到第二个处理器的突发传送大型参数数据的通信程序相关联。

10. 发明申请

US20090034548A1 Hardware Queue Management with Distributed Linking Information 有权
标题翻译：具有分布式链接信息的硬件队列管理
公开(公告)号：US20090034548A1
公开(公告)日：2009-02-05
申请号：US12181802
申请日：2008-07-29
申请人： Maneesh Soni , Brian J. Karguth , Michael A. Denio
发明人： Maneesh Soni , Brian J. Karguth , Michael A. Denio
IPC分类号： H04L12/56
CPC分类号： H04L49/901 , H04L49/90
摘要： A network element including a processor with logic for managing packet queues by way of packet descriptor index values that are mapped to addresses in the memory space of the packet descriptors. A linking memory is implemented in the same integrated circuit as the processor, and has entries corresponding to the descriptor index values. Each entry can store the next descriptor index in a packet queue, to form a linked list of packet descriptors. Queue manager logic receives push and pop requests from host applications, and updates the linking memory to maintain the queue. The queue manager logic also maintains a queue control register for each queue, including head and tail descriptor index values.
摘要翻译：一种网元，包括具有逻辑的处理器，用于通过映射到分组描述符的存储器空间中的地址的分组描述符索引值来管理分组队列。链接存储器在与处理器相同的集成电路中实现，并具有对应于描述符索引值的条目。每个条目可以将下一个描述符索引存储在分组队列中，以形成分组描述符的链表。队列管理器逻辑从主机应用程序接收推送和弹出请求，并更新链接内存以维护队列。队列管理器逻辑还为每个队列维护一个队列控制寄存器，包括头部和尾部描述符索引值。

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