专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09015376B2 Method for infrastructure messaging 有权
标题翻译：基础设施信息的方法
公开(公告)号：US09015376B2
公开(公告)日：2015-04-21
申请号：US13459212
申请日：2012-04-29
申请人： Michael A. Denio , Brian Karguth , Akila Subramaniam , Charles Fuoco
发明人： Michael A. Denio , Brian Karguth , Akila Subramaniam , Charles Fuoco
IPC分类号： G06F3/00 , G06F15/16 , G06F9/54
CPC分类号： G06F9/546 , G06F2209/548
摘要： A low overhead method to handle inter process and peer to peer communication. A queue manager is used to create a list of messages with minimal configuration overhead. A hardware queue can be connected to another software task owned by the same core or a different processor core, or connected to a hardware DMA peripheral. There is no limitation on how many messages can be queued between the producer and consumer cores. The low latency interrupt generation to the processor cores is handled by an accumulator inside the QMSS which can be configured to generate interrupts based on a programmable threshold of descriptors in a queue. The accumulator thus removes the polling overhead from software and boosts performance by doing the descriptor pops and message transfer in the background.
摘要翻译：一种低开销的处理流程和对等通信的方法。队列管理器用于以最少的配置开销创建消息列表。硬件队列可以连接到由同一核心或不同处理器内核拥有的另一个软件任务，或连接到硬件DMA外设。在生产者和消费者核心之间排队的邮件数量没有限制。处理器内核的低延迟中断产生由QMSS内的累加器来处理，该累加器可以配置为基于队列中描述符的可编程阈值产生中断。因此，累加器消除了软件的轮询开销，并通过在后台执行描述符弹出和消息传输来提高性能。

2. 发明申请

US20130290984A1 Method for Infrastructure Messaging 有权
标题翻译：基础设施消息传递方法
公开(公告)号：US20130290984A1
公开(公告)日：2013-10-31
申请号：US13459212
申请日：2012-04-29
申请人： Michael A. Denio , Brian Karguth , Akila Subramaniam , Charles Fuoco
发明人： Michael A. Denio , Brian Karguth , Akila Subramaniam , Charles Fuoco
IPC分类号： G06F9/46
CPC分类号： G06F9/546 , G06F2209/548
摘要： A low overhead method to handle inter process and peer to peer communication. A queue manager is used to create a list of messages with minimal configuration overhead. A hardware queue can be connected to another software task owned by the same core or a different processor core, or connected to a hardware DMA peripheral. There is no limitation on how many messages can be queued between the producer and consumer cores. The low latency interrupt generation to the processor cores is handled by an accumulator inside the QMSS which can be configured to generate interrupts based on a programmable threshold of descriptors in a queue. The accumulator thus removes the polling overhead from software and boosts performance by doing the descriptor pops and message transfer in the background.
摘要翻译：一种低开销的处理流程和对等通信的方法。队列管理器用于以最少的配置开销创建消息列表。硬件队列可以连接到由同一核心或不同处理器内核拥有的另一个软件任务，或连接到硬件DMA外设。在生产者和消费者核心之间排队的邮件数量没有限制。处理器内核的低延迟中断产生由QMSS内的累加器来处理，该累加器可以配置为基于队列中描述符的可编程阈值产生中断。因此，累加器消除了软件的轮询开销，并通过在后台执行描述符弹出和消息传输来提高性能。

3. 发明申请

US20130054852A1 Deadlock Avoidance in a Multi-Node System 审中-公开
标题翻译：多节点系统中的死锁避免
公开(公告)号：US20130054852A1
公开(公告)日：2013-02-28
申请号：US13216572
申请日：2011-08-24
申请人： Charles Fuoco , Akila Subramaniam
发明人： Charles Fuoco , Akila Subramaniam
IPC分类号： G06F13/00
CPC分类号： G06F9/524 , G06F13/4022
摘要： Transaction requests in an interconnect fabric in a system with multiple nodes are managed in a manner that prevents deadlocks. One or more patterns of transaction requests from a master device to various slave devices within the multiple nodes that may cause a deadlock are determined. While the system is in operation, an occurrence of one of the patterns is detected by observing a sequence of transaction requests from the master device. A transaction request in the detected pattern is stalled to allow an earlier transaction request to complete in order to prevent a deadlock.
摘要翻译：具有多个节点的系统中的互连结构中的事务请求以防止死锁的方式进行管理。确定从主设备到可能导致死锁的多个节点内的各种从设备的事务请求的一种或多种模式。当系统运行时，通过观察来自主设备的事务请求的顺序来检测其中一个模式的发生。检测到的模式中的事务请求被停止以允许较早的事务请求完成以防止死锁。

4. 发明申请

US20120226839A1 Method and System for Monitoring and Debugging Access to a Bus Slave Using One or More Throughput Counters 审中-公开
标题翻译：使用一个或多个吞吐量计数器监视和调试访问总线从站的方法和系统
公开(公告)号：US20120226839A1
公开(公告)日：2012-09-06
申请号：US13347736
申请日：2012-01-11
申请人： Charles Fuoco , Brian Cruickshank , Akila Subramaniam , Chunhua Hu , Samuel Paul Visalli
发明人： Charles Fuoco , Brian Cruickshank , Akila Subramaniam , Chunhua Hu , Samuel Paul Visalli
IPC分类号： G06F13/20
CPC分类号： G06F11/3636 , G06F11/348 , G06F11/349 , G06F2201/86
摘要： A bus monitoring and debugging system operating independently without impacting the normal operation of the CPU and without adding any overhead to the application being monitored. Bus transactions to a selected slave are monitored to determine possible conflicts when multiple masters may be addressing the slave. Users are alerted to timing problems as they occur, and bus statistics that are relevant to providing insight to system operation are automatically captured. Logging of relevant events may be enabled or disabled when a sliding time window expires, by a selected address range or alternatively by external trigger events.
摘要翻译：总线监控和调试系统独立运行，不会影响CPU的正常运行，并且不会对正在监视的应用程序造成任何开销。监视到所选从站的总线事务，以确定当多个主站可能寻址从站时可能的冲突。用户在发生定时问题时收到警报，并自动捕获与提供系统操作的洞察相关的总线统计信息。当滑动时间窗口到期时，可以通过选定的地址范围或外部触发事件来启用或禁用相关事件的记录。

5. 发明申请

US20120226837A1 Method and System of debugging Multicore Bus Transaction Problems 有权
标题翻译：调试多核总线事务处理问题的方法与系统
公开(公告)号：US20120226837A1
公开(公告)日：2012-09-06
申请号：US13329261
申请日：2011-12-17
申请人： Brian Cruickshank , David Quintin Bell , Samuel Paul Visalli , Chunhua Hu , Akila Subramaniam , Charles Fuoco
发明人： Brian Cruickshank , David Quintin Bell , Samuel Paul Visalli , Chunhua Hu , Akila Subramaniam , Charles Fuoco
IPC分类号： G06F13/00
CPC分类号： G06F11/3632 , G06F11/349 , G06F11/3636 , G06F11/3648
摘要： A bus monitoring and debugging system operating independently without impacting the normal operation of the CPU and without adding any overhead to the application being monitored. Users are alerted to timing problems as they occur, and bus statistics that are relevant to providing insight to system operation are automatically captured. Logging of relevant events may be enabled or disabled when a sliding time window expires, or alternatively by external trigger events.
摘要翻译：总线监控和调试系统独立运行，不会影响CPU的正常运行，并且不会对正在监视的应用程序造成任何开销。用户在发生定时问题时收到警报，并自动捕获与提供系统操作的洞察相关的总线统计信息。当滑动时间窗口到期时，或者通过外部触发事件，可以启用或禁用相关事件的记录。

6. 发明授权

US08706937B2 Method and system of debugging multicore bus transaction problems 有权
标题翻译：调试多核总线交易问题的方法和系统
公开(公告)号：US08706937B2
公开(公告)日：2014-04-22
申请号：US13329261
申请日：2011-12-17
申请人： Brian Cruickshank , David Quintin Bell , Samuel Paul Visalli , Chunhua Hu , Akila Subramaniam , Charles Fuoco
发明人： Brian Cruickshank , David Quintin Bell , Samuel Paul Visalli , Chunhua Hu , Akila Subramaniam , Charles Fuoco
IPC分类号： G06F13/00
CPC分类号： G06F11/3632 , G06F11/349 , G06F11/3636 , G06F11/3648
摘要： A bus monitoring and debugging system operating independently without impacting the normal operation of the CPU and without adding any overhead to the application being monitored. Users are alerted to timing problems as they occur, and bus statistics that are relevant to providing insight to system operation are automatically captured. Logging of relevant events may be enabled or disabled when a sliding time window expires, or alternatively by external trigger events.
摘要翻译：总线监控和调试系统独立运行，不会影响CPU的正常运行，并且不会对正在监视的应用程序造成任何开销。用户在发生定时问题时收到警报，并自动捕获与提供系统操作的洞察相关的总线统计信息。当滑动时间窗口到期时，或者通过外部触发事件，可以启用或禁用相关事件的记录。

7. 发明授权

US06594713B1 Hub interface unit and application unit interfaces for expanded direct memory access processor 有权
标题翻译： Hub接口单元和应用单元接口，用于扩展的直接存储器访问处理器
公开(公告)号：US06594713B1
公开(公告)日：2003-07-15
申请号：US09637492
申请日：2000-08-11
申请人： Charles Fuoco , David A. Comisky , Sanjive Agarwala , Raguram Damodaran
发明人： Charles Fuoco , David A. Comisky , Sanjive Agarwala , Raguram Damodaran
IPC分类号： G06F1300
CPC分类号： G06F13/28
摘要： An expanded direct memory access processor has ports which may be divided into two sections. The first is an application specific design referred to as the application unit, or application unit. Between the application unit and the expanded direct memory access processor hub is a second module, known as the hub interface unit hub interface unit which serves several functions. It provides buffering for read and write data, it prioritizes read and write commands from the source and destination pipelines such that the port sees a single interface with both access types consolidated and finally, it acts to decouple the port interface clock domain from the core processor clock domain through synchronization.
摘要翻译：扩展的直接存储器存取处理器具有可分为两部分的端口。第一种是被称为应用单元或应用单元的应用特定设计。在应用单元和扩展的直接存储器访问处理器集线器之间是第二模块，称为集线器接口单元集线器接口单元，其用于多个功能。它为读取和写入数据提供缓冲，它优先考虑来自源和目标管道的读取和写入命令，使得端口看到具有两个访问类型的单个接口合并，最后，它用于将端口接口时钟域与核心处理器时钟域通过同步。

8. 发明授权

US06985982B2 Active ports in a transfer controller with hub and ports 有权
公开(公告)号：US06985982B2
公开(公告)日：2006-01-10
申请号：US10003856
申请日：2001-10-24
申请人： Sanjive Agarwala , David A. Comisky , Charles Fuoco , Raguram Damodaran
发明人： Sanjive Agarwala , David A. Comisky , Charles Fuoco , Raguram Damodaran
IPC分类号： G06F13/00
CPC分类号： G06F13/385 , G06F13/28
摘要： In a transfer controller with hub and ports architecture one of the data ports is an active data port. This active data port can supply its own source information, destination information and data quantity in a data transfer request. This data transfer request is serviced in a manner similar to other data transfer requests. The active data port may specify itself as the data destination in an active read. Alternatively, the active data port may specify itself as the data source in an active data write.

9. 发明授权

US06694385B1 Configuration bus reconfigurable/reprogrammable interface for expanded direct memory access processor 有权
标题翻译：配置总线可重配置/可重新编程接口，用于扩展的直接存储器访问处理器
公开(公告)号：US06694385B1
公开(公告)日：2004-02-17
申请号：US09638512
申请日：2000-08-11
申请人： Charles Fuoco , David A. Comisky , Sanjive Agarwala
发明人： Charles Fuoco , David A. Comisky , Sanjive Agarwala
IPC分类号： G06F300
CPC分类号： G06F13/4256 , G06F13/28
摘要： The configuration bus interconnection protocol provides the configuration interfaces to the memory-mapped registers throughout the digital signal processor chip. The configuration bus is a parallel set of communications protocols, but for control of peripherals rather than for data transfer. While the expanded direct memory access processor is heavily optimized for maximizing data transfers, the configuration bus protocol is made to be as simple as possible for ease of implementation and portability.
摘要翻译：配置总线互连协议提供了整个数字信号处理器芯片中的存储器映射寄存器的配置接口。配置总线是一组并行的通信协议，但是用于控制外设而不是数据传输。虽然扩展的直接存储器访问处理器被大量优化以最大化数据传输，但是为了便于实现和便携性，使得配置总线协议尽可能简单。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式