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1. 发明授权

US07844435B2 Integrated circuit chip having on-chip signal integrity and noise verification using frequency dependent RLC extraction and modeling techniques 有权
标题翻译：具有片上信号完整性和使用频率相关RLC提取和建模技术的噪声验证的集成电路芯片
公开(公告)号：US07844435B2
公开(公告)日：2010-11-30
申请号：US11942270
申请日：2007-11-19
申请人： Michael A. Bowen , Alina Deutsch , Gerard V. Kopcsay , Byron L. Krauter , Barry J. Rubin , Howard H. Smith , David J. Widiger
发明人： Michael A. Bowen , Alina Deutsch , Gerard V. Kopcsay , Byron L. Krauter , Barry J. Rubin , Howard H. Smith , David J. Widiger
IPC分类号： G06F17/50 , G06G7/62 , G06G7/48
CPC分类号： G06F17/5036
摘要： An integrated circuit chip has new Frequency dependent RLC extraction and modeling providing on chip integrity and noise verification and the extraction and modeling employs: A) 2D scan line algorithm for the collection of adjacent signal and power conductor coordinates; B) In core pair-wise frequency Dependent RL extraction; C) In core equivalent circuit synthesis; D) caching and partitioning RL extraction techniques for run time efficiency; and E) Techniques for synthesizing stable circuits to represent frequency dependent RL circuits for non-mono tonic R12.
摘要翻译：集成电路芯片具有新的频率相关RLC提取和建模，提供片上完整性和噪声验证，提取和建模采用：A）用于收集相邻信号和电源导线坐标的2D扫描线算法; B）在核心配对频率从属RL提取中; C）在核心等效电路合成中; D）缓存和分区RL提取技术，用于运行时效率; 和E）用于合成稳定电路以表示用于非单音补音R12的频率相关RL电路的技术。

2. 发明授权

US07319946B2 Method for on-chip signal integrity and noise verification using frequency dependent RLC extraction and modeling techniques 有权
标题翻译：使用频率相关RLC提取和建模技术的片上信号完整性和噪声验证方法
公开(公告)号：US07319946B2
公开(公告)日：2008-01-15
申请号：US10274861
申请日：2002-10-21
申请人： Michael A. Bowen , Alina Deutsch , Gerard V. Kopcsay , Byron L. Krauter , Barry J. Rubin , Howard H. Smith , David J. Widiger
发明人： Michael A. Bowen , Alina Deutsch , Gerard V. Kopcsay , Byron L. Krauter , Barry J. Rubin , Howard H. Smith , David J. Widiger
IPC分类号： G06F17/50 , G06G7/62 , G06G7/48
CPC分类号： G06F17/5036
摘要： New Frequency dependent RLC extraction and modeling for on chip integrity and noise verification employs: A) 2D scan line algorithm for the collection of adjacent signal and power conductor coordinates; B) In core pair-wise frequency Dependent RL extraction; C) In core equivalent circuit synthesis; D) caching and partitioning RL extraction techniques for run time efficiency; and E) Techniques for synthesizing stable circuits to represent frequency dependent RL circuits for non-mono tonic R12.
摘要翻译：新的频率相关RLC提取和片上完整性和噪声验证的建模采用：A）用于收集相邻信号和电源导体坐标的2D扫描线算法; B）在核心配对频率从属RL提取中; C）在核心等效电路合成中; D）缓存和分区RL提取技术，用于运行时效率; 和E）用于合成稳定电路以表示用于非单音增益R 12的频率相关RL电路的技术。

3. 发明授权

US06963204B2 Method to include delta-I noise on chip using lossy transmission line representation for the power mesh 失效
标题翻译：使用功率网格的有损传输线表示在芯片上包括Δ-I噪声的方法
公开(公告)号：US06963204B2
公开(公告)日：2005-11-08
申请号：US10818578
申请日：2004-04-06
申请人： Alina Deutsch , Gerard V. Kopcsay , Byron L. Krauter , Barry J. Rubin , Howard H. Smith
发明人： Alina Deutsch , Gerard V. Kopcsay , Byron L. Krauter , Barry J. Rubin , Howard H. Smith
IPC分类号： G01R21/00 , G01R29/26 , G01R31/317 , G05B24/02 , G05F1/00 , G06F17/50 , H01L23/522 , H01L23/528 , H02J1/00 , H02J3/12 , H02J3/18
CPC分类号： G01R31/31721 , H01L23/5225 , H01L23/5286 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： The present invention relates to a method for analyzing the noise prediction within one or more electrical circuits, wherein the electrical circuits have a power mesh grid distribution system that feeds power levels to the electrical circuits that are connected by signal wires. After identifying a driver and receiver electrical circuit to be analyzed, a power block is generated that is associated with the driver and receiver electrical circuit by partitioning an area of a power mesh grid distribution system into a power block that can be modeled with lossy transmission line techniques. Next, signal wires situated between the driver and receiver electrical circuits are partitioned into signal blocks that can be modeled with lossy transmission line techniques. Lastly, the power blocks and signal blocks associated with the electrical circuits are analyzed in order to predict the noise performance within the electrical circuits.
摘要翻译：本发明涉及一种用于分析一个或多个电路内的噪声预测的方法，其中电路具有功率网格分布系统，其将功率电平馈送到通过信号线连接的电路。在识别要分析的驱动器和接收器电路之后，通过将功率网格分布系统的区域划分成可以用有损传输线建模的功率块来产生与驱动器和接收器电路相关联的功率块技术接下来，位于驱动器和接收器电路之间的信号线被分割成可以用有损传输线技术建模的信号块。最后，分析与电路相关联的功率块和信号块，以便预测电路内的噪声性能。

4. 发明授权

US07093206B2 Computer aided design method and apparatus for modeling and analyzing on-chip interconnect structures 失效
标题翻译：用于对片上互连结构进行建模和分析的计算机辅助设计方法和装置
公开(公告)号：US07093206B2
公开(公告)日：2006-08-15
申请号：US10690238
申请日：2003-10-21
申请人： Minakshisundaran B. Anand , Matthew S. Angyal , Alina Deutsch , Ibrahim M. Elfadel , Gerard V. Kopcsay , Barry J. Rubin , Howard H. Smith
发明人： Minakshisundaran B. Anand , Matthew S. Angyal , Alina Deutsch , Ibrahim M. Elfadel , Gerard V. Kopcsay , Barry J. Rubin , Howard H. Smith
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A computer aided design (CAD) system. A template generation engine generates templates from interconnect configuration files. A field solver generates high frequency passive element relationships from the templates. A circuit builder generates circuit description files from device technology models and from high frequency passive element relationships. Parameterized circuit description models may be generated for large range of sensitivity analyses. A simulator simulates circuit responses for transmission line models from the circuit description files. Interconnect configuration files may be generated by a geometry and material definition module that receives process description data from a designer.
摘要翻译：计算机辅助设计（CAD）系统。模板生成引擎从互连配置文件生成模板。场解算器从模板生成高频无源元件关系。电路构建器从器件技术模型和高频无源元件关系生成电路描述文件。可以为大范围的灵敏度分析生成参数化电路描述模型。模拟器模拟来自电路描述文件的传输线模型的电路响应。互连配置文件可以由接收来自设计者的过程描述数据的几何和材料定义模块生成。

5. 发明授权

US06418401B1 Efficient method for modeling three-dimensional interconnect structures for frequency-dependent crosstalk simulation 失效
标题翻译：针对频率相关串扰模拟的三维互连结构建模的高效方法
公开(公告)号：US06418401B1
公开(公告)日：2002-07-09
申请号：US09248667
申请日：1999-02-11
申请人： Allan H. Dansky , Alina Deutsch , Gerard V. Kopcsay , Phillip J. Restle , Howard H. Smith
发明人： Allan H. Dansky , Alina Deutsch , Gerard V. Kopcsay , Phillip J. Restle , Howard H. Smith
IPC分类号： G06F1750
CPC分类号： G06F17/5036
摘要： A method for reducing the computation time and improving the productivity in designing high-performance microprocessor chips that have no failures—due to crosstalk noise. The technique allows a very fast calculation of tables of frequency-dependent circuit parameters needed for accurate crosstalk prediction on lossy on-chip interconnections. These tables of parameters are the basis for CAD tools that perform crosstalk checking on >10K critical nets on typical microprocessor chips. A fast table generation allows for rapid incorporation of design or processing changes and transition to more advanced technologies.
摘要翻译：一种减少计算时间并提高设计高性能微处理器芯片的生产率的方法，这些微处理器芯片由于串扰噪声而无故障。该技术允许非常快速地计算在有损片上互连上精确串扰预测所需的频率相关电路参数表。这些参数表是在典型微处理器芯片上对> 10K关键网进行串扰检查的CAD工具的基础。快速表生成允许快速结合设计或处理更改并转换到更先进的技术。

6. 发明申请

US20100277197A1 SYSTEM AND METHOD IMPLEMENTING SHORT-PULSE PROPAGATION TECHNIQUE ON PRODUCTION-LEVEL BOARDS WITH INCREMENTAL ACCURACY AND PRODUCTIVITY LEVELS 有权
标题翻译：系统和方法实施生产级别的短脉冲传播技术，具有更高的精度和生产力水平
公开(公告)号：US20100277197A1
公开(公告)日：2010-11-04
申请号：US12432082
申请日：2009-04-29
申请人： Alina Deutsch , George A. Katopis , Gerard V. Kopcsay , Roger S. Krabbenhoft , Christopher W. Surovic
发明人： Alina Deutsch , George A. Katopis , Gerard V. Kopcsay , Roger S. Krabbenhoft , Christopher W. Surovic
IPC分类号： G01R31/02
CPC分类号： G01R31/2818 , G01R31/2822
摘要： A system and method for performing a test for characterizing high frequency operation of PCB boards. More particularly, a system and methodology is provided to implement a time-domain short pulse propagation (SPP) technique on the production line, on large, multi-layer, product-level PCB boards, for large volume testing, by people who are not familiar with advanced, delicate, measurement techniques, who need robust test facilities, and cannot afford the time or expense of other lab-type approaches.
摘要翻译：一种执行PCB板高频运行特性测试的系统和方法。更具体地，提供了一种系统和方法，用于在生产线上，在大型，多层，产品级PCB板上实施时域短脉冲传播（SPP）技术，用于大容量测试，由不是熟悉先进，精细，测量技术，需要强大的测试设施，无法承担其他实验室方法的时间或费用。

7. 发明授权

US5502392A Methods for the measurement of the frequency dependent complex propagation matrix, impedance matrix and admittance matrix of coupled transmission lines 失效
标题翻译：耦合传输线的频率相关复传播矩阵，阻抗矩阵和导纳矩阵的测量方法
公开(公告)号：US5502392A
公开(公告)日：1996-03-26
申请号：US151595
申请日：1993-11-12
申请人： Gnanalingam Arjavalingam , Alina Deutsch , Gerard V. Kopcsay , James K. Tam
发明人： Gnanalingam Arjavalingam , Alina Deutsch , Gerard V. Kopcsay , James K. Tam
IPC分类号： G01R27/06 , G01R27/32 , G01R31/28 , G01R27/04
CPC分类号： G01R27/32 , G01R27/06 , G01R31/2822
摘要： A method for completely characterizing coupled transmission lines by short-pulse propagation is described. The complex frequency-dependent propagation matrix, impedance matrix and admittance matrix for a set of n parallel transmission lines can be determined by comparing the properties of two sets of coupled transmission lines of different length. Each transmission line set has two conductors of unequal length and ground conductors to form a coupled transmission line system. Each transmission line set can have uncoupled ends. An input pulse is provided at at least one node of each transmission line set. The complex frequency dependent propagation matrix of each transmission line set is determined by a comparison of the output pulses at the remaining nodes of each transmission line set which involves ratioing to cancel out the effect of the pad-to-probe discontinuity and the uncoupled ends which make it unnecessary to do any embedding. For a transmission line wherein the dielectric loss is negligible, the complex frequency dependent characteristic admittance can be determined from the propagation matrix and the empirically determined capacitance matrix. For a transmission line wherein the resistive loss is negligible, the frequency dependent characteristic impedance matrix can be determined from the propagation matrix and the empirically determined inductance matrix. Specific structures are used with the measurement method to determine these coupled transmission line parameters. The method is particularly useful to determine these parameters for transmission lines in semiconductor chip packaging substrates.
摘要翻译：描述了通过短脉冲传播完全表征耦合传输线的方法。可以通过比较两组不同长度的耦合传输线的性质来确定一组n条并行传输线的复频率相关传播矩阵，阻抗矩阵和导纳矩阵。每个传输线组具有两个不等长度的导体和接地导体，以形成耦合传输线系统。每个传输线组可以具有非耦合端。在每个传输线组的至少一个节点处提供输入脉冲。每个传输线组的复频率相关传播矩阵通过比较每个传输线组的剩余节点上的输出脉冲来确定，该比较涉及比例以抵消焊盘与探针不连续性的影响和非耦合端无需做任何嵌入。对于其中介电损耗可忽略的传输线，可以根据传播矩阵和经验确定的电容矩阵来确定复频率相关特性导纳。对于其中电阻损耗可忽略的传输线，可以从传播矩阵和经验确定的电感矩阵确定频率相关特性阻抗矩阵。与测量方法一起使用具体结构来确定这些耦合的传输线参数。该方法对于确定半导体芯片封装衬底中的传输线的这些参数特别有用。

8. 发明授权

US08035409B2 System and method implementing short-pulse propagation technique on production-level boards with incremental accuracy and productivity levels 有权
标题翻译：系统和方法在生产级板上以增量精度和生产率水平实现短脉冲传播技术
公开(公告)号：US08035409B2
公开(公告)日：2011-10-11
申请号：US12432082
申请日：2009-04-29
申请人： Alina Deutsch , George A. Katopis , Gerard V. Kopcsay , Roger S. Krabbenhoft , Christopher W. Surovic
发明人： Alina Deutsch , George A. Katopis , Gerard V. Kopcsay , Roger S. Krabbenhoft , Christopher W. Surovic
IPC分类号： G01R31/304 , G01R31/306 , G01R31/309 , G06F11/30
CPC分类号： G01R31/2818 , G01R31/2822
摘要： A system and method for performing a test for characterizing high frequency operation of PCB boards. More particularly, a system and methodology is provided to implement a time-domain short pulse propagation (SPP) technique on the production line, on large, multi-layer, product-level PCB boards, for large volume testing, by people who are not familiar with advanced, delicate, measurement techniques, who need robust test facilities, and cannot afford the time or expense of other lab-type approaches.
摘要翻译：一种执行PCB板高频运行特性测试的系统和方法。更具体地，提供了一种系统和方法，用于在生产线上，在大型，多层，产品级PCB板上实施时域短脉冲传播（SPP）技术，用于大容量测试，由不是熟悉先进，精细，测量技术，需要强大的测试设施，无法承担其他实验室方法的时间或费用。

9. 发明申请

US20120266008A1 SYSTEM-WIDE POWER MANAGEMENT CONTROL VIA CLOCK DISTRIBUTION NETWORK 有权
标题翻译：通过时钟分配网络进行系统的电源管理控制
公开(公告)号：US20120266008A1
公开(公告)日：2012-10-18
申请号：US13085879
申请日：2011-04-13
申请人： Paul W. Coteus , Alan Gara , Thomas M. Gooding , Rudolf A. Haring , Gerard V. Kopcsay , Thomas A. Liebsch , Don D. Reed
发明人： Paul W. Coteus , Alan Gara , Thomas M. Gooding , Rudolf A. Haring , Gerard V. Kopcsay , Thomas A. Liebsch , Don D. Reed
IPC分类号： G06F1/12
CPC分类号： G06F1/329 , G06F1/10 , G06F1/12 , G06F1/206 , G06F1/3206 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/16 , Y02D10/172 , Y02D10/24
摘要： An apparatus, method and computer program product for automatically controlling power dissipation of a parallel computing system that includes a plurality of processors. A computing device issues a command to the parallel computing system. A clock pulse-width modulator encodes the command in a system clock signal to be distributed to the plurality of processors. The plurality of processors in the parallel computing system receive the system clock signal including the encoded command, and adjusts power dissipation according to the encoded command.
摘要翻译：一种用于自动控制包括多个处理器的并行计算系统的功耗的装置，方法和计算机程序产品。计算设备向并行计算系统发出命令。时钟脉冲宽度调制器对系统时钟信号中的命令进行编码，以分配给多个处理器。并行计算系统中的多个处理器接收包括编码命令的系统时钟信号，并根据编码命令调整功耗。

10. 发明授权

US07761687B2 Ultrascalable petaflop parallel supercomputer 失效
标题翻译：超平面petaflop平行超级计算机
公开(公告)号：US07761687B2
公开(公告)日：2010-07-20
申请号：US11768905
申请日：2007-06-26
申请人： Matthias A. Blumrich , Dong Chen , George Chiu , Thomas M. Cipolla , Paul W. Coteus , Alan G. Gara , Mark E. Giampapa , Shawn Hall , Rudolf A. Haring , Philip Heidelberger , Gerard V. Kopcsay , Martin Ohmacht , Valentina Salapura , Krishnan Sugavanam , Todd Takken
发明人： Matthias A. Blumrich , Dong Chen , George Chiu , Thomas M. Cipolla , Paul W. Coteus , Alan G. Gara , Mark E. Giampapa , Shawn Hall , Rudolf A. Haring , Philip Heidelberger , Gerard V. Kopcsay , Martin Ohmacht , Valentina Salapura , Krishnan Sugavanam , Todd Takken
IPC分类号： G06F15/173
CPC分类号： G06F15/17337
摘要： A massively parallel supercomputer of petaOPS-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC) having up to four processing elements. The ASIC nodes are interconnected by multiple independent networks that optimally maximize the throughput of packet communications between nodes with minimal latency. The multiple networks may include three high-speed networks for parallel algorithm message passing including a Torus, collective network, and a Global Asynchronous network that provides global barrier and notification functions. These multiple independent networks may be collaboratively or independently utilized according to the needs or phases of an algorithm for optimizing algorithm processing performance. The use of a DMA engine is provided to facilitate message passing among the nodes without the expenditure of processing resources at the node.
摘要翻译： petaOPS规模的大规模并行超级计算机包括基于片上系统技术的节点架构，其中每个处理节点包括具有多达四个处理元件的单个专用集成电路（ASIC）。 ASIC节点通过多个独立网络互连，以最小的延迟最大化节点之间的数据包通信的吞吐量。多个网络可以包括用于并行算法消息传递的三个高速网络，包括Torus，集合网络和提供全局障碍和通知功能的全球异步网络。这些多个独立网络可以根据用于优化算法处理性能的算法的需求或阶段来协同或独立地利用。提供DMA引擎的使用以促进节点之间的消息传递，而不需要节点处理资源。

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