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1. 发明授权

US07319946B2 Method for on-chip signal integrity and noise verification using frequency dependent RLC extraction and modeling techniques 有权
标题翻译：使用频率相关RLC提取和建模技术的片上信号完整性和噪声验证方法
公开(公告)号：US07319946B2
公开(公告)日：2008-01-15
申请号：US10274861
申请日：2002-10-21
申请人： Michael A. Bowen , Alina Deutsch , Gerard V. Kopcsay , Byron L. Krauter , Barry J. Rubin , Howard H. Smith , David J. Widiger
发明人： Michael A. Bowen , Alina Deutsch , Gerard V. Kopcsay , Byron L. Krauter , Barry J. Rubin , Howard H. Smith , David J. Widiger
IPC分类号： G06F17/50 , G06G7/62 , G06G7/48
CPC分类号： G06F17/5036
摘要： New Frequency dependent RLC extraction and modeling for on chip integrity and noise verification employs: A) 2D scan line algorithm for the collection of adjacent signal and power conductor coordinates; B) In core pair-wise frequency Dependent RL extraction; C) In core equivalent circuit synthesis; D) caching and partitioning RL extraction techniques for run time efficiency; and E) Techniques for synthesizing stable circuits to represent frequency dependent RL circuits for non-mono tonic R12.
摘要翻译：新的频率相关RLC提取和片上完整性和噪声验证的建模采用：A）用于收集相邻信号和电源导体坐标的2D扫描线算法; B）在核心配对频率从属RL提取中; C）在核心等效电路合成中; D）缓存和分区RL提取技术，用于运行时效率; 和E）用于合成稳定电路以表示用于非单音增益R 12的频率相关RL电路的技术。

2. 发明授权

US07844435B2 Integrated circuit chip having on-chip signal integrity and noise verification using frequency dependent RLC extraction and modeling techniques 有权
标题翻译：具有片上信号完整性和使用频率相关RLC提取和建模技术的噪声验证的集成电路芯片
公开(公告)号：US07844435B2
公开(公告)日：2010-11-30
申请号：US11942270
申请日：2007-11-19
申请人： Michael A. Bowen , Alina Deutsch , Gerard V. Kopcsay , Byron L. Krauter , Barry J. Rubin , Howard H. Smith , David J. Widiger
发明人： Michael A. Bowen , Alina Deutsch , Gerard V. Kopcsay , Byron L. Krauter , Barry J. Rubin , Howard H. Smith , David J. Widiger
IPC分类号： G06F17/50 , G06G7/62 , G06G7/48
CPC分类号： G06F17/5036
摘要： An integrated circuit chip has new Frequency dependent RLC extraction and modeling providing on chip integrity and noise verification and the extraction and modeling employs: A) 2D scan line algorithm for the collection of adjacent signal and power conductor coordinates; B) In core pair-wise frequency Dependent RL extraction; C) In core equivalent circuit synthesis; D) caching and partitioning RL extraction techniques for run time efficiency; and E) Techniques for synthesizing stable circuits to represent frequency dependent RL circuits for non-mono tonic R12.
摘要翻译：集成电路芯片具有新的频率相关RLC提取和建模，提供片上完整性和噪声验证，提取和建模采用：A）用于收集相邻信号和电源导线坐标的2D扫描线算法; B）在核心配对频率从属RL提取中; C）在核心等效电路合成中; D）缓存和分区RL提取技术，用于运行时效率; 和E）用于合成稳定电路以表示用于非单音补音R12的频率相关RL电路的技术。

3. 发明授权

US06963204B2 Method to include delta-I noise on chip using lossy transmission line representation for the power mesh 失效
标题翻译：使用功率网格的有损传输线表示在芯片上包括Δ-I噪声的方法
公开(公告)号：US06963204B2
公开(公告)日：2005-11-08
申请号：US10818578
申请日：2004-04-06
申请人： Alina Deutsch , Gerard V. Kopcsay , Byron L. Krauter , Barry J. Rubin , Howard H. Smith
发明人： Alina Deutsch , Gerard V. Kopcsay , Byron L. Krauter , Barry J. Rubin , Howard H. Smith
IPC分类号： G01R21/00 , G01R29/26 , G01R31/317 , G05B24/02 , G05F1/00 , G06F17/50 , H01L23/522 , H01L23/528 , H02J1/00 , H02J3/12 , H02J3/18
CPC分类号： G01R31/31721 , H01L23/5225 , H01L23/5286 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： The present invention relates to a method for analyzing the noise prediction within one or more electrical circuits, wherein the electrical circuits have a power mesh grid distribution system that feeds power levels to the electrical circuits that are connected by signal wires. After identifying a driver and receiver electrical circuit to be analyzed, a power block is generated that is associated with the driver and receiver electrical circuit by partitioning an area of a power mesh grid distribution system into a power block that can be modeled with lossy transmission line techniques. Next, signal wires situated between the driver and receiver electrical circuits are partitioned into signal blocks that can be modeled with lossy transmission line techniques. Lastly, the power blocks and signal blocks associated with the electrical circuits are analyzed in order to predict the noise performance within the electrical circuits.
摘要翻译：本发明涉及一种用于分析一个或多个电路内的噪声预测的方法，其中电路具有功率网格分布系统，其将功率电平馈送到通过信号线连接的电路。在识别要分析的驱动器和接收器电路之后，通过将功率网格分布系统的区域划分成可以用有损传输线建模的功率块来产生与驱动器和接收器电路相关联的功率块技术接下来，位于驱动器和接收器电路之间的信号线被分割成可以用有损传输线技术建模的信号块。最后，分析与电路相关联的功率块和信号块，以便预测电路内的噪声性能。

4. 发明授权

US07093206B2 Computer aided design method and apparatus for modeling and analyzing on-chip interconnect structures 失效
标题翻译：用于对片上互连结构进行建模和分析的计算机辅助设计方法和装置
公开(公告)号：US07093206B2
公开(公告)日：2006-08-15
申请号：US10690238
申请日：2003-10-21
申请人： Minakshisundaran B. Anand , Matthew S. Angyal , Alina Deutsch , Ibrahim M. Elfadel , Gerard V. Kopcsay , Barry J. Rubin , Howard H. Smith
发明人： Minakshisundaran B. Anand , Matthew S. Angyal , Alina Deutsch , Ibrahim M. Elfadel , Gerard V. Kopcsay , Barry J. Rubin , Howard H. Smith
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A computer aided design (CAD) system. A template generation engine generates templates from interconnect configuration files. A field solver generates high frequency passive element relationships from the templates. A circuit builder generates circuit description files from device technology models and from high frequency passive element relationships. Parameterized circuit description models may be generated for large range of sensitivity analyses. A simulator simulates circuit responses for transmission line models from the circuit description files. Interconnect configuration files may be generated by a geometry and material definition module that receives process description data from a designer.
摘要翻译：计算机辅助设计（CAD）系统。模板生成引擎从互连配置文件生成模板。场解算器从模板生成高频无源元件关系。电路构建器从器件技术模型和高频无源元件关系生成电路描述文件。可以为大范围的灵敏度分析生成参数化电路描述模型。模拟器模拟来自电路描述文件的传输线模型的电路响应。互连配置文件可以由接收来自设计者的过程描述数据的几何和材料定义模块生成。

5. 发明授权

US06418401B1 Efficient method for modeling three-dimensional interconnect structures for frequency-dependent crosstalk simulation 失效
标题翻译：针对频率相关串扰模拟的三维互连结构建模的高效方法
公开(公告)号：US06418401B1
公开(公告)日：2002-07-09
申请号：US09248667
申请日：1999-02-11
申请人： Allan H. Dansky , Alina Deutsch , Gerard V. Kopcsay , Phillip J. Restle , Howard H. Smith
发明人： Allan H. Dansky , Alina Deutsch , Gerard V. Kopcsay , Phillip J. Restle , Howard H. Smith
IPC分类号： G06F1750
CPC分类号： G06F17/5036
摘要： A method for reducing the computation time and improving the productivity in designing high-performance microprocessor chips that have no failures—due to crosstalk noise. The technique allows a very fast calculation of tables of frequency-dependent circuit parameters needed for accurate crosstalk prediction on lossy on-chip interconnections. These tables of parameters are the basis for CAD tools that perform crosstalk checking on >10K critical nets on typical microprocessor chips. A fast table generation allows for rapid incorporation of design or processing changes and transition to more advanced technologies.
摘要翻译：一种减少计算时间并提高设计高性能微处理器芯片的生产率的方法，这些微处理器芯片由于串扰噪声而无故障。该技术允许非常快速地计算在有损片上互连上精确串扰预测所需的频率相关电路参数表。这些参数表是在典型微处理器芯片上对> 10K关键网进行串扰检查的CAD工具的基础。快速表生成允许快速结合设计或处理更改并转换到更先进的技术。

6. 发明授权

US06546529B1 Method for performing coupling analysis 失效
标题翻译：执行耦合分析的方法
公开(公告)号：US06546529B1
公开(公告)日：2003-04-08
申请号：US09677362
申请日：2000-10-02
申请人： Allan H. Dansky , Michael A. Bowen , Peter J. Camporese , Alina Deutsch , Howard H. Smith
发明人： Allan H. Dansky , Michael A. Bowen , Peter J. Camporese , Alina Deutsch , Howard H. Smith
IPC分类号： G06F945
CPC分类号： G06F17/5036
摘要： Deterministic evaluation of coupling noise voltage is a function of many physical and electrical parameters such as wiring level, widths, spacing, net topologies, drv impedance and slew rates. This evaluation requires electrical modeling and subsequent circuit simulation to assess the sensitivities of these parameters. These sensitivities can be categorized as coupling guidelines that can be directly linked through extracted physical design data. This invention discloses the development and implementation of a technique for using a coupling guideline table early in the design of an integrated circuit when all the parameters generally required for coupling noise voltage calculations are not available. The steps include: creating a flat wire routing map of the integrated circuit, identifying the coupled wire segments on the integrated circuit, tracking wire interconnection patterns on the integrated circuit, deriving electrical parameters for the coupled wire segments, and generating a coupling guideline table with parameters for a plurality of electrical parameters. The parameters in the coupling guideline table are applied to the derived electrical parameters and a report is generated that lists the derived electrical parameters that fail to comply with the parameters in the coupling guideline table.
摘要翻译：耦合噪声电压的确定性评估是许多物理和电气参数的函数，如布线级别，宽度，间距，网络拓扑，drv阻抗和转换速率。该评估需要电气建模和后续电路仿真来评估这些参数的灵敏度。这些敏感性可以归类为可以通过提取的物理设计数据直接相关联的耦合准则。本发明公开了当耦合噪声电压计算通常需要的所有参数不可用时，在集成电路设计早期使用耦合指南表的技术的开发和实现。步骤包括：创建集成电路的扁平布线图，识别集成电路上的耦合线段，跟踪集成电路上的导线互连图案，导出耦合的线段的电参数，以及生成具有用于多个电参数的参数。耦合准则表中的参数应用于导出的电气参数，并生成报告，列出导出的电气参数不符合耦合指南表中的参数。

7. 发明授权

US06333680B1 Method and system for characterizing coupling capacitance between integrated circuit interconnects 失效
标题翻译：表征集成电路互连之间的耦合电容的方法和系统
公开(公告)号：US06333680B1
公开(公告)日：2001-12-25
申请号：US09677348
申请日：2000-10-02
申请人： Howard H. Smith , Alina Deutsch , Ching-Lung L. Tong , Rolf H. Nijhuis
发明人： Howard H. Smith , Alina Deutsch , Ching-Lung L. Tong , Rolf H. Nijhuis
IPC分类号： H03B524
CPC分类号： G01R27/2605 , G01R31/04
摘要： An exemplary embodiment of the invention is a method of characterizing capacitances of a plurality of integrated circuit interconnects. The method includes coupling a first oscillator to a first integrated circuit interconnect and coupling a second oscillator to a second integrated circuit interconnect. The first oscillator is activated to characterize the sum of (i) coupling capacitance between the first integrated-circuit interconnect and the second integrated-circuit interconnect and (ii) ground capacitance between the first integrated-circuit interconnect and a ground. In addition, both of the first oscillator and the second oscillator are activated to characterize the ground capacitance between the first integrated-circuit interconnect and the ground.
摘要翻译：本发明的示例性实施例是表征多个集成电路互连的电容的方法。该方法包括将第一振荡器耦合到第一集成电路互连并将第二振荡器耦合到第二集成电路互连。激活第一振荡器以表征（i）第一集成电路互连和第二集成电路互连之间的耦合电容和（ii）第一集成电路互连和地之间的接地电容之和的和。此外，第一振荡器和第二振荡器都被激活以表征第一集成电路互连和地之间的接地电容。

8. 发明授权

US06323050B1 Method for evaluating decoupling capacitor placement for VLSI chips 失效
标题翻译：评估VLSI芯片去耦电容放置的方法
公开(公告)号：US06323050B1
公开(公告)日：2001-11-27
申请号：US09677285
申请日：2000-10-02
申请人： Allan H. Dansky , Wiren D. Becker , Howard H. Smith , Peter J. Camporese , Kwok Fai Eng , Dale E. Hoffman , Bhupindra Singh
发明人： Allan H. Dansky , Wiren D. Becker , Howard H. Smith , Peter J. Camporese , Kwok Fai Eng , Dale E. Hoffman , Bhupindra Singh
IPC分类号： H01L2166
CPC分类号： G06F17/5072 , G06F17/5036
摘要： A method of evaluating decoupling capacitor placement for Very Large Scale Integrated Chips (VLSI) is disclosed. Included in the method is an analysis of the usage for each decoupling capacitor, the distance from the devices, and the locations of the devices and decoupling capacitors. Also addressed are the orientations and size of the components.
摘要翻译：公开了一种评估超大规模集成芯片（VLSI）的去耦电容放置的方法。该方法中包括对每个去耦电容器的使用情况，与器件的距离以及器件和去耦电容器的位置的分析。还解决了组件的方向和尺寸。

9. 发明授权

US4054073A Jeweler's tool 失效
标题翻译：珠宝商{3 s工具
公开(公告)号：US4054073A
公开(公告)日：1977-10-18
申请号：US743564
申请日：1976-11-22
申请人： Howard H. Smith , Glenn E. Christensen
发明人： Howard H. Smith , Glenn E. Christensen
IPC分类号： A44C9/00 , B26D1/30 , B26D3/00
CPC分类号： A44C9/0084 , B26D1/30 , Y10S83/917 , Y10S83/935 , Y10T83/0596 , Y10T83/8801 , Y10T83/8809
摘要： A cutting tool is provided with a plurality of circular cutting blades of varying predetermined thicknesses to shear sections from rings made of precious metals. Each blade is formed with a notched perimeter to provide a pair of blade cutting edges. The blades are mounted on a spindle for rotation therewith, while the spindle is rotatably mounted in a plurality of cutting blocks which are affixed to a base in an alternating arrangement with the aforesaid blades. The cutting blocks define cutting edges so that rotation of the spindle causes the blade cutting edges formed by the notched perimeter to come into a simultaneous shearing relation with the cutting edges of the two adjacent cutting blocks. Further rotation of the spindle will shear out a section of a ring interposed in the notched perimeter of the blade. The tool is further provided with removable trays to catch sheared pieces of precious metals. Rotation of the spindle is accomplished through a conventional crank handle.
摘要翻译：切割工具设置有多个具有预定厚度的圆形切割刀片，其具有由贵金属制成的环的剪切部分。每个叶片形成有切口周边以提供一对刀片切割刃。刀片安装在主轴上以与其一起旋转，而主轴可旋转地安装在多个切割块中，该多个切割块以与上述刀片交替布置的方式固定到基座。切割块限定切割边缘，使得主轴的旋转导致由切口周边形成的叶片切割边缘与两个相邻切割块的切割边缘同时剪切关系。主轴的进一步旋转将剪切插入在叶片的切口周边中的环的一部分。该工具还提供有可拆卸的托盘，以捕获剪切的贵金属件。主轴的旋转通过传统的曲柄手柄实现。

10. 发明授权

US07269806B2 Decoupling capacitance analysis method 失效
标题翻译：去耦电容分析方法
公开(公告)号：US07269806B2
公开(公告)日：2007-09-11
申请号：US11408228
申请日：2006-04-20
申请人： Christopher J. Berry , Howard H. Smith , Richard P. Underwood , Alan P. Wagstaff
发明人： Christopher J. Berry , Howard H. Smith , Richard P. Underwood , Alan P. Wagstaff
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： This method for decoupling capacitance analysis improves upon existing techniques to attempt to give a more accurate representation of the power supply fluctuations on a chip while keeping runtime comparable. This method employs the following techniques; a) a method for descending through hierarchy and dividing the design into a variable sized grid; b) an algorithm to determine which grid locations of a design don't have enough decoupling capacitors for all of the devices in that grid location; c) an algorithm to determine which grid locations are subject to harmful neighboring effects; and d) a method to display the results of the calculations in a graphical manor to allow easy identification of problem areas.
摘要翻译：用于去耦电容分析的这种方法改进了现有技术，以试图给出对芯片上的电源波动的更准确的表示，同时保持运行时可比性。该方法采用以下技术; a）通过层级降级并将设计划分为可变尺寸网格的方法; b）确定设计的哪些网格位置对于该网格位置中的所有设备没有足够的去耦电容器的算法; c）确定哪些网格位置受到有害的相邻影响的算法; 以及d）以图形方式显示计算结果的方法，以便容易地识别问题区域。

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