专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06988173B2 Bus protocol for a switchless distributed shared memory computer system 失效
标题翻译：总线协议用于无交换分布式共享内存计算机系统
公开(公告)号：US06988173B2
公开(公告)日：2006-01-17
申请号：US10435878
申请日：2003-05-12
申请人： Michael A. Blake , Steven M. German , Pak-kin Mak , Adrian E. Seigler , Gary A. Van Huben
发明人： Michael A. Blake , Steven M. German , Pak-kin Mak , Adrian E. Seigler , Gary A. Van Huben
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/0813
摘要： A bus protocol is disclosed for a symmetric multiprocessing computer system consisting of a plurality of nodes, each of which contains a multitude of processors, I/O devices, main memory and a system controller comprising an integrated switch with a top level cache. The nodes are interconnected by a dual concentric ring topology. The bus protocol is used to exchange snoop requests and addresses, data, coherency information and operational status between nodes in a manner that allows partial coherency results to be passed in parallel with a snoop request and address as an operation is forwarded along each ring. Each node combines it's own coherency results with the partial coherency results it received prior to forwarding the snoop request, address and updated partial coherency results to the next node on the ring. The protocol allows each node in the system to see the final coherency results without requiring the requesting node to broadcast these results to all the other nodes in the system. The bus protocol also allows data to be returned on one of the two rings, with the ring selection determined by the relative placement of the source and destination nodes on each ring, in order to control latency and data bus utilization.
摘要翻译：公开了一种用于由多个节点组成的对称多处理计算机系统的总线协议，每个节点包含多个处理器，I / O设备，主存储器和包括具有顶级高速缓存的集成交换机的系统控制器。节点通过双同心环拓扑互连。总线协议用于以一种允许部分一致性结果与窥探请求和地址并行传送的方式来交换窥探请求和地址，数据，相关性信息和节点之间的操作状态，因为操作沿着每个环转发。每个节点将其自身的一致性结果与在将窥探请求转发之前接收的部分一致性结果相结合，将地址和更新的部分一致性结果合并到环上的下一个节点。该协议允许系统中的每个节点查看最终的一致性结果，而不需要请求节点将这些结果广播到系统中的所有其他节点。总线协议还允许在两个振铃中的一个上返回数据，其中环选择由每个振铃上的源节点和目的节点的相对位置确定，以便控制等待时间和数据总线的利用。

2. 发明授权

US06738872B2 Clustered computer system with deadlock avoidance 有权
标题翻译：具有死锁避免的集群计算机系统
公开(公告)号：US06738872B2
公开(公告)日：2004-05-18
申请号：US09746686
申请日：2000-12-22
申请人： Gary A. Van Huben , Michael A. Blake , Pak-Kin Mak , Adrian Eric Seigler
发明人： Gary A. Van Huben , Michael A. Blake , Pak-Kin Mak , Adrian Eric Seigler
IPC分类号： G06F1200
CPC分类号： G06F9/524
摘要： A remote resource management system for managing resources in a symmetrical multiprocessing environment having a plurality of clusters of symmetric multiprocessors each of which provides interfaces between cluster nodes of the symmetric multiprocessor system with a local interface and an interface controller. One or more remote storage controllers each has a local interface controller and a local-to-remote data bus. A remote fetch controller is responsible for processing data accesses across the clusters and a remote store controller is responsible for processing data accesses across the clusters. These controllers work in conjunction to provide a deadlock avoidance system for preventing hangs.
摘要翻译：一种用于在具有多个对称多处理器群集的对称多处理环境中管理资源的远程资源管理系统，每个处理器集群在对称多处理器系统的群集节点与本地接口和接口控制器之间提供接口。一个或多个远程存储控制器各自具有本地接口控制器和本地到远程的数据总线。远程提取控制器负责处理跨集群的数据访问，远程存储控制器负责处理跨集群的数据访问。这些控制器协同工作，提供一个防止挂起的死锁避免系统。

3. 发明授权

US06738870B2 High speed remote storage controller 失效
标题翻译：高速远程存储控制器
公开(公告)号：US06738870B2
公开(公告)日：2004-05-18
申请号：US09745593
申请日：2000-12-22
申请人： Gary A. Van Huben , Michael A. Blake , Pak-Kin Mak
发明人： Gary A. Van Huben , Michael A. Blake , Pak-Kin Mak
IPC分类号： G06F1200
CPC分类号： G06F15/17381
摘要： A high speed remote storage controller system for a computer system has cluster nodes of symmetric multiprocessors. A plurality of clusters of symmetric multiprocessors each of has a plurality of processors, a shared cache memory, a plurality of I/O adapters and a main memory accessible from the cluster. Each cluster has an interface for passing data between cluster nodes of the symmetric multiprocessor system. Each cluster has a local interface and interface controller. The system provides one or more remote storage controllers each having a local interface controller and a local-to-remote data bus. A remote resource manager manages the interface between clusters of symmetric multiprocessors. The remote store controller is responsible for processing data accesses across a plurality of clusters and processes data storage operations involving shared memory. A macro is provided for processing a plurality of simultaneous data storage operations either synchronously through interaction with a sequential multistage centralized pipeline to serialize requests and provide address interlocking services or asynchronously whereby main memory accesses bypass a centralized system pipeline. These accesses can occur in parallel with other remote storage operations.
摘要翻译：用于计算机系统的高速远程存储控制器系统具有对称多处理器的集群节点。多个对称多处理器群集具有多个处理器，共享高速缓存存储器，多个I / O适配器和可从群集访问的主存储器。每个集群都有一个用于在对称多处理器系统的集群节点之间传递数据的接口。每个集群都有一个本地接口和接口控制器。该系统提供一个或多个远程存储控制器，每个具有本地接口控制器和本地到远程的数据总线。远程资源管理器管理对称多处理器群集之间的接口。远程存储控制器负责处理跨多个集群的数据访问，并处理涉及共享存储器的数据存储操作。提供宏，用于通过与顺序多级集中式流水线的交互同步地处理多个同时的数据存储操作，以串行化请求并提供地址互锁服务或异步地使主存储器访问绕过集中式系统流水线。这些访问可能与其他远程存储操作并行发生。

4. 发明授权

US06738871B2 Method for deadlock avoidance in a cluster environment 有权
标题翻译：集群环境中的死锁避免方法
公开(公告)号：US06738871B2
公开(公告)日：2004-05-18
申请号：US09745830
申请日：2000-12-22
申请人： Gary A. Van Huben , Michael A. Blake , Pak-Kin Mak , Adrian Eric Seigler
发明人： Gary A. Van Huben , Michael A. Blake , Pak-Kin Mak , Adrian Eric Seigler
IPC分类号： G06F1200
CPC分类号： G06F15/17381
摘要： A remote resource management system for managing resources in a symmetrical multiprocessing environment having a plurality of clusters of symmetric multiprocessors each of which provides interfaces between cluster nodes of the symmetric multiprocessor system with a local interface and an interface controller. One or more remote storage controllers each has a local interface controller and a local-to-remote data bus. A remote fetch controller is responsible for processing data accesses in accordance with the methods described.
摘要翻译：一种用于在具有多个对称多处理器群集的对称多处理环境中管理资源的远程资源管理系统，每个处理器集群在对称多处理器系统的群集节点与本地接口和接口控制器之间提供接口。一个或多个远程存储控制器各自具有本地接口控制器和本地到远程的数据总线。远程提取控制器负责根据所述方法处理数据访问。

5. 发明授权

US07971166B2 Method, system, and program product for automated verification of gating logic using formal verification 有权
标题翻译：使用形式验证自动验证门控逻辑的方法，系统和程序产品
公开(公告)号：US07971166B2
公开(公告)日：2011-06-28
申请号：US12139483
申请日：2008-06-15
申请人： Adrian E. Seigler , Gary A. Van Huben
发明人： Adrian E. Seigler , Gary A. Van Huben
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： Gating rules for a device design containing microelectronic devices are tested using formal verification. Testbench design code is generated for a device design from a design source containing hardware design language code. A formal verification process on the testbench device code determines whether the devices within the device design will be stable or unstable under a gating condition. If the test shows a design is unstable under the gating condition; it is indicated that a hardware design fix for the device design is required. If not, the test ends.
摘要翻译：使用形式验证测试包含微电子器件的器件设计的门控规则。测试台设计代码是从包含硬件设计语言代码的设计源中为设备设计生成的。测试台设备代码上的正式验证过程确定设备设计中的设备是否在门控条件下稳定或不稳定。如果测试显示设计在门控条件下不稳定; 表明需要对设备设计进行硬件设计修复。如果没有，测试结束。

6. 发明授权

US07448008B2 Method, system, and program product for automated verification of gating logic using formal verification 有权
标题翻译：使用形式验证自动验证门控逻辑的方法，系统和程序产品
公开(公告)号：US07448008B2
公开(公告)日：2008-11-04
申请号：US11468078
申请日：2006-08-29
申请人： Adrian E. Seigler , Gary A. Van Huben
发明人： Adrian E. Seigler , Gary A. Van Huben
IPC分类号： G06F17/50 , G06F19/00
CPC分类号： G06F17/504
摘要： Automated verification methodology parsing scripts auto generate testbench hardware design language, such as VHDL or Verilog, from the design source VHDL or Verilog. A formal verification model is then built comprising the testbench VHDL and the design under test. The resulting design verification tool then provides proofs and counterexamples for all of the rules, e.g., auto-generated rules, in the testbench.
摘要翻译：自动验证方法解析脚本从设计源VHDL或Verilog自动生成测试平台硬件设计语言，如VHDL或Verilog。然后构建一个正式的验证模型，包括测试台VHDL和被测设计。因此，所产生的设计验证工具将为测试平台中的所有规则（例如自动生成的规则）提供证明和反例。

7. 发明申请

US20090183129A1 Method, System, and Program Product for Automated Verification of Gating Logic Using Formal Verification 有权
标题翻译：使用正式验证自动验证门控逻辑的方法，系统和程序产品
公开(公告)号：US20090183129A1
公开(公告)日：2009-07-16
申请号：US12139483
申请日：2008-06-15
申请人： Adrian E. Seigler , Gary A. Van Huben
发明人： Adrian E. Seigler , Gary A. Van Huben
IPC分类号： G06F17/50 , G06F19/00
CPC分类号： G06F17/504
摘要： Gating rules for a device design containing microelectronic devices are tested using formal verification. Testbench design code is generated for a device design from a design source containing hardware design language code. A formal verification process on the testbench device code determines whether the devices within the device design will be stable or unstable under a gating condition. If the test shows a design is unstable under the gating condition; it is indicated that a hardware design fix for the device design is required. If not, the test ends.
摘要翻译：使用形式验证测试包含微电子器件的器件设计的门控规则。测试台设计代码是从包含硬件设计语言代码的设计源中为设备设计生成的。测试台设备代码上的正式验证过程确定设备设计中的设备是否在门控条件下稳定或不稳定。如果测试显示设计在门控条件下不稳定; 表明需要对设备设计进行硬件设计修复。如果没有，测试结束。

8. 发明申请

US20080059925A1 Method, System, and Program Product for Automated Verification of Gating Logic Using Formal Verification 有权
标题翻译：使用正式验证自动验证门控逻辑的方法，系统和程序产品
公开(公告)号：US20080059925A1
公开(公告)日：2008-03-06
申请号：US11468078
申请日：2006-08-29
申请人： Adrian E. Seigler , Gary A. Van Huben
发明人： Adrian E. Seigler , Gary A. Van Huben
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： As described herein the automated verification methodology parsing scripts auto generate test bench hardware design langaue, such as VHDL or Verilog, from the design source VHDL or Verilog. A formal verification model is then built comprising the testbench VHDL and the design under test. The resulting design verification tool then provides proofs and counterexamples for all of the rules, e.g., auto-generated rules, in the test bench.
摘要翻译：如本文所述，解析脚本的自动验证方法从设计源VHDL或Verilog自动生成测试台硬件设计语言，如VHDL或Verilog。然后构建一个正式的验证模型，包括测试台VHDL和被测设计。然后，所得到的设计验证工具在测试台中提供所有规则（例如，自动生成的规则）的证明和反例。

9. 发明授权

US08874808B2 Hierarchical buffer system enabling precise data delivery through an asynchronous boundary 有权
标题翻译：分层缓冲系统，能够通过异步边界进行精确的数据传送
公开(公告)号：US08874808B2
公开(公告)日：2014-10-28
申请号：US13352913
申请日：2012-01-18
申请人： Steven J. Hnatko , Gary A. Van Huben
发明人： Steven J. Hnatko , Gary A. Van Huben
IPC分类号： G06F3/00 , G06F5/00 , G06F15/16 , G11C7/10 , G06F13/28
CPC分类号： G11C7/1075 , G06F13/28 , G11C7/106 , G11C7/1087
摘要： The present invention provides a system and method for controlling data entries in a hierarchical buffer system. The system includes an integrated circuit device with a memory core, a high speed upstream data bus, and a plurality of 1st tier buffers that receive data from the memory. The system further includes a 2nd tier transfer buffer spanning a plurality of asynchronous timing domains that delivers the data onto the upstream data bus to minimize gaps in a data transfer. The method includes managing the buffers to allow data to flow from a plurality of 1st tier buffers through a 2nd tier transfer buffer, and delivering the data onto a high speed data bus with pre-determined timing in a manner which minimizes latency to the extent that the returning read data beats are always transmitted contiguously with no intervening gaps.
摘要翻译：本发明提供一种用于控制分级缓冲系统中的数据条目的系统和方法。该系统包括具有存储器核心的集成电路装置，高速上行数据总线以及从存储器接收数据的多个第一层缓冲器。该系统还包括跨越多个异步定时域的第二层传输缓冲器，其将数据传送到上游数据总线以最小化数据传输中的间隙。该方法包括管理缓冲器以允许数据从多个第一层缓冲器通过第二层传输缓冲器流动，并以预定定时以最小化等待时间的方式将数据传送到高速数据总线上，返回的读数据跳动总是连续发送，没有中间间隙。

10. 发明申请

US20090030666A1 Software Entity for the Creation of a Hybrid Cycle Simulation Model 有权
标题翻译：创建混合循环模拟模型的软件实体
公开(公告)号：US20090030666A1
公开(公告)日：2009-01-29
申请号：US12248951
申请日：2008-10-10
申请人： Gary A. Van Huben , Edward J. Kamindki, JR. , Elspeth Anne Iluston
发明人： Gary A. Van Huben , Edward J. Kamindki, JR. , Elspeth Anne Iluston
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： Disclosed is a software entity for constructing a Hybrid Cycle Simulation model comprising Compiled Data Units (CDUs) for use in design verification. The simulation model may contain a plurality of 1-cycle CDUs, optimized for simulation throughput, and 2-cycle CDUs, optimized for simulation accuracy, or a mixture thereof. Utilizing a netlist tool extracting hierarchical design source components for use, the construction checks that all inputs and outputs of any hierarchical design source components bind, and employs Object Traversal Directives for incorporating the selected CDUs into the simulation model. A data management method is used for tracking the validity of the components in the model. Additionally, a software entity (FACDDR) permits high bandwidth simulation of design components normally requiring cycle accurate simulation. FACDDR provides linkages for standard logic elements for abstracting one or more design interface components out of a cycle simulation environment and design interface emulation of an interface which interacts with a cycle simulation model through an API to extract present value of driving side signals of an interface and to set the cycle simulation model on the receiving side.
摘要翻译：公开了一种用于构建混合循环模拟模型的软件实体，该模型包括用于设计验证的编译数据单元（CDU）。模拟模型可以包含针对模拟吞吐量优化的多个1周期CDU，以及针对模拟精度优化的2周期CDU或其混合。利用提取分层设计源组件的网表工具，该构造检查任何分层设计源组件的所有输入和输出是否绑定，并使用对象遍历指令将所选择的CDU合并到仿真模型中。数据管理方法用于跟踪模型中组件的有效性。另外，一个软件实体（FACDDR）允许设计组件的高带宽仿真，通常需要循环精确的模拟。 FACDDR为标准逻辑元件提供链接，用于从循环模拟环境中抽取一个或多个设计接口组件，并通过API与循环模拟模型交互的界面的设计界面仿真，以提取接口的驱动侧信号的当前值，在接收侧设置循环模拟模型。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式