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1. 发明申请

US20060176410A1 IC card 审中-公开
标题翻译： IC卡
公开(公告)号：US20060176410A1
公开(公告)日：2006-08-10
申请号：US11366737
申请日：2006-03-03
申请人： Masaki Nose , Junji Tomita , Tomohisa Shingai , Fumio Yamagishi , Kenzo Nishide , Shigeru Hashimoto , Yoshiyasu Sugimura , Yoshikazu Yabe , Futoshi Kisuno , Takahiro Hirano
发明人： Masaki Nose , Junji Tomita , Tomohisa Shingai , Fumio Yamagishi , Kenzo Nishide , Shigeru Hashimoto , Yoshiyasu Sugimura , Yoshikazu Yabe , Futoshi Kisuno , Takahiro Hirano
IPC分类号： G02F1/13 , G02F1/1347
CPC分类号： G06K19/07749 , G02F1/13473 , G02F1/13718 , G02F2001/13478 , G06K19/077 , G06K19/07703 , G06K19/07769 , G09G3/18 , G09G2310/0254 , G09G2310/06
摘要： In an IC card, cholesteric liquid crystal layers reflecting red light and a cholesteric liquid crystal layer reflecting blue light, in a planar state, are laminated, and a voltage is respectively applied to the laminated cholesteric liquid crystal layers, to change the orientation of the cholesteric liquid crystals between the planar state and a focal conic state, so as to transmit or reflect light, thereby displaying predetermined information.
摘要翻译：在IC卡中，叠层反射红光的胆甾醇型液晶层和反射蓝色光的胆甾型液晶层，分别向层叠的胆甾醇型液晶层施加电压，以改变在平面状态和焦点锥形状态之间的胆甾型液晶，以便透射或反射光，从而显示预定信息。

2. 发明申请

US20060198629A1 DISPLAY ELEMENT, METHOD OF DRIVING DISPLAY ELEMENT AND PORTABLE DISPLAY DEVICE 审中-公开
标题翻译：显示元件，驱动显示元件和便携式显示器件的方法
公开(公告)号：US20060198629A1
公开(公告)日：2006-09-07
申请号：US11276499
申请日：2006-03-02
申请人： Junji Tomita , Masaki Nose , Tomohisa Shingai , Fumio Yamagishi , Shigeru Hashimoto , Yoshiyasu Sugimura , Yoshikazu Yabe , Futoshi Kisuno , Takahiro Hirano , Kenzo Nishide , Shunji Baba
发明人： Junji Tomita , Masaki Nose , Tomohisa Shingai , Fumio Yamagishi , Shigeru Hashimoto , Yoshiyasu Sugimura , Yoshikazu Yabe , Futoshi Kisuno , Takahiro Hirano , Kenzo Nishide , Shunji Baba
IPC分类号： G03B19/00
CPC分类号： G02F1/13394 , G02F1/1339 , G02F1/1341 , G02F1/134327 , G02F1/13718 , G06K19/0723 , G06K19/077 , G06K19/07703 , G06K19/07749 , G09G3/3614 , G09G3/3629 , G09G2300/0486 , G09G2310/06 , H01Q1/2225 , H01Q1/248
摘要： It is an object of the present invention to improve mechanical durability of a portable display device using cholesteric liquid crystal with a memory function such as a non-contact IC card. A display element comprising two substrates 1 which oppose each other and a display portion (liquid crystal) 2 which is sandwiched by the substrates 1, comprises a wall structure 3 bearing a substrate on portions other than the display portion 2, in which the wall is perpendicular to the substrate 1 and a surface perpendicular to the wall is adhered to the substrate 1. Further, in the above display element, an area of the surface which is adhered to the substrate 1 is larger than an area of a surface of the display portion 2 which faces the substrate 1.
摘要翻译：本发明的目的是提高使用具有诸如非接触式IC卡等记忆功能的胆甾型液晶的便携式显示装置的机械耐久性。包括彼此相对的两个基板1和由基板1夹持的显示部分（液晶）2的显示元件包括：壁结构3，其在除显示部分2之外的部分上承载基板，其中壁是垂直于基板1的垂直于壁的表面粘附到基板1.此外，在上述显示元件中，附着到基板1的表面的面积大于显示器的表面的面积面向基板1的部分2。

3. 发明申请

US20080195842A1 ARRAY-TYPE PROCESSOR 失效
标题翻译：阵列式处理器
公开(公告)号：US20080195842A1
公开(公告)日：2008-08-14
申请号：US12030619
申请日：2008-02-13
申请人： Yoshitaka Izawa , Yoshikazu Yabe
发明人： Yoshitaka Izawa , Yoshikazu Yabe
IPC分类号： G06F9/00
CPC分类号： G06F15/7867 , H03K17/002 , Y02D10/12 , Y02D10/13
摘要： Occurrence and propagation of glitches caused by changing the path layout are suppressed, thereby reducing the power consumption. An array-type processor comprises a plurality of processor elements and can change the path layout relating to data transmission/reception between the processor elements depending on clock cycle. Each processor element comprises a layout information memory 11 that stores a layout information indicating signal relating to the layout of the paths, a delay adjusting circuit 12 that adjusts the timing of a layout information indicating signal Pin outputted from the layout information memory 11 at every clock cycle, and a wiring connection circuit 13 that changes a path to at least one of the other processor elements (PE) or function unit(s) (a register file unit 14 and an arithmetic logic unit 15) based on a layout information indicating signal Pout whose timing has been adjusted.
摘要翻译：通过改变路径布局导致的毛刺的发生和传播被抑制，从而降低功耗。阵列式处理器包括多个处理器元件，并且可以根据时钟周期改变与处理器元件之间的数据发送/接收有关的路径布局。每个处理器元件包括布局信息存储器11，其存储指示与路径布局相关的信号的布局信息;延迟调整电路12，其调整布局信息存储器11在每个时钟输出的布局信息指示信号Pin的定时循环，以及基于布局信息指示信号改变到其他处理器元件（PE）或功能单元（寄存器文件单元14和算术逻辑单元15）中的至少一个的路径的布线连接电路13 Pout的时间调整了。

4. 发明授权

US08402298B2 Array-type processor having delay adjusting circuit for adjusting a clock cycle in accordance with a critical path delay of the data path 有权
标题翻译：具有延迟调整电路的阵列型处理器，用于根据数据路径的关键路径延迟来调整时钟周期
公开(公告)号：US08402298B2
公开(公告)日：2013-03-19
申请号：US12071221
申请日：2008-02-19
申请人： Yoshikazu Yabe
发明人： Yoshikazu Yabe
IPC分类号： G06F1/12 , G06F1/00
CPC分类号： G06F1/04 , G06F15/7867
摘要： Disclosed is an array-type processor including a data path unit in which a plurality of processor elements are arranged in an array; a state-transition management unit that stores information for controlling changeover of data paths; and a delay adjusting circuit that adjusts delay of the input clock signal based upon information output from the state-transition management unit, and provides the delay-adjusted clock signal to the data path unit. The delay adjusting circuit has a delay control information memory and a programmable delay. The delay control information memory stores a plurality of items of delay control information, delay control information is read out using a configuration number supplied from the state-transition management unit as an address, and the delay control information is applied to the programmable array. The programmable delay delays the input clock signal by a delay time specified by the delay control information and provides the delayed clock signal to the data path unit.
摘要翻译：公开了一种阵列型处理器，包括数据路径单元，其中多个处理器元件排列成阵列; 状态转移管理单元，其存储用于控制数据路径的切换的信息; 以及延迟调整电路，其根据从状态转移管理单元输出的信息来调整输入时钟信号的延迟，并将延迟调整的时钟信号提供给数据路径单元。延迟调整电路具有延迟控制信息存储器和可编程延迟。延迟控制信息存储器存储多个延迟控制信息项，使用从状态转换管理单元提供的配置号作为地址读出延迟控制信息，并将延迟控制信息应用于可编程阵列。可编程延迟将输入时钟信号延迟延迟控制信息指定的延迟时间，并将延迟的时钟信号提供给数据路径单元。

5. 发明授权

US5845312A System for accessing dynamic random access memory where the logic/control circuit temporarily stops upon word line switching 失效
标题翻译：用于访问动态随机存取存储器的系统，其中逻辑/控制电路在字线切换时暂时停止
公开(公告)号：US5845312A
公开(公告)日：1998-12-01
申请号：US673315
申请日：1996-06-28
申请人： Tohru Kimura , Yoshiharu Aimoto , Yoshikazu Yabe
发明人： Tohru Kimura , Yoshiharu Aimoto , Yoshikazu Yabe
IPC分类号： G06F12/06 , G06F13/16 , G06F13/00
CPC分类号： G06F13/161 , Y02B60/1228
摘要： A memory access system including a logic/control circuit, a memory, an address bus connecting the logic/control circuit and the memory and an address transition detector circuit provided on address lines constituting the address bus, the address transition detector circuit detecting a memory access signal requesting memory access involving word line switching in the memory out of memory access signals transmitted from the logic/control circuit to the memory through the address lines and outputting a detection signal, and the logic/control circuit receiving input of the detection signal from the address transition detector circuit to temporarily stop its operation until the memory access is completed.
摘要翻译：包括逻辑/控制电路，存储器，连接逻辑/控制电路和存储器的地址总线以及设置在构成地址总线的地址线上的地址转换检测器电路的存储器访问系统，地址转换检测器电路检测存储器访问信号请求存储器访问，涉及存储器中的字线切换，通过地址线从逻辑/控制电路发送到存储器的存储器存取信号中，并输出检测信号，并且逻辑/控制电路接收来自地址转换检测器电路暂时停止其操作，直到存储器访问完成。

6. 发明授权

US07523292B2 Array-type processor having state control units controlling a plurality of processor elements arranged in a matrix 有权
标题翻译：具有状态控制单元的阵列式处理器，其控制以矩阵形式布置的多个处理器元件
公开(公告)号：US07523292B2
公开(公告)日：2009-04-21
申请号：US10682830
申请日：2003-10-10
申请人： Taro Fujii , Koichiro Furuta , Masato Motomura , Kenichiro Anjo , Yoshikazu Yabe , Toru Awashima , Takao Toi , Noritsugu Nakamura
发明人： Taro Fujii , Koichiro Furuta , Masato Motomura , Kenichiro Anjo , Yoshikazu Yabe , Toru Awashima , Takao Toi , Noritsugu Nakamura
IPC分类号： G06F15/00 , G06F15/76
CPC分类号： G06F15/8007
摘要： A multiplicity of processor elements, which both individually execute data processing in accordance with instruction codes that have been set as data and for which mutual connection relations are switch-controlled, are arranged in matrix form, and the instruction codes of this multiplicity of processor elements are successively switched by a state control unit. The state control units are composed of a plurality of units that intercommunicate to realize linked operation, and the multiplicity of processor elements is divided into a number of element areas that corresponds to the number of state control units. The plurality of state control units are arranged for each of the plurality of element areas and are connected to the processor elements, whereby the plurality of state control units can individually control a plurality of small-scale state transitions, or the plurality of state control units can cooperate to control a single large-scale state transition.
摘要翻译：多个处理器元件分别按照已经被设置为数据并且相互连接关系被切换控制的指令代码单独执行数据处理，以矩阵形式排列，并且该多个处理器元件的指令代码被状态控制单元依次切换。状态控制单元由多个单元组成，这些单元相互通信以实现链接操作，并且多个处理器元件被分成与状态控制单元数量相对应的多个元件区域。多个状态控制单元被布置用于多个元件区域中的每一个，并且连接到处理器元件，由此多个状态控制单元可以单独地控制多个小规模状态转换，或者多个状态控制单元可以合作控制单一的大规模国家转型。

7. 发明申请

US20080201526A1 Array-type processor having delay adjusting circuit 有权
标题翻译：具有延迟调整电路的阵列式处理器
公开(公告)号：US20080201526A1
公开(公告)日：2008-08-21
申请号：US12071221
申请日：2008-02-19
申请人： Yoshikazu Yabe
发明人： Yoshikazu Yabe
IPC分类号： G06F12/00
CPC分类号： G06F1/04 , G06F15/7867
摘要： Disclosed is an array-type processor including a data path unit in which a plurality of processor elements are arranged in an array; a state-transition management unit that stores information for controlling changeover of data paths; and a delay adjusting circuit that adjusts delay of the input clock signal based upon information output from the state-transition management unit, and provides the delay-adjusted clock signal to the data path unit. The delay adjusting circuit has a delay control information memory and a programmable delay. The delay control information memory stores a plurality of items of delay control information, delay control information is read out using a configuration number supplied from the state-transition management unit as an address, and the delay control information is applied to the programmable array. The programmable delay delays the input clock signal by a delay time specified by the delay control information and provides the delayed clock signal to the data path unit.
摘要翻译：公开了一种阵列型处理器，包括数据路径单元，其中多个处理器元件排列成阵列; 状态转移管理单元，其存储用于控制数据路径的切换的信息; 以及延迟调整电路，其根据从状态转移管理单元输出的信息来调整输入时钟信号的延迟，并将延迟调整的时钟信号提供给数据路径单元。延迟调整电路具有延迟控制信息存储器和可编程延迟。延迟控制信息存储器存储多个延迟控制信息项，使用从状态转换管理单元提供的配置号作为地址读出延迟控制信息，并将延迟控制信息应用于可编程阵列。可编程延迟将输入时钟信号延迟延迟控制信息指定的延迟时间，并将延迟的时钟信号提供给数据路径单元。

8. 发明授权

US06263413B1 Memory integrated circuit and main memory and graphics memory systems applying the above 失效
标题翻译：存储器集成电路和应用上述的主存储器和图形存储器系统
公开(公告)号：US06263413B1
公开(公告)日：2001-07-17
申请号：US09066605
申请日：1998-04-27
申请人： Masato Motomura , Yoshikazu Yabe , Yoshiharu Aimoto
发明人： Masato Motomura , Yoshikazu Yabe , Yoshiharu Aimoto
IPC分类号： G06F1202
CPC分类号： G06F12/08 , G06F2212/401 , G09G5/39 , G09G5/393 , G09G5/395 , G09G2340/02 , H03M7/30
摘要： A memory large scale integrated circuit with a data compression/decompression function, applicable to a main memory system, graphics memory system and such is provided with a data compression/decompression section. In this structure, compressed data-read with respect to a memory section is performed with an application of a data compressor within the compression/decompression section, and compressed data-write with respect to the memory section is performed with an application of a data decompressor within the compression/decompression section. Owing to this structure, even when a data bandwidth is physically the same as in the conventional case, it is practically possible to achieve a larger data bandwidth in use.
摘要翻译：具有数据压缩/解压缩功能的存储器大规模集成电路，适用于主存储器系统，图形存储器系统等具有数据压缩/解压缩部分。在该结构中，通过应用压缩/解压缩部分内的数据压缩器来执行相对于存储器部分的压缩数据读取，并且通过使用数据解压缩器来执行关于存储器部分的压缩数据写入在压缩/解压缩部分内。由于这种结构，即使当数据带宽在传统情况下物理上相同时，实际上可以在使用中实现更大的数据带宽。

9. 发明授权

US6034911A Semiconductor memory device for a rapid random access 失效
标题翻译：用于快速随机存取的半导体存储器件
公开(公告)号：US6034911A
公开(公告)日：2000-03-07
申请号：US729422
申请日：1996-10-11
申请人： Yoshiharu Aimoto , Tohru Kimura , Yoshikazu Yabe
发明人： Yoshiharu Aimoto , Tohru Kimura , Yoshikazu Yabe
IPC分类号： G11C11/401 , G11C7/00 , G11C8/12 , G11C11/407 , G11C8/00
CPC分类号： G11C8/12
摘要： A random access memory device includes a plurality of memory blocks, a memory block selecting circuit and a column decoder. Each memory block comprise a memory cell array including a plurality of word lines, a plurality of bit line pairs and a plurality of memory cells, and a peripheral circuit including sense amplifiers which amplify data read out onto bit line pairs when a memory block select signal for a particular memory block is active to connect all memory cells contained in one row with associated bit line pairs. An access control circuit changes a block address and a column address while maintaining a row address unchanged, thus performing a rapid random access of memory cells contained in a common row over the memory blocks.
摘要翻译：随机存取存储装置包括多个存储块，存储块选择电路和列解码器。每个存储块包括包括多个字线，多个位线对和多个存储器单元的存储单元阵列，以及包括读出放大器的外围电路，当存储器块选择信号对于特定的存储器块来说，活动的是将包含在一行中的所有存储单元与相关联的位线对连接。访问控制电路在保持行地址不变的同时改变块地址和列地址，从而对存储块中的公共行中包含的存储单元执行快速随机存取。

10. 发明授权

US08151089B2 Array-type processor having plural processor elements controlled by a state control unit 有权
标题翻译：具有由状态控制单元控制的多个处理器单元的阵列型处理器
公开(公告)号：US08151089B2
公开(公告)日：2012-04-03
申请号：US10694822
申请日：2003-10-29
申请人： Taro Fujii , Koichiro Furuta , Masato Motomura , Kenichiro Anjo , Yoshikazu Yabe , Toru Awashima , Takao Toi , Noritsugu Nakamura
发明人： Taro Fujii , Koichiro Furuta , Masato Motomura , Kenichiro Anjo , Yoshikazu Yabe , Toru Awashima , Takao Toi , Noritsugu Nakamura
IPC分类号： G06F15/00 , G06F15/76
CPC分类号： G06F15/8007
摘要： A multiplicity of processor elements that are arranged in rows and columns individually execute data processing in accordance with instruction codes that are individually set as data and supply event data as output. A state control unit is composed of a plurality of units that successively switch the instruction codes of the multiplicity of processor elements in accordance with a computer program and the event data, these state control units communicating with each other to realize linked operation as necessary. An event distributing means distributes event data to this plurality of state control units that intercommunicate to realize linked operation, whereby the plurality of state control units can realize linked operation to control a large-scale state transition.
摘要翻译：排列成行和列的多个处理器元件根据单独设置为数据并提供事件数据作为输出的指令代码单独执行数据处理。状态控制单元由多个单元组成，多个单元根据计算机程序和事件数据连续地切换多个处理器单元的指令代码，这些状态控制单元相互通信以根据需要实现链接操作。事件分配装置将事件数据分配给相互通信的多个状态控制单元，以实现链接操作，由此多个状态控制单元可以实现链接操作以控制大规模状态转换。

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