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1. 发明授权

US06263413B1 Memory integrated circuit and main memory and graphics memory systems applying the above 失效
标题翻译：存储器集成电路和应用上述的主存储器和图形存储器系统
公开(公告)号：US06263413B1
公开(公告)日：2001-07-17
申请号：US09066605
申请日：1998-04-27
申请人： Masato Motomura , Yoshikazu Yabe , Yoshiharu Aimoto
发明人： Masato Motomura , Yoshikazu Yabe , Yoshiharu Aimoto
IPC分类号： G06F1202
CPC分类号： G06F12/08 , G06F2212/401 , G09G5/39 , G09G5/393 , G09G5/395 , G09G2340/02 , H03M7/30
摘要： A memory large scale integrated circuit with a data compression/decompression function, applicable to a main memory system, graphics memory system and such is provided with a data compression/decompression section. In this structure, compressed data-read with respect to a memory section is performed with an application of a data compressor within the compression/decompression section, and compressed data-write with respect to the memory section is performed with an application of a data decompressor within the compression/decompression section. Owing to this structure, even when a data bandwidth is physically the same as in the conventional case, it is practically possible to achieve a larger data bandwidth in use.
摘要翻译：具有数据压缩/解压缩功能的存储器大规模集成电路，适用于主存储器系统，图形存储器系统等具有数据压缩/解压缩部分。在该结构中，通过应用压缩/解压缩部分内的数据压缩器来执行相对于存储器部分的压缩数据读取，并且通过使用数据解压缩器来执行关于存储器部分的压缩数据写入在压缩/解压缩部分内。由于这种结构，即使当数据带宽在传统情况下物理上相同时，实际上可以在使用中实现更大的数据带宽。

2. 发明授权

US07366821B2 High-speed memory system 有权
标题翻译：高速内存系统
公开(公告)号：US07366821B2
公开(公告)日：2008-04-29
申请号：US10311687
申请日：2001-06-20
申请人： Muneo Fukaishi , Masato Motomura , Yoshiharu Aimoto , Masakazu Yamashina
发明人： Muneo Fukaishi , Masato Motomura , Yoshiharu Aimoto , Masakazu Yamashina
IPC分类号： G06F12/00 , G06F9/00
CPC分类号： G11C7/1057 , G06F13/1684 , G11C7/10 , G11C7/1006 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1078 , G11C7/1084 , G11C7/1087
摘要： A memory system has a memory controller and a plurality of memories. The plurality of memories are connected via a switch to an end of a bus, which is connected to the memory controller, wherein the plurality of memories are controlled by the switch. By suppressing reflection and loads on the bus, a higher data transmission speed can be obtained.
摘要翻译：存储器系统具有存储器控制器和多个存储器。多个存储器经由开关连接到连接到存储器控制器的总线的一端，其中多个存储器由开关控制。通过抑制总线上的反射和负载，可以获得更高的数据传输速度。

3. 发明授权

US6034911A Semiconductor memory device for a rapid random access 失效
标题翻译：用于快速随机存取的半导体存储器件
公开(公告)号：US6034911A
公开(公告)日：2000-03-07
申请号：US729422
申请日：1996-10-11
申请人： Yoshiharu Aimoto , Tohru Kimura , Yoshikazu Yabe
发明人： Yoshiharu Aimoto , Tohru Kimura , Yoshikazu Yabe
IPC分类号： G11C11/401 , G11C7/00 , G11C8/12 , G11C11/407 , G11C8/00
CPC分类号： G11C8/12
摘要： A random access memory device includes a plurality of memory blocks, a memory block selecting circuit and a column decoder. Each memory block comprise a memory cell array including a plurality of word lines, a plurality of bit line pairs and a plurality of memory cells, and a peripheral circuit including sense amplifiers which amplify data read out onto bit line pairs when a memory block select signal for a particular memory block is active to connect all memory cells contained in one row with associated bit line pairs. An access control circuit changes a block address and a column address while maintaining a row address unchanged, thus performing a rapid random access of memory cells contained in a common row over the memory blocks.
摘要翻译：随机存取存储装置包括多个存储块，存储块选择电路和列解码器。每个存储块包括包括多个字线，多个位线对和多个存储器单元的存储单元阵列，以及包括读出放大器的外围电路，当存储器块选择信号对于特定的存储器块来说，活动的是将包含在一行中的所有存储单元与相关联的位线对连接。访问控制电路在保持行地址不变的同时改变块地址和列地址，从而对存储块中的公共行中包含的存储单元执行快速随机存取。

4. 发明授权

US5815442A Data transfer apparatus with large noise margin and reduced power dissipation 失效
标题翻译：数据传输设备，噪声容量大，功耗降低
公开(公告)号：US5815442A
公开(公告)日：1998-09-29
申请号：US705340
申请日：1996-08-29
申请人： Yoshiharu Aimoto , Tohru Kimura , Yoshikazu Yabe
发明人： Yoshiharu Aimoto , Tohru Kimura , Yoshikazu Yabe
IPC分类号： G11C11/41 , G11C7/10 , G11C11/409 , G11C11/417 , H03K17/687 , H03K19/0175 , H04L25/02 , G11C16/04
CPC分类号： G11C7/1051 , G11C7/10 , G11C7/1006
摘要： In a data transfer apparatus powered by first and second power supply voltages, a data output circuit generates first complementary output signals, a data transfer circuit having a large load capacitance transfers the first complementary output signals to generate second complementary output signals, and an amplifier circuit amplifies the second complementary output signals to generate third complementary output signals. A first transfer gate circuit is connected between the data output circuit and the data transfer circuit. A second transfer gate circuit is connected between the data transfer circuit and the amplifier circuit. The first, second and third complementary output signals are caused to be approximately at an intermediate level between the first and second voltages.
摘要翻译：在由第一和第二电源电压供电的数据传送装置中，数据输出电路产生第一互补输出信号，具有大负载电容的数据传输电路传送第一互补输出信号以产生第二互补输出信号，以及放大电路放大第二互补输出信号以产生第三互补输出信号。第一传输门电路连接在数据输出电路和数据传输电路之间。第二传输门电路连接在数据传输电路和放大器电路之间。使第一，第二和第三互补输出信号大致处于第一和第二电压之间的中间电平。

5. 发明授权

US5714893A Signal transmission circuit 失效
标题翻译：信号传输电路
公开(公告)号：US5714893A
公开(公告)日：1998-02-03
申请号：US619312
申请日：1996-03-21
申请人： Yoshiharu Aimoto , Tohru Kimura , Yoshikazu Yabe
发明人： Yoshiharu Aimoto , Tohru Kimura , Yoshikazu Yabe
IPC分类号： G11C11/413 , G11C7/10 , G11C11/401 , G11C11/409 , G11C11/41 , H03K19/018 , G11C11/40
CPC分类号： G11C7/1006 , G11C7/1048
摘要： A signal transmission circuit suitable for a memory device includes a signal generating section for generating a data signal from a power source, a pair of signal transmission lines for transferring the data signal by transferring signal charge associated by the data signal, an amplifying section for amplifying the data signal transferred by the signal transmission lines, and a precharge section for precharging the output of the signal generating section, the pair of signal transmission lines and the output of the amplifying section to a median potential level between the potential levels of the power source. The precharge section provides power saving as well as a larger noise margin.
摘要翻译：一种适用于存储器件的信号传输电路包括一个用于从电源产生数据信号的信号产生部分，一对用于通过传送与该数据信号相关联的信号电荷传送数据信号的信号传输线，一个放大部分由信号传输线传送的数据信号，以及预充电部分，用于将信号产生部分的输出，一对信号传输线和放大部分的输出预充电到电源的电位电平之间的中间电位电平。预充电部分提供省电以及更大的噪声容限。

6. 发明授权

US5845312A System for accessing dynamic random access memory where the logic/control circuit temporarily stops upon word line switching 失效
标题翻译：用于访问动态随机存取存储器的系统，其中逻辑/控制电路在字线切换时暂时停止
公开(公告)号：US5845312A
公开(公告)日：1998-12-01
申请号：US673315
申请日：1996-06-28
申请人： Tohru Kimura , Yoshiharu Aimoto , Yoshikazu Yabe
发明人： Tohru Kimura , Yoshiharu Aimoto , Yoshikazu Yabe
IPC分类号： G06F12/06 , G06F13/16 , G06F13/00
CPC分类号： G06F13/161 , Y02B60/1228
摘要： A memory access system including a logic/control circuit, a memory, an address bus connecting the logic/control circuit and the memory and an address transition detector circuit provided on address lines constituting the address bus, the address transition detector circuit detecting a memory access signal requesting memory access involving word line switching in the memory out of memory access signals transmitted from the logic/control circuit to the memory through the address lines and outputting a detection signal, and the logic/control circuit receiving input of the detection signal from the address transition detector circuit to temporarily stop its operation until the memory access is completed.
摘要翻译：包括逻辑/控制电路，存储器，连接逻辑/控制电路和存储器的地址总线以及设置在构成地址总线的地址线上的地址转换检测器电路的存储器访问系统，地址转换检测器电路检测存储器访问信号请求存储器访问，涉及存储器中的字线切换，通过地址线从逻辑/控制电路发送到存储器的存储器存取信号中，并输出检测信号，并且逻辑/控制电路接收来自地址转换检测器电路暂时停止其操作，直到存储器访问完成。

7. 发明授权

US06212120B1 Semiconductor memory device with less power consumption 有权
标题翻译：半导体存储器件具有较少的功耗
公开(公告)号：US06212120B1
公开(公告)日：2001-04-03
申请号：US09576781
申请日：2000-05-23
申请人： Noritsugu Nakamura , Yoshiharu Aimoto
发明人： Noritsugu Nakamura , Yoshiharu Aimoto
IPC分类号： G11C712
CPC分类号： G11C7/1048
摘要： A semiconductor memory device includes a pair of data lines, a precharging and equalizing circuit, a setting circuit and a data write circuit. The precharging and equalizing circuit is provided between the data lines to equally precharge the data lines to a first voltage in response to a precharge and equalize signal. The setting circuit is provided between the data lines to set one of the precharged data lines to a second voltage in response to data signals. The second voltage is lower than the first voltage. Also, a data Is written to a memory cell based on the second voltage of the one precharged data line and the first voltage of the other precharged data line. The data write circuit supplies the data signals to the setting circuit based on the data.
摘要翻译：半导体存储器件包括一对数据线，预充电和均衡电路，设置电路和数据写入电路。预充电均衡电路设置在数据线之间，以响应于预充电和均衡信号将数据线均等地预充电到第一电压。设置电路设置在数据线之间，以响应于数据信号将一个预充电数据线设置为第二电压。第二电压低于第一电压。此外，基于一个预充电数据线的第二电压和另一个预充电数据线的第一电压将数据写入存储器单元。数据写入电路根据数据将数据信号提供给设置电路。

8. 发明申请

US20050213416A1 Semiconductor circuit apparatus with power save mode 有权
标题翻译：具有省电模式的半导体电路设备
公开(公告)号：US20050213416A1
公开(公告)日：2005-09-29
申请号：US11088750
申请日：2005-03-25
申请人： Yoshiharu Aimoto
发明人： Yoshiharu Aimoto
IPC分类号： H01L21/822 , G06F1/32 , H01L27/04 , H01P1/20 , H03K19/00
CPC分类号： G06F1/3203
摘要： A semiconductor circuit apparatus comprises a substrate and a circuit block including a memory formed on the substrate. The circuit block performs regular operations at a first power supply voltage in an active mode, and a part of the circuit block is stopped and the memory keeps stored data at a second power supply voltage smaller than the first power supply voltage in a power save mode. The memory holds the stored data during the power save mode, resulting in higher speed return to a regular active mode, as well as power consumption reduction.
摘要翻译：半导体电路装置包括基板和包括形成在基板上的存储器的电路块。该电路块在主动模式下以第一电源电压执行正常操作，并且电池块的一部分停止，并且存储器将存储的数据保存在比节电模式下小于第一电源电压的第二电源电压。存储器在节能模式期间保存存储的数据，导致更高的速度返回到常规的活动模式以及功耗降低。

9. 发明授权

US5521877A Serial random access memory device capable of reducing peak current through subword data register 失效
标题翻译：串行随机存取存储器能够通过子字数据寄存器减少峰值电流
公开(公告)号：US5521877A
公开(公告)日：1996-05-28
申请号：US288248
申请日：1994-08-09
申请人： Yoshiharu Aimoto
发明人： Yoshiharu Aimoto
IPC分类号： G11C11/401 , G11C7/10 , G11C8/00
CPC分类号： G11C7/103 , G11C7/1075
摘要： In a semiconductor memory device comprising a plurality of memory cells which are arranged on a cell area defined by a first number of column signal lines and a second number of row signal lines, a row decoder produces a row selection signal through one of the second number of row signal lines. A serial access section includes a data register and serially accesses a part of the plurality of memory cells arranged along the one end of the second number of row signal lines. The plurality of memory cells are divided into a plurality of cell blocks. The data register is divided into a plurality of subword data registers each of which corresponds to each of the plurality of cell blocks. The serial access section accesses the plurality of cell blocks, in order, at a predetermined interval. Each of the plurality of subword data registers stores subword data in each of the plurality of cell blocks, in order, at the predetermined interval.
摘要翻译：在包括布置在由第一数量的列信号线和第二数量的行信号线限定的单元区域上的多个存储单元的半导体存储器件中，行解码器通过第二数目之一产生行选择信号的行信号线。串行访问部分包括数据寄存器，并且串行地访问沿着第二行行信号线的一端布置的多个存储单元的一部分。多个存储单元被分成多个单元块。数据寄存器被分成多个子字数据寄存器，每个子字数据寄存器对应于多个单元块中的每一个。串行访问部分以预定间隔按顺序访问多个单元块。多个子字数据寄存器中的每一个以预定间隔按顺序存储多个单元块中的每一个中的子字数据。

10. 发明授权

US07248533B2 Semiconductor circuit apparatus with power save mode 有权
标题翻译：具有省电模式的半导体电路设备
公开(公告)号：US07248533B2
公开(公告)日：2007-07-24
申请号：US11088750
申请日：2005-03-25
申请人： Yoshiharu Aimoto
发明人： Yoshiharu Aimoto
IPC分类号： G11C5/14
CPC分类号： G06F1/3203
摘要： A semiconductor circuit apparatus comprises a substrate and a circuit block including a memory formed on the substrate. The circuit block performs regular operations at a first power supply voltage in an active mode, and a part of the circuit block is stopped and the memory keeps stored data at a second power supply voltage smaller than the first power supply voltage in a power save mode. The memory holds the stored data during the power save mode, resulting in higher speed return to a regular active mode, as well as power consumption reduction.
摘要翻译：半导体电路装置包括基板和包括形成在基板上的存储器的电路块。该电路块在主动模式下以第一电源电压执行正常操作，并且电池块的一部分停止，并且存储器将存储的数据保存在比节电模式下小于第一电源电压的第二电源电压。存储器在节能模式期间保存存储的数据，导致更高的速度返回到常规的活动模式以及功耗降低。

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