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1. 发明授权

US06263413B1 Memory integrated circuit and main memory and graphics memory systems applying the above 失效
标题翻译：存储器集成电路和应用上述的主存储器和图形存储器系统
公开(公告)号：US06263413B1
公开(公告)日：2001-07-17
申请号：US09066605
申请日：1998-04-27
申请人： Masato Motomura , Yoshikazu Yabe , Yoshiharu Aimoto
发明人： Masato Motomura , Yoshikazu Yabe , Yoshiharu Aimoto
IPC分类号： G06F1202
CPC分类号： G06F12/08 , G06F2212/401 , G09G5/39 , G09G5/393 , G09G5/395 , G09G2340/02 , H03M7/30
摘要： A memory large scale integrated circuit with a data compression/decompression function, applicable to a main memory system, graphics memory system and such is provided with a data compression/decompression section. In this structure, compressed data-read with respect to a memory section is performed with an application of a data compressor within the compression/decompression section, and compressed data-write with respect to the memory section is performed with an application of a data decompressor within the compression/decompression section. Owing to this structure, even when a data bandwidth is physically the same as in the conventional case, it is practically possible to achieve a larger data bandwidth in use.
摘要翻译：具有数据压缩/解压缩功能的存储器大规模集成电路，适用于主存储器系统，图形存储器系统等具有数据压缩/解压缩部分。在该结构中，通过应用压缩/解压缩部分内的数据压缩器来执行相对于存储器部分的压缩数据读取，并且通过使用数据解压缩器来执行关于存储器部分的压缩数据写入在压缩/解压缩部分内。由于这种结构，即使当数据带宽在传统情况下物理上相同时，实际上可以在使用中实现更大的数据带宽。

2. 发明授权

US6034911A Semiconductor memory device for a rapid random access 失效
标题翻译：用于快速随机存取的半导体存储器件
公开(公告)号：US6034911A
公开(公告)日：2000-03-07
申请号：US729422
申请日：1996-10-11
申请人： Yoshiharu Aimoto , Tohru Kimura , Yoshikazu Yabe
发明人： Yoshiharu Aimoto , Tohru Kimura , Yoshikazu Yabe
IPC分类号： G11C11/401 , G11C7/00 , G11C8/12 , G11C11/407 , G11C8/00
CPC分类号： G11C8/12
摘要： A random access memory device includes a plurality of memory blocks, a memory block selecting circuit and a column decoder. Each memory block comprise a memory cell array including a plurality of word lines, a plurality of bit line pairs and a plurality of memory cells, and a peripheral circuit including sense amplifiers which amplify data read out onto bit line pairs when a memory block select signal for a particular memory block is active to connect all memory cells contained in one row with associated bit line pairs. An access control circuit changes a block address and a column address while maintaining a row address unchanged, thus performing a rapid random access of memory cells contained in a common row over the memory blocks.
摘要翻译：随机存取存储装置包括多个存储块，存储块选择电路和列解码器。每个存储块包括包括多个字线，多个位线对和多个存储器单元的存储单元阵列，以及包括读出放大器的外围电路，当存储器块选择信号对于特定的存储器块来说，活动的是将包含在一行中的所有存储单元与相关联的位线对连接。访问控制电路在保持行地址不变的同时改变块地址和列地址，从而对存储块中的公共行中包含的存储单元执行快速随机存取。

3. 发明授权

US5845312A System for accessing dynamic random access memory where the logic/control circuit temporarily stops upon word line switching 失效
标题翻译：用于访问动态随机存取存储器的系统，其中逻辑/控制电路在字线切换时暂时停止
公开(公告)号：US5845312A
公开(公告)日：1998-12-01
申请号：US673315
申请日：1996-06-28
申请人： Tohru Kimura , Yoshiharu Aimoto , Yoshikazu Yabe
发明人： Tohru Kimura , Yoshiharu Aimoto , Yoshikazu Yabe
IPC分类号： G06F12/06 , G06F13/16 , G06F13/00
CPC分类号： G06F13/161 , Y02B60/1228
摘要： A memory access system including a logic/control circuit, a memory, an address bus connecting the logic/control circuit and the memory and an address transition detector circuit provided on address lines constituting the address bus, the address transition detector circuit detecting a memory access signal requesting memory access involving word line switching in the memory out of memory access signals transmitted from the logic/control circuit to the memory through the address lines and outputting a detection signal, and the logic/control circuit receiving input of the detection signal from the address transition detector circuit to temporarily stop its operation until the memory access is completed.
摘要翻译：包括逻辑/控制电路，存储器，连接逻辑/控制电路和存储器的地址总线以及设置在构成地址总线的地址线上的地址转换检测器电路的存储器访问系统，地址转换检测器电路检测存储器访问信号请求存储器访问，涉及存储器中的字线切换，通过地址线从逻辑/控制电路发送到存储器的存储器存取信号中，并输出检测信号，并且逻辑/控制电路接收来自地址转换检测器电路暂时停止其操作，直到存储器访问完成。

4. 发明授权

US5815442A Data transfer apparatus with large noise margin and reduced power dissipation 失效
标题翻译：数据传输设备，噪声容量大，功耗降低
公开(公告)号：US5815442A
公开(公告)日：1998-09-29
申请号：US705340
申请日：1996-08-29
申请人： Yoshiharu Aimoto , Tohru Kimura , Yoshikazu Yabe
发明人： Yoshiharu Aimoto , Tohru Kimura , Yoshikazu Yabe
IPC分类号： G11C11/41 , G11C7/10 , G11C11/409 , G11C11/417 , H03K17/687 , H03K19/0175 , H04L25/02 , G11C16/04
CPC分类号： G11C7/1051 , G11C7/10 , G11C7/1006
摘要： In a data transfer apparatus powered by first and second power supply voltages, a data output circuit generates first complementary output signals, a data transfer circuit having a large load capacitance transfers the first complementary output signals to generate second complementary output signals, and an amplifier circuit amplifies the second complementary output signals to generate third complementary output signals. A first transfer gate circuit is connected between the data output circuit and the data transfer circuit. A second transfer gate circuit is connected between the data transfer circuit and the amplifier circuit. The first, second and third complementary output signals are caused to be approximately at an intermediate level between the first and second voltages.
摘要翻译：在由第一和第二电源电压供电的数据传送装置中，数据输出电路产生第一互补输出信号，具有大负载电容的数据传输电路传送第一互补输出信号以产生第二互补输出信号，以及放大电路放大第二互补输出信号以产生第三互补输出信号。第一传输门电路连接在数据输出电路和数据传输电路之间。第二传输门电路连接在数据传输电路和放大器电路之间。使第一，第二和第三互补输出信号大致处于第一和第二电压之间的中间电平。

5. 发明授权

US5714893A Signal transmission circuit 失效
标题翻译：信号传输电路
公开(公告)号：US5714893A
公开(公告)日：1998-02-03
申请号：US619312
申请日：1996-03-21
申请人： Yoshiharu Aimoto , Tohru Kimura , Yoshikazu Yabe
发明人： Yoshiharu Aimoto , Tohru Kimura , Yoshikazu Yabe
IPC分类号： G11C11/413 , G11C7/10 , G11C11/401 , G11C11/409 , G11C11/41 , H03K19/018 , G11C11/40
CPC分类号： G11C7/1006 , G11C7/1048
摘要： A signal transmission circuit suitable for a memory device includes a signal generating section for generating a data signal from a power source, a pair of signal transmission lines for transferring the data signal by transferring signal charge associated by the data signal, an amplifying section for amplifying the data signal transferred by the signal transmission lines, and a precharge section for precharging the output of the signal generating section, the pair of signal transmission lines and the output of the amplifying section to a median potential level between the potential levels of the power source. The precharge section provides power saving as well as a larger noise margin.
摘要翻译：一种适用于存储器件的信号传输电路包括一个用于从电源产生数据信号的信号产生部分，一对用于通过传送与该数据信号相关联的信号电荷传送数据信号的信号传输线，一个放大部分由信号传输线传送的数据信号，以及预充电部分，用于将信号产生部分的输出，一对信号传输线和放大部分的输出预充电到电源的电位电平之间的中间电位电平。预充电部分提供省电以及更大的噪声容限。

6. 发明授权

US07523292B2 Array-type processor having state control units controlling a plurality of processor elements arranged in a matrix 有权
标题翻译：具有状态控制单元的阵列式处理器，其控制以矩阵形式布置的多个处理器元件
公开(公告)号：US07523292B2
公开(公告)日：2009-04-21
申请号：US10682830
申请日：2003-10-10
申请人： Taro Fujii , Koichiro Furuta , Masato Motomura , Kenichiro Anjo , Yoshikazu Yabe , Toru Awashima , Takao Toi , Noritsugu Nakamura
发明人： Taro Fujii , Koichiro Furuta , Masato Motomura , Kenichiro Anjo , Yoshikazu Yabe , Toru Awashima , Takao Toi , Noritsugu Nakamura
IPC分类号： G06F15/00 , G06F15/76
CPC分类号： G06F15/8007
摘要： A multiplicity of processor elements, which both individually execute data processing in accordance with instruction codes that have been set as data and for which mutual connection relations are switch-controlled, are arranged in matrix form, and the instruction codes of this multiplicity of processor elements are successively switched by a state control unit. The state control units are composed of a plurality of units that intercommunicate to realize linked operation, and the multiplicity of processor elements is divided into a number of element areas that corresponds to the number of state control units. The plurality of state control units are arranged for each of the plurality of element areas and are connected to the processor elements, whereby the plurality of state control units can individually control a plurality of small-scale state transitions, or the plurality of state control units can cooperate to control a single large-scale state transition.
摘要翻译：多个处理器元件分别按照已经被设置为数据并且相互连接关系被切换控制的指令代码单独执行数据处理，以矩阵形式排列，并且该多个处理器元件的指令代码被状态控制单元依次切换。状态控制单元由多个单元组成，这些单元相互通信以实现链接操作，并且多个处理器元件被分成与状态控制单元数量相对应的多个元件区域。多个状态控制单元被布置用于多个元件区域中的每一个，并且连接到处理器元件，由此多个状态控制单元可以单独地控制多个小规模状态转换，或者多个状态控制单元可以合作控制单一的大规模国家转型。

7. 发明授权

US08151089B2 Array-type processor having plural processor elements controlled by a state control unit 有权
标题翻译：具有由状态控制单元控制的多个处理器单元的阵列型处理器
公开(公告)号：US08151089B2
公开(公告)日：2012-04-03
申请号：US10694822
申请日：2003-10-29
申请人： Taro Fujii , Koichiro Furuta , Masato Motomura , Kenichiro Anjo , Yoshikazu Yabe , Toru Awashima , Takao Toi , Noritsugu Nakamura
发明人： Taro Fujii , Koichiro Furuta , Masato Motomura , Kenichiro Anjo , Yoshikazu Yabe , Toru Awashima , Takao Toi , Noritsugu Nakamura
IPC分类号： G06F15/00 , G06F15/76
CPC分类号： G06F15/8007
摘要： A multiplicity of processor elements that are arranged in rows and columns individually execute data processing in accordance with instruction codes that are individually set as data and supply event data as output. A state control unit is composed of a plurality of units that successively switch the instruction codes of the multiplicity of processor elements in accordance with a computer program and the event data, these state control units communicating with each other to realize linked operation as necessary. An event distributing means distributes event data to this plurality of state control units that intercommunicate to realize linked operation, whereby the plurality of state control units can realize linked operation to control a large-scale state transition.
摘要翻译：排列成行和列的多个处理器元件根据单独设置为数据并提供事件数据作为输出的指令代码单独执行数据处理。状态控制单元由多个单元组成，多个单元根据计算机程序和事件数据连续地切换多个处理器单元的指令代码，这些状态控制单元相互通信以根据需要实现链接操作。事件分配装置将事件数据分配给相互通信的多个状态控制单元，以实现链接操作，由此多个状态控制单元可以实现链接操作以控制大规模状态转换。

8. 发明授权

US06556484B2 Plural line buffer type memory LSI 失效
公开(公告)号：US06556484B2
公开(公告)日：2003-04-29
申请号：US09746809
申请日：2000-12-20
申请人： Yoshikazu Yabe , Masato Motomura
发明人： Yoshikazu Yabe , Masato Motomura
IPC分类号： G11C700
CPC分类号： G11C7/1039
摘要： In a plural line buffer type memory LSI, a line selection register 16 (holding an address for designating a line buffer) is added. The value of the line selection register 16 is previously updated by a memory access instruction having a room in an address. Thus, it is possible to maintain compatibility with input/output terminals of a general purpose memory LSI, or to prevent the increase in the number of input/output terminals, and also to prevent the increase of the memory access delay attributable to the restriction in connection with the issue of the commands. Accordingly, it is possible to maintain the compatibility with the general purpose memory LSI having no line buffer, or alternatively to prevent the increase of the memory access delay attributable to a restriction in an interval for issuing the commands.

9. 发明授权

US06414880B1 Multiple line buffer type memory LSI 失效
公开(公告)号：US06414880B1
公开(公告)日：2002-07-02
申请号：US09933820
申请日：2001-08-22
申请人： Yoshikazu Yabe , Masato Motomura
发明人： Yoshikazu Yabe , Masato Motomura
IPC分类号： G11C700
CPC分类号： G11C7/1087 , G11C7/1051 , G11C7/1078
摘要： In a multiple line buffer type memory LSI, when line buffers retaining data read out from a memory section does not exist in a multiple line buffer section, data retained in any of the line buffers are copied and held temporarily in standby in the write-back buffers. The data read out from the memory section are retained in the line buffers. The data temporarily held in standby in the write-back buffers are written back into the memory section.

10. 发明申请

US20080195842A1 ARRAY-TYPE PROCESSOR 失效
标题翻译：阵列式处理器
公开(公告)号：US20080195842A1
公开(公告)日：2008-08-14
申请号：US12030619
申请日：2008-02-13
申请人： Yoshitaka Izawa , Yoshikazu Yabe
发明人： Yoshitaka Izawa , Yoshikazu Yabe
IPC分类号： G06F9/00
CPC分类号： G06F15/7867 , H03K17/002 , Y02D10/12 , Y02D10/13
摘要： Occurrence and propagation of glitches caused by changing the path layout are suppressed, thereby reducing the power consumption. An array-type processor comprises a plurality of processor elements and can change the path layout relating to data transmission/reception between the processor elements depending on clock cycle. Each processor element comprises a layout information memory 11 that stores a layout information indicating signal relating to the layout of the paths, a delay adjusting circuit 12 that adjusts the timing of a layout information indicating signal Pin outputted from the layout information memory 11 at every clock cycle, and a wiring connection circuit 13 that changes a path to at least one of the other processor elements (PE) or function unit(s) (a register file unit 14 and an arithmetic logic unit 15) based on a layout information indicating signal Pout whose timing has been adjusted.
摘要翻译：通过改变路径布局导致的毛刺的发生和传播被抑制，从而降低功耗。阵列式处理器包括多个处理器元件，并且可以根据时钟周期改变与处理器元件之间的数据发送/接收有关的路径布局。每个处理器元件包括布局信息存储器11，其存储指示与路径布局相关的信号的布局信息;延迟调整电路12，其调整布局信息存储器11在每个时钟输出的布局信息指示信号Pin的定时循环，以及基于布局信息指示信号改变到其他处理器元件（PE）或功能单元（寄存器文件单元14和算术逻辑单元15）中的至少一个的路径的布线连接电路13 Pout的时间调整了。

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