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1. 发明授权

US07523292B2 Array-type processor having state control units controlling a plurality of processor elements arranged in a matrix 有权
标题翻译：具有状态控制单元的阵列式处理器，其控制以矩阵形式布置的多个处理器元件
公开(公告)号：US07523292B2
公开(公告)日：2009-04-21
申请号：US10682830
申请日：2003-10-10
申请人： Taro Fujii , Koichiro Furuta , Masato Motomura , Kenichiro Anjo , Yoshikazu Yabe , Toru Awashima , Takao Toi , Noritsugu Nakamura
发明人： Taro Fujii , Koichiro Furuta , Masato Motomura , Kenichiro Anjo , Yoshikazu Yabe , Toru Awashima , Takao Toi , Noritsugu Nakamura
IPC分类号： G06F15/00 , G06F15/76
CPC分类号： G06F15/8007
摘要： A multiplicity of processor elements, which both individually execute data processing in accordance with instruction codes that have been set as data and for which mutual connection relations are switch-controlled, are arranged in matrix form, and the instruction codes of this multiplicity of processor elements are successively switched by a state control unit. The state control units are composed of a plurality of units that intercommunicate to realize linked operation, and the multiplicity of processor elements is divided into a number of element areas that corresponds to the number of state control units. The plurality of state control units are arranged for each of the plurality of element areas and are connected to the processor elements, whereby the plurality of state control units can individually control a plurality of small-scale state transitions, or the plurality of state control units can cooperate to control a single large-scale state transition.
摘要翻译：多个处理器元件分别按照已经被设置为数据并且相互连接关系被切换控制的指令代码单独执行数据处理，以矩阵形式排列，并且该多个处理器元件的指令代码被状态控制单元依次切换。状态控制单元由多个单元组成，这些单元相互通信以实现链接操作，并且多个处理器元件被分成与状态控制单元数量相对应的多个元件区域。多个状态控制单元被布置用于多个元件区域中的每一个，并且连接到处理器元件，由此多个状态控制单元可以单独地控制多个小规模状态转换，或者多个状态控制单元可以合作控制单一的大规模国家转型。

2. 发明授权

US08151089B2 Array-type processor having plural processor elements controlled by a state control unit 有权
标题翻译：具有由状态控制单元控制的多个处理器单元的阵列型处理器
公开(公告)号：US08151089B2
公开(公告)日：2012-04-03
申请号：US10694822
申请日：2003-10-29
申请人： Taro Fujii , Koichiro Furuta , Masato Motomura , Kenichiro Anjo , Yoshikazu Yabe , Toru Awashima , Takao Toi , Noritsugu Nakamura
发明人： Taro Fujii , Koichiro Furuta , Masato Motomura , Kenichiro Anjo , Yoshikazu Yabe , Toru Awashima , Takao Toi , Noritsugu Nakamura
IPC分类号： G06F15/00 , G06F15/76
CPC分类号： G06F15/8007
摘要： A multiplicity of processor elements that are arranged in rows and columns individually execute data processing in accordance with instruction codes that are individually set as data and supply event data as output. A state control unit is composed of a plurality of units that successively switch the instruction codes of the multiplicity of processor elements in accordance with a computer program and the event data, these state control units communicating with each other to realize linked operation as necessary. An event distributing means distributes event data to this plurality of state control units that intercommunicate to realize linked operation, whereby the plurality of state control units can realize linked operation to control a large-scale state transition.
摘要翻译：排列成行和列的多个处理器元件根据单独设置为数据并提供事件数据作为输出的指令代码单独执行数据处理。状态控制单元由多个单元组成，多个单元根据计算机程序和事件数据连续地切换多个处理器单元的指令代码，这些状态控制单元相互通信以根据需要实现链接操作。事件分配装置将事件数据分配给相互通信的多个状态控制单元，以实现链接操作，由此多个状态控制单元可以实现链接操作以控制大规模状态转换。

3. 发明授权

US08176451B2 Behavioral synthesis apparatus, behavioral synthesis method, and computer readable recording medium 有权
标题翻译：行为综合装置，行为综合方法和计算机可读记录介质
公开(公告)号：US08176451B2
公开(公告)日：2012-05-08
申请号：US12569043
申请日：2009-09-29
申请人： Takao Toi , Noritsugu Nakamura , Yoshinosuke Kato , Toru Awashima , Taro Fujii , Toshiro Kitaoka , Koichiro Furuta , Masato Motomura
发明人： Takao Toi , Noritsugu Nakamura , Yoshinosuke Kato , Toru Awashima , Taro Fujii , Toshiro Kitaoka , Koichiro Furuta , Masato Motomura
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A behavioral synthesis apparatus includes a acquisition unit, a scheduling unit and a generation unit. The acquisition unit acquires a behavioral level description describing an operation of a semiconductor integrated circuit. The scheduling unit separates the acquired behavioral level description into N stage descriptions, and makes a schedule in such a way that input/output operations and computations among the N stage descriptions are pipelined. The generation unit generates a register transfer level description based on the N stage descriptions and a result of scheduling performed by the scheduling unit in such a way as to form stage circuits respectively corresponding to the N stage descriptions and a state control circuit which controls possible 2N−1 stage control states of the semiconductor integrated circuit. The generation unit generates the register transfer level description in such a way as to inhibit the operation of a stage circuit which need not be operated.
摘要翻译：行为综合装置包括获取单元，调度单元和生成单元。采集单元获取描述半导体集成电路的操作的行为级别描述。调度单元将所获取的行为级别描述分为N级描述，并且进行调度，使得N级描述中的输入/输出操作和计算被流水线化。生成单元基于N级描述和由调度单元执行的调度结果以分别对应于N级描述的级电路和控制可能的2N的状态控制电路来生成寄存器传送级别描述 -1级控制状态的半导体集成电路。生成单元以禁止不需要操作的级电路的操作的方式生成寄存器传送级别描述。

4. 发明授权

US07120903B2 Data processing apparatus and method for generating the data of an object program for a parallel operation apparatus 有权
标题翻译：用于生成用于并行操作装置的对象程序的数据的数据处理装置和方法
公开(公告)号：US07120903B2
公开(公告)日：2006-10-10
申请号：US10252564
申请日：2002-09-24
申请人： Takao Toi , Toru Awashima , Yoshiyuki Miyazawa , Noritsugu Nakamura , Taro Fujii , Koichiro Furuta , Masato Motomura
发明人： Takao Toi , Toru Awashima , Yoshiyuki Miyazawa , Noritsugu Nakamura , Taro Fujii , Koichiro Furuta , Masato Motomura
IPC分类号： G06F9/45 , G06F15/00 , G06F7/38 , G06F15/76 , G06F9/46
CPC分类号： G06F17/5045
摘要： An object code for sequentially switching contexts of processing circuits arrayed in a matrix in a parallel operation apparatus is generated from a general source code descriptive of operation of the parallel operation apparatus. A Data Flow Graph (DFG) is generated from the source code descriptive of operation of the parallel operation apparatus according to limiting conditions, registered in advance, representing a physical structure, etc. of the parallel operation apparatus, and scheduled in a Control Data Flow Graph (CDFG). An Register Transfer Level (RTL) description is generated from the CDFG, converting a finite-state machine into an object code and converting a data path into a net list. An object code of the processing circuits is generated in each context from the net list.
摘要翻译：根据描述并行操作装置的操作的通用源代码，生成用于顺序切换并行操作装置中矩阵排列的处理电路的上下文的目标代码。根据并行操作装置的操作的源代码，根据预先登记的表示并行运算装置的物理结构等的限制条件生成数据流图（DFG），并将其调度到控制数据流图（CDFG）。从CDFG生成寄存器传送级别（RTL）描述，将有限状态机转换为目标代码，并将数据路径转换为网络列表。在每个上下文中，从网络列表生成处理电路的目标代码。

5. 发明申请

US20080040700A1 Behavioral synthesizer, debugger, writing device and computer aided design system and method 审中-公开
标题翻译：行为综合器，调试器，书写装置和计算机辅助设计系统及方法
公开(公告)号：US20080040700A1
公开(公告)日：2008-02-14
申请号：US11727948
申请日：2007-03-29
申请人： Yoshinosuke Katoh , Toru Awashima , Noritsugu Nakamura , Hirokazu Kami , Takao Toi
发明人： Yoshinosuke Katoh , Toru Awashima , Noritsugu Nakamura , Hirokazu Kami , Takao Toi
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5045
摘要： The liveness information that is obtained from behavioral synthesis and that shows the periods during which variables described in a behavioral level description have valid values is used for processing at a logic synthesizing stage, placement and routing stage, debugging stage, writing stage of circuit information to a reconfigurable device, or the like, so as to use storage elements that are to be allocated to the variables described in the behavioral level description in common and to achieve optimization such as minimizing data paths and the like. Also in a debugger and in a writing device for writing circuit information, the aforementioned liveness information is used to execute a task of not displaying invalid variables, a task of reducing the amount of information to be saved to an external memory, etc.
摘要翻译：从行为综合获得的活动信息，并且显示了在行为级别描述中描述的变量具有有效值的时期，用于逻辑合成阶段，布局和路由阶段，调试阶段，电路信息写入阶段的处理可重新配置的设备等，以便使用要分配给行为级别描述中描述的变量的存储元件，并且实现最小化数据路径等的优化。另外，在调试器和用于写入电路信息的写入装置中，上述活动信息用于执行不显示无效变量的任务，减少要保存到外部存储器的信息量的任务等。

6. 发明申请

US20090249262A1 BEHAVIORAL SYNTHESIS DEVICE, BEHAVIORAL SYNTHESIS METHOD, AND COMPUTER PROGRAM PRODUCT 有权
标题翻译：行为综合设备，行为综合方法和计算机程序产品
公开(公告)号：US20090249262A1
公开(公告)日：2009-10-01
申请号：US12409856
申请日：2009-03-24
申请人： Yoshinosuke Kato , Takao Toi , Noritsugu Nakamura , Toru Awashima , Hirokazu Kami
发明人： Yoshinosuke Kato , Takao Toi , Noritsugu Nakamura , Toru Awashima , Hirokazu Kami
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A behavioral synthesis device include a profile unit that implements an electronic circuit at a reconfigurable hardware based on a first register transfer level description generated by a behavioral synthesis unit, actuates the implemented electronic circuit, and causes the electric circuit to output profile information from the actuated electronic circuit; and an optimizer that generates optimization information for optimizing a behavioral synthesis carried out by the behavioral synthesis unit based on the profile information that the profile unit causes the electric circuit to output, and outputs the generated optimization information to the behavioral synthesis unit, wherein the behavioral synthesis unit acquires a first behavioral level description, and subjects the acquired first behavioral level description to behavioral synthesis and generates the second register transfer level description based on the optimization information outputted by the optimizer.
摘要翻译：行为综合装置包括：简档单元，其基于由行为合成单元生成的第一寄存器传送级别描述，在可重新配置的硬件上实现电子电路，致动所实现的电子电路，并且使电路从致动的电路输出简档信息电子电路; 以及优化器，其基于所述简档单元使所述电路输出的所述简档信息，生成用于优化由所述行为综合单元执行的行为综合的优化信息，并将所生成的优化信息输出到所述行为综合单元，其中，合成单元获取第一行为级别描述，并且将所获取的第一行为级别描述进行行为综合，并且基于优化器输出的优化信息生成第二寄存器传送级别描述。

7. 发明授权

US08516414B2 Behavioral synthesis device, behavioral synthesis method, and computer program product 有权
标题翻译：行为综合装置，行为综合方法和计算机程序产品
公开(公告)号：US08516414B2
公开(公告)日：2013-08-20
申请号：US12409856
申请日：2009-03-24
申请人： Yoshinosuke Kato , Takao Toi , Noritsugu Nakamura , Toru Awashima , Hirokazu Kami
发明人： Yoshinosuke Kato , Takao Toi , Noritsugu Nakamura , Toru Awashima , Hirokazu Kami
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A behavioral synthesis device include a profile unit that implements an electronic circuit at a reconfigurable hardware based on a first register transfer level description generated by a behavioral synthesis unit, actuates the implemented electronic circuit, and causes the electric circuit to output profile information from the actuated electronic circuit; and an optimizer that generates optimization information for optimizing a behavioral synthesis carried out by the behavioral synthesis unit based on the profile information that the profile unit causes the electric circuit to output, and outputs the generated optimization information to the behavioral synthesis unit, wherein the behavioral synthesis unit acquires a first behavioral level description, and subjects the acquired first behavioral level description to behavioral synthesis and generates the second register transfer level description based on the optimization information outputted by the optimizer.
摘要翻译：行为综合装置包括：简档单元，其基于由行为合成单元生成的第一寄存器传送级别描述，在可重新配置的硬件上实现电子电路，致动所实现的电子电路，并且使电路从致动的电路输出简档信息电子电路; 以及优化器，其基于所述简档单元使所述电路输出的所述简档信息，生成用于优化由所述行为综合单元执行的行为综合的优化信息，并将所生成的优化信息输出到所述行为综合单元，其中，合成单元获取第一行为级别描述，并且将所获取的第一行为级别描述进行行为综合，并且基于优化器输出的优化信息生成第二寄存器传送级别描述。

8. 发明授权

US06344992B1 SRAM operating with a reduced power dissipation 有权
标题翻译： SRAM的功耗降低
公开(公告)号：US06344992B1
公开(公告)日：2002-02-05
申请号：US09721489
申请日：2000-11-22
申请人： Noritsugu Nakamura
发明人： Noritsugu Nakamura
IPC分类号： G11C1100
CPC分类号： G11C11/412 , G11C5/147 , G11C11/413
摘要： A SRAM has a plurality of four-transistor/no-load memory cells each operating in a precharge mode for maintaining stored data based on off-leak currents of MOSFETs. The SRAM has a reference voltage generator, an impedance converter, a plurality of word line drivers, and a plurality of word lines each extending along a row of the memory cells.
摘要翻译： SRAM具有多个四晶体管/空载存储单元，每个在预充电模式下工作，用于基于MOSFET的漏电流来维持存储的数据。 SRAM具有参考电压发生器，阻抗转换器，多个字线驱动器以及沿着存储单元的一行延伸的多个字线。

9. 发明授权

US07633052B2 Impact detection system with three or more optical fiber sensors 有权
标题翻译：具有三个或更多光纤传感器的冲击检测系统
公开(公告)号：US07633052B2
公开(公告)日：2009-12-15
申请号：US11987531
申请日：2007-11-30
申请人： Noritsugu Nakamura , Toshimichi Ogisu , Nobuo Takeda
发明人： Noritsugu Nakamura , Toshimichi Ogisu , Nobuo Takeda
IPC分类号： G01J1/04 , G01J1/42 , G01J5/08
CPC分类号： G01M11/083
摘要： Disclosed an impact detection system including: three or more optical fiber sensors disposed respectively in different positions, the sensors not being in alignment with one another, in which the sensors each includes a core portion to have a grating portion formed therein, the grating portion has a plurality of gratings; light source; two or more optical filters having different pass bands to one another to an output light of one of the optical fiber sensors; and an arithmetic processing apparatus to perform arithmetic processing of output values of the three or more optical fiber sensors through the optical filters so as to specify a position on the subject where an impact is loaded, the output values being obtained when the impact is loaded on the subject.
摘要翻译：公开了一种冲击检测系统，包括：分别设置在不同位置的三个或更多个光纤传感器，所述传感器彼此不对准，其中所述传感器各自包括具有形成在其中的光栅部分的芯部分，所述光栅部分具有多个光栅; 光源; 两个或更多个光滤波器彼此具有彼此不同的通带至光纤传感器之一的输出光; 以及算术处理装置，通过光学滤波器对三个以上的光纤传感器的输出值进行运算处理，以指定对象上的冲击加载位置，当冲击加载时得到的输出值主题。

10. 发明申请

US20080129982A1 Impact detection system 有权
标题翻译：冲击检测系统
公开(公告)号：US20080129982A1
公开(公告)日：2008-06-05
申请号：US11987531
申请日：2007-11-30
申请人： Noritsugu Nakamura , Toshimichi Ogisu , Nobuo Takeda
发明人： Noritsugu Nakamura , Toshimichi Ogisu , Nobuo Takeda
IPC分类号： G01N21/00
CPC分类号： G01M11/083
摘要： Disclosed an impact detection system including: three or more optical fiber sensors disposed respectively in different positions, the sensors not being in alignment with one another, in which the sensors each includes a core portion to have a grating portion formed therein, the grating portion has a plurality of gratings; light source; two or more optical filters having different pass bands to one another to an output light of one of the optical fiber sensors; and an arithmetic processing apparatus to perform arithmetic processing of output values of the three or more optical fiber sensors through the optical filters so as to specify a position on the subject where an impact is loaded, the output values being obtained when the impact is loaded on the subject.
摘要翻译：公开了一种冲击检测系统，包括：分别设置在不同位置的三个或更多个光纤传感器，所述传感器彼此不对准，其中所述传感器各自包括具有形成在其中的光栅部分的芯部分，所述光栅部分具有多个光栅; 光源; 两个或更多个光滤波器彼此具有彼此不同的通带至光纤传感器之一的输出光; 以及算术处理装置，通过光学滤波器对三个以上的光纤传感器的输出值进行运算处理，以指定对象上的冲击加载位置，当冲击加载时得到的输出值主题。

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