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1. 发明授权

US4992845A Semiconductor integrated circuit device having input/output buffer cells each comprising a plurality of transistor regions arranged in a single line 失效
标题翻译：具有输入/输出缓冲单元的半导体集成电路器件，每个单元包括排列成一行的多个晶体管区域
公开(公告)号：US4992845A
公开(公告)日：1991-02-12
申请号：US294020
申请日：1989-01-06
申请人： Takahiko Arakawa , Kazuhiro Sakashita , Satoru Kishida , Toshiaki Hanibuchi , Ichiro Tomioka , Masahiro Ueda , Yoshihiro Okuno
发明人： Takahiko Arakawa , Kazuhiro Sakashita , Satoru Kishida , Toshiaki Hanibuchi , Ichiro Tomioka , Masahiro Ueda , Yoshihiro Okuno
IPC分类号： H01L21/82 , H01L27/118
CPC分类号： H01L27/11898
摘要： An internal logic gate portion (3) is provided in the central portion of a semiconductor chip (1), input/output buffers (4) are provided to surround the internal logic gate portion (3), and bonding pads (2) are provided in the peripheral portions of the semiconductor chip (1) corresponding to input/output buffer cells (5) in the input/output buffer. Each of the input/output buffer cells (5) comprises an output P-MOS portion (6), an output N-MOS portion (7), an input/logic P-MOS portion (8) and an input/logic N-MOS portion (9), which are respectively arranged in a single line in the direction from the bonding pads (2) to the internal logic gate portion (3). In the above described structure, the size of each of the input/output buffer cells (5) in the pad arranging direction of the bonding pads (2) is decreased, so that the number of input/output pins can be increased according to the decreased use of space in the pad arranging direction required by each input/output buffer cell (5).
摘要翻译：在半导体芯片（1）的中央部分设置有内部逻辑门部（3），设置有用于包围内部逻辑门部（3）的输入/输出缓冲器（4），并且提供接合焊盘（2）在对应于输入/输出缓冲器中的输入/输出缓冲单元（5）的半导体芯片（1）的外围部分中。每个输入/输出缓冲器单元（5）包括输出P-MOS部分（6），输出N-MOS部分（7），输入/逻辑P-MOS部分（8）和输入/ MOS部分（9），它们在从接合焊盘（2）到内部逻辑门部分（3）的方向上分别布置成单行。在上述结构中，键合焊盘（2）的焊盘布置方向上的输入/输出缓冲单元（5）中的每一个的尺寸减小，从而可以根据减少每个输入/输出缓冲单元（5）所需的排列方向的空间的使用。

2. 发明授权

US5323070A Output buffer circuit having output bouncing controlled circuits 失效
标题翻译：输出缓冲电路，具有输出弹跳控制电路
公开(公告)号：US5323070A
公开(公告)日：1994-06-21
申请号：US821941
申请日：1992-01-17
申请人： Masahiro Ueda , Ichiro Tomioka
发明人： Masahiro Ueda , Ichiro Tomioka
IPC分类号： H03K17/16 , H03K17/687 , H03K19/003 , H03K19/017 , H03K19/0175 , H03K19/0944 , H03K19/092
CPC分类号： H03K19/01721 , H03K19/00361 , H03K19/09448
摘要： A first output buffer having a large current driving capability and a second output buffer having a small current driving capability are connected in parallel between an input terminal and an external lead. The first and second output buffers each includes two CMOS inverters connected in series between the input terminal and the external lead. The P-channel and N-channel MOSFETs of the two CMOS inverters in the second output buffer have gate widths smaller than each of the P-channel and N-channel MOSFETs, respectively, of the two CMOS inverters in the first output buffer. Also disclosed is an output buffer having P-channel and N-channel MOSFETs arranged as a CMOS inverter, but with a base of a first bipolar transistor connected to a source of the N-channel MOSFET. An emitter of the first bipolar transistor is connected to ground and its collector is connected to an output of the output buffer. A base of a second bipolar transistor is connected to an output of the CMOS inverter and its emitter is connected to the output of the output buffer. An input of the output buffer is supplied to an input of the CMOS inverter. Another transistor is connected between the output of the output buffer and ground and is responsive to the input of the output buffer.
摘要翻译：具有大电流驱动能力的第一输出缓冲器和具有小电流驱动能力的第二输出缓冲器并联连接在输入端和外部引线之间。第一和第二输出缓冲器各自包括串联连接在输入端和外部引线之间的两个CMOS反相器。第二输出缓冲器中的两个CMOS反相器的P沟道和N沟道MOSFET分别具有比第一输出缓冲器中的两个CMOS反相器的P沟道和N沟道MOSFET中的每一个的栅极宽度小的栅极宽度。还公开了具有布置为CMOS反相器但具有连接到N沟道MOSFET的源极的第一双极晶体管的基极的P沟道和N沟道MOSFET的输出缓冲器。第一双极晶体管的发射极连接到地，其集电极连接到输出缓冲器的输出端。第二双极晶体管的基极连接到CMOS反相器的输出，其发射极连接到输出缓冲器的输出端。输出缓冲器的输入被提供给CMOS反相器的输入。另一个晶体管连接在输出缓冲器的输出和地之间，并响应于输出缓冲器的输入。

3. 发明授权

US4916385A Inverter circuit 失效
标题翻译：逆变电路
公开(公告)号：US4916385A
公开(公告)日：1990-04-10
申请号：US262302
申请日：1988-10-25
申请人： Ichiro Tomioka , Masahiro Ueda , Takahiko Arakawa , Toshiaki Hanibuchi , Yoshihiro Okuno
发明人： Ichiro Tomioka , Masahiro Ueda , Takahiko Arakawa , Toshiaki Hanibuchi , Yoshihiro Okuno
IPC分类号： G01R19/165 , G01R31/316 , G01R31/317 , G01R31/319 , H03K17/00 , H03K17/16 , H03K19/003 , H03K19/0948
CPC分类号： H03K19/00361 , G01R31/316 , G01R31/31905
摘要： An inverter circuit (I.sub.3) is disclosed which includes a P-channel MOSFET (3) and a N-channel MOSFET (4) connected in series between a power supply (V.sub.DD) and a ground (GND). The inverter circuit further includes a P-channel MOSFET (5) and a N-channel MOSFET (6) connected in parallel between the gates of the FETs (3) and (4). The FETs (3) and (4) have their gates connected to receive testing mode signals (T.sub.E). In a testing mode operation, the FET (6) is rendered conductive to allow an input signal to be applied to the gate of the FET (4) through the FET (6). The FET (4), having an on-resistance lower than the FET (3), is driven into conduction in response to the output signal applied through the FET (6), thereby providing a slowly rising output signal. The slow rising output signal is free from undershoot or ringing.
摘要翻译：公开了一种逆变器电路（I3），其包括串联连接在电源（VDD）和地（GND）之间的P沟道MOSFET（3）和N沟道MOSFET（4）。逆变器电路还包括在FET（3）和（4）的栅极之间并联连接的P沟道MOSFET（5）和N沟道MOSFET（6）。 FET（3）和（4）的栅极连接以接收测试模式信号（TE）。在测试模式操作中，使FET（6）导通以允许通过FET（6）将输入信号施加到FET（4）的栅极。响应于通过FET（6）施加的输出信号，具有低于FET（3）的导通电阻的FET（4）被驱动成导通，从而提供缓慢上升的输出信号。缓慢上升的输出信号没有下冲或振铃。

4. 发明授权

US4864579A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US4864579A
公开(公告)日：1989-09-05
申请号：US81094
申请日：1987-08-03
申请人： Satoru Kishida , Kazuhiro Sakashita , Ichiro Tomioka
发明人： Satoru Kishida , Kazuhiro Sakashita , Ichiro Tomioka
IPC分类号： G06F11/16 , G01R31/3185 , G06F11/22
CPC分类号： G01R31/318541
摘要： A semiconductor integrated circuit device for transmitting data between a plurality of circuit blocks at least one thereof including a sequential circuit and enabling the circuit blocks to test in a scan testing type which has a plurality of scan registers provided between the plurality of circuit blocks corresponding to the number of bits of data to be transmitted for outputting the output data of the previous stage circuit block as it is at ordinary operating time and for holding and outputting the output data of the previous circuit block or test data for scan test synchronously with an external clock at testing time so that the circuits are connected by a shift register pass in such a manner that the entirety has one shaft register function, and a latch circuit provided at its data input terminal to the data output terminal of the corresponding scan register for outputtting the output data of the corresponding scan register as it is to the circuit block of next stage at ordinary operation time and holding the output data of the corresponding scan register before the scanning operation in a scan mode at testing time to continuously apply the data to the circuit block of next stage and holding and outputting the output data of the corresponding scan register in a test mode synchronously with the external clock, test data setting means for setting serial data of test from the exterior of the circuit device to each of the scan registers, test result outputting means for sequentially outputting the data of each scan register as serial data out of the circuit device, and operation switching means for switching the ordinary operation and the testing operation and switching the scan mode and the test mode, thereby enabling the semiconductor integrated circuit device to be readily subjected to a scan test together with circuit blocks including asynchronous sequential circuits.
摘要翻译：一种半导体集成电路装置，用于在多个电路块之间传输数据，其中至少一个电路块包括时序电路，并使电路块能够以扫描测试类型进行测试，该扫描测试类型具有多个扫描寄存器，该扫描寄存器设置在与要发送的数据的比特数，用于在正常操作时间输出前一级电路块的输出数据，并且用于保持和输出前一个电路块的输出数据或与外部的同步的扫描测试的测试数据时钟，使得电路通过移位寄存器通过连接，使得整体具有一个轴寄存器功能，以及锁存电路，在其数据输入端提供到相应扫描寄存器的数据输出端，用于输出相应的扫描寄存器的输出数据与普通操作下一级的电路块相同并且在测试时间内以扫描模式扫描操作之前保持相应扫描寄存器的输出数据，以将数据连续地施加到下一级的电路块，并在测试中保存和输出相应的扫描寄存器的输出数据与外部时钟同步的模式的测试数据设置装置，用于将测试的串行数据从电路设备的外部设置到每个扫描寄存器;测试结果输出装置，用于将每个扫描寄存器的数据顺序地输出为电路装置和用于切换普通操作和测试操作以及切换扫描模式和测试模式的操作切换装置，从而使得半导体集成电路器件能够容易地与包括异步时序电路的电路块一起进行扫描测试。

5. 发明授权

US4995039A Circuit for transparent scan path testing of integrated circuit devices 失效
标题翻译：集成电路器件透明扫描路径测试电路
公开(公告)号：US4995039A
公开(公告)日：1991-02-19
申请号：US247289
申请日：1988-09-22
申请人： Kazuhiro Sakashita , Ichiro Tomioka , Takeshi Hashizume
发明人： Kazuhiro Sakashita , Ichiro Tomioka , Takeshi Hashizume
IPC分类号： G01R31/28 , G01R31/3185 , G06F11/22 , H01L21/66
CPC分类号： G01R31/318552
摘要： In a circuit for testing integrated circuit devices, scan registers (8.about.16) and data selecting circuits (20-28) are connected between a plurality of circuit blocks (29.about.31) in correspondence with the number of bits of the data, with the scan registers connected to each other by a shift register path so as to have a function of one shift register as a whole. A register selecting circuit (20.about.28) is connected to a clock input terminal (T1, T2) of the scan register. The scan registers other than those corresponding to the logic circuit block to be tested are selected by the register selecting circuit. Consequently, clocks for scanning scan registers other than those provided before and after the required circuit block are eliminated, enabling reduction of time required for scan test.
摘要翻译：在用于测试集成电路器件的电路中，扫描寄存器（8差分16）和数据选择电路（20-28）根据数据的位数连接在多个电路块（29差分31）之间，扫描寄存器通过移位寄存器路径彼此连接，从而整体上具有一个移位寄存器的功能。寄存器选择电路（20差分28）连接到扫描寄存器的时钟输入端（T1，T2）。除了与要测试的逻辑电路块相对应的扫描寄存器之外的扫描寄存器由寄存器选择电路选择。因此，消除了除所需电路块之前和之后提供的扫描寄存器之外的扫描寄存器的时钟，从而可以减少扫描测试所需的时间。

6. 发明授权

US4780666A Semiconductor integrated circuit device having rest function 失效
标题翻译：具有休息功能的半导体集成电路器件
公开(公告)号：US4780666A
公开(公告)日：1988-10-25
申请号：US81256
申请日：1987-08-03
申请人： Kazuhiro Sakashita , Satoru Kishida , Toshiaki Hanibuchi , Ichiro Tomioka , Takahiko Arakawa
发明人： Kazuhiro Sakashita , Satoru Kishida , Toshiaki Hanibuchi , Ichiro Tomioka , Takahiko Arakawa
IPC分类号： G01R31/28 , G01R31/3185 , G06F11/22 , G11C19/28 , G01R15/12
CPC分类号： G01R31/318541
摘要： A semiconductor integrated circuit device includes a plurality of latch circuits which are provided between adjacent circuit blocks. Each latch circuit functions to transfer output data from a preceding circuit block directly to a subsequent circuit block during a normal operation of the circuit device, to hold the output data until a scanning of associated scan register and supply them to the subsequent circuit block in a scan mode of a test operation and to hole the output data while outputting them in synchronism with an external clock in a test mode of the test operation.
摘要翻译：半导体集成电路器件包括设置在相邻电路块之间的多个锁存电路。每个锁存电路用于在电路设备的正常操作期间将来自前一电路块的输出数据直接传送到后续电路块，以保持输出数据直到扫描相关扫描寄存器并将其提供给后续电路块扫描模式，并且在测试操作的测试模式中与外部时钟同步地输出输出数据。

7. 发明授权

US5404035A Multi-voltage-level master-slice integrated circuit 失效
标题翻译：多电压级主片集成电路
公开(公告)号：US5404035A
公开(公告)日：1995-04-04
申请号：US75211
申请日：1993-06-10
申请人： Hideki Taniguchi , Ichiro Tomioka , Kunihiko Sanada , Masatomi Okabe
发明人： Hideki Taniguchi , Ichiro Tomioka , Kunihiko Sanada , Masatomi Okabe
IPC分类号： H01L21/82 , H01L27/118 , H01L27/10 , H01L27/02
CPC分类号： H01L27/11898 , H01L2224/05554
摘要： A master-slice semiconductor integrated circuit device includes a substrate for an input/output circuit section, which is segmented into a plurality of segments during a master processing step. In a slice processing step, slice cells are formed, using different substrate segments. Input/output circuits are formed by respective slice cells so that desired different supply voltages can be applied to input/output circuits on different substrate segments.
摘要翻译：主切片半导体集成电路器件包括用于输入/输出电路部分的衬底，其在主处理步骤期间被分割成多个段。在切片处理步骤中，使用不同的基底片段形成切片单元。输入/输出电路由相应的切片单元形成，从而可以将期望的不同电源电压施加到不同基片段上的输入/输出电路。

8. 发明授权

US5148514A Neural network integrated circuit device having self-organizing function 失效
标题翻译：具有自组织功能的神经网络集成电路器件
公开(公告)号：US5148514A
公开(公告)日：1992-09-15
申请号：US515476
申请日：1990-04-24
申请人： Yutaka Arima , Ichiro Tomioka , Toshiaki Hanibuchi
发明人： Yutaka Arima , Ichiro Tomioka , Toshiaki Hanibuchi
IPC分类号： G06N3/063
CPC分类号： G06N3/063
摘要： An extension directed integrated circuit device having a learning function on a Boltzmann model, includes a plurality of synapse representing units arrayed in a matrix to form a rectangle including a first and second triangles on a semiconductor chip, a plurality of neuron representing units and a plurality of educator signal control circuits which are arranged along first and second sides of the rectangle, and a plurality of buffer circuits arranged along third and fourth sides of the rectangle. The first side is opposite to the third side, and the second side is opposite to the fourth side. Axon signal transfer lines and dendrite signal lines are so arranged that the neuron representing units are full-connected in each of the first right triangle the second right triangle. Alternatively, axon signal lines and dendrite signal ines are arranged in parallel with rows and columns of the synapse representing unit matrix, so that the neuron representing units are full-connected in the rectangle. Each synapse representing unit is connected to a pair of axon signal transfer lines and a pair of dendrite signal transfer lines.
摘要翻译：具有Boltzmann模型学习功能的延伸定向集成电路装置包括多个突触，其表示以矩阵排列的单元，以形成包括半导体芯片上的第一和第二三角形的矩形，多个神经元表示单元和多个沿矩形的第一和第二侧布置的教育者信号控制电路以及沿矩形的第三和第四侧布置的多个缓冲电路。第一面与第三面相反，第二面与第四面相反。轴突信号传输线和枝晶信号线被布置成使得表示单元的神经元在第二直角三角形的第一直角三角形的每一个中是全连接的。或者，轴突信号线和枝晶信号与突触表示单位矩阵的行和列平行布置，使得表示单元的神经元表示在矩形中。每个突触代表单元连接到一对轴突信号传输线和一对枝晶信号传输线。

9. 发明授权

US5483479A Associative storage memory 失效
标题翻译：关联存储器
公开(公告)号：US5483479A
公开(公告)日：1996-01-09
申请号：US50850
申请日：1993-04-21
申请人： Nobuyuki Osawa , Ichiro Tomioka , Mitsuhiro Deguchi
发明人： Nobuyuki Osawa , Ichiro Tomioka , Mitsuhiro Deguchi
IPC分类号： G11C15/00 , G11C15/04
CPC分类号： G11C15/04
摘要： A memory cell for an associative storage memory device includes a transmission gate which is rendered conductive or non-conductive in response to a potential on a word line for transferring information between an information hold circuit and a bit line or between the information hold circuit and an inverted bit line. Match line are precharged to ground and supply potentials, respectively, and, thereafter, a retrieval circuit compares information on the bit line or inverted bit line with information held in the information hold circuit and produces a control signal to control the potentials on the match lines in accordance with the result of comparison. After the match lines are precharged, a gating circuit is rendered conductive in response to potentials on output control line and inverted output control line to thereby couple the control signal to the match lines.
摘要翻译：用于关联存储存储器件的存储器单元包括传输门，其响应于字线上的电位而被导通或不导通，用于在信息保持电路和位线之间或在信息保持电路和信号保持电路之间传送信息反转位线。匹配线分别被预充电到接地和供电电位，之后，检索电路将有关位线或反向位线的信息与保存在信息保持电路中的信息进行比较，并产生控制信号以控制匹配线上的电位按照比较结果。在匹配线被预充电之后，门控电路响应于输出控制线和反相输出控制线上的电位而导通，从而将控制信号耦合到匹配线。

10. 发明授权

US5293457A Neural network integrated circuit device having self-organizing function 失效
标题翻译：具有自组织功能的神经网络集成电路器件
公开(公告)号：US5293457A
公开(公告)日：1994-03-08
申请号：US877514
申请日：1992-05-01
申请人： Yutaka Arima , Ichiro Tomioka , Toshiaki Hanibuchi
发明人： Yutaka Arima , Ichiro Tomioka , Toshiaki Hanibuchi
IPC分类号： G06G7/60 , G06F15/18 , G06N3/063 , G06N99/00 , H01L21/822 , H01L27/04 , G06F7/00
CPC分类号： G06N3/063
摘要： An extension directed integrated circuit device having a learning function on a Boltzmann model, includes a plurality of synapse representing units arrayed in a matrix, a plurality of neuron representing units, a plurality of educator signal control circuits, and a plurality of buffer circuits. Each synapse representing unit is connected to a pair of axon signal transfer lines and a pair of dendrite signal transfer lines. Each synapse representing unit includes a learning control circuit which derives synapse load change value data in accordance with predetermined learning rules in response to a first axon signal Si and a second axon signal Sj, a synapse load representing circuit which corrects a synapse load in response to the synapse load change valued data and holds the corrected synapse load value Wij, a first synapse coupling operating circuit which derives a current signal indicating a product Wij.multidot.Si from the synapse load Wij and the first axon signal Si and transfers the same to a first dendrite signal line, and a second product signal indicating a product Wij.multidot.Sj from the synapse load Wij and the second axon signal Sj and transfers the same onto a second dendrite signal line.
摘要翻译：具有Boltzmann模型学习功能的延伸定向集成电路器件包括表示以矩阵排列的单元的多个突触，多个神经元表示单元，多个教育者信号控制电路和多个缓冲电路。每个突触代表单元连接到一对轴突信号传输线和一对枝晶信号传输线。每个突触表示单元包括学习控制电路，该学习控制电路响应于第一轴突信号Si和第二轴突信号Sj，根据预定的学习规则导出突触负荷变化值数据，突变负载表示电路响应于突触负荷改变数值数据并保持校正的突触负载值Wij，第一突触耦合操作电路从突触负载Wij和第一轴突信号Si导出指示产品Wij * Si的电流信号，并将其转移到第一枝晶信号线和第二产品信号，其从突触载荷Wij和第二轴突信号Sj指示乘积Wij * Sj，并将其传送到第二枝晶信号线。

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