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1. 发明授权

US4992845A Semiconductor integrated circuit device having input/output buffer cells each comprising a plurality of transistor regions arranged in a single line 失效
标题翻译：具有输入/输出缓冲单元的半导体集成电路器件，每个单元包括排列成一行的多个晶体管区域
公开(公告)号：US4992845A
公开(公告)日：1991-02-12
申请号：US294020
申请日：1989-01-06
申请人： Takahiko Arakawa , Kazuhiro Sakashita , Satoru Kishida , Toshiaki Hanibuchi , Ichiro Tomioka , Masahiro Ueda , Yoshihiro Okuno
发明人： Takahiko Arakawa , Kazuhiro Sakashita , Satoru Kishida , Toshiaki Hanibuchi , Ichiro Tomioka , Masahiro Ueda , Yoshihiro Okuno
IPC分类号： H01L21/82 , H01L27/118
CPC分类号： H01L27/11898
摘要： An internal logic gate portion (3) is provided in the central portion of a semiconductor chip (1), input/output buffers (4) are provided to surround the internal logic gate portion (3), and bonding pads (2) are provided in the peripheral portions of the semiconductor chip (1) corresponding to input/output buffer cells (5) in the input/output buffer. Each of the input/output buffer cells (5) comprises an output P-MOS portion (6), an output N-MOS portion (7), an input/logic P-MOS portion (8) and an input/logic N-MOS portion (9), which are respectively arranged in a single line in the direction from the bonding pads (2) to the internal logic gate portion (3). In the above described structure, the size of each of the input/output buffer cells (5) in the pad arranging direction of the bonding pads (2) is decreased, so that the number of input/output pins can be increased according to the decreased use of space in the pad arranging direction required by each input/output buffer cell (5).
摘要翻译：在半导体芯片（1）的中央部分设置有内部逻辑门部（3），设置有用于包围内部逻辑门部（3）的输入/输出缓冲器（4），并且提供接合焊盘（2）在对应于输入/输出缓冲器中的输入/输出缓冲单元（5）的半导体芯片（1）的外围部分中。每个输入/输出缓冲器单元（5）包括输出P-MOS部分（6），输出N-MOS部分（7），输入/逻辑P-MOS部分（8）和输入/ MOS部分（9），它们在从接合焊盘（2）到内部逻辑门部分（3）的方向上分别布置成单行。在上述结构中，键合焊盘（2）的焊盘布置方向上的输入/输出缓冲单元（5）中的每一个的尺寸减小，从而可以根据减少每个输入/输出缓冲单元（5）所需的排列方向的空间的使用。

2. 发明授权

US4916385A Inverter circuit 失效
标题翻译：逆变电路
公开(公告)号：US4916385A
公开(公告)日：1990-04-10
申请号：US262302
申请日：1988-10-25
申请人： Ichiro Tomioka , Masahiro Ueda , Takahiko Arakawa , Toshiaki Hanibuchi , Yoshihiro Okuno
发明人： Ichiro Tomioka , Masahiro Ueda , Takahiko Arakawa , Toshiaki Hanibuchi , Yoshihiro Okuno
IPC分类号： G01R19/165 , G01R31/316 , G01R31/317 , G01R31/319 , H03K17/00 , H03K17/16 , H03K19/003 , H03K19/0948
CPC分类号： H03K19/00361 , G01R31/316 , G01R31/31905
摘要： An inverter circuit (I.sub.3) is disclosed which includes a P-channel MOSFET (3) and a N-channel MOSFET (4) connected in series between a power supply (V.sub.DD) and a ground (GND). The inverter circuit further includes a P-channel MOSFET (5) and a N-channel MOSFET (6) connected in parallel between the gates of the FETs (3) and (4). The FETs (3) and (4) have their gates connected to receive testing mode signals (T.sub.E). In a testing mode operation, the FET (6) is rendered conductive to allow an input signal to be applied to the gate of the FET (4) through the FET (6). The FET (4), having an on-resistance lower than the FET (3), is driven into conduction in response to the output signal applied through the FET (6), thereby providing a slowly rising output signal. The slow rising output signal is free from undershoot or ringing.
摘要翻译：公开了一种逆变器电路（I3），其包括串联连接在电源（VDD）和地（GND）之间的P沟道MOSFET（3）和N沟道MOSFET（4）。逆变器电路还包括在FET（3）和（4）的栅极之间并联连接的P沟道MOSFET（5）和N沟道MOSFET（6）。 FET（3）和（4）的栅极连接以接收测试模式信号（TE）。在测试模式操作中，使FET（6）导通以允许通过FET（6）将输入信号施加到FET（4）的栅极。响应于通过FET（6）施加的输出信号，具有低于FET（3）的导通电阻的FET（4）被驱动成导通，从而提供缓慢上升的输出信号。缓慢上升的输出信号没有下冲或振铃。

3. 发明授权

US4780666A Semiconductor integrated circuit device having rest function 失效
标题翻译：具有休息功能的半导体集成电路器件
公开(公告)号：US4780666A
公开(公告)日：1988-10-25
申请号：US81256
申请日：1987-08-03
申请人： Kazuhiro Sakashita , Satoru Kishida , Toshiaki Hanibuchi , Ichiro Tomioka , Takahiko Arakawa
发明人： Kazuhiro Sakashita , Satoru Kishida , Toshiaki Hanibuchi , Ichiro Tomioka , Takahiko Arakawa
IPC分类号： G01R31/28 , G01R31/3185 , G06F11/22 , G11C19/28 , G01R15/12
CPC分类号： G01R31/318541
摘要： A semiconductor integrated circuit device includes a plurality of latch circuits which are provided between adjacent circuit blocks. Each latch circuit functions to transfer output data from a preceding circuit block directly to a subsequent circuit block during a normal operation of the circuit device, to hold the output data until a scanning of associated scan register and supply them to the subsequent circuit block in a scan mode of a test operation and to hole the output data while outputting them in synchronism with an external clock in a test mode of the test operation.
摘要翻译：半导体集成电路器件包括设置在相邻电路块之间的多个锁存电路。每个锁存电路用于在电路设备的正常操作期间将来自前一电路块的输出数据直接传送到后续电路块，以保持输出数据直到扫描相关扫描寄存器并将其提供给后续电路块扫描模式，并且在测试操作的测试模式中与外部时钟同步地输出输出数据。

4. 发明授权

US4870345A Semiconductor intergrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US4870345A
公开(公告)日：1989-09-26
申请号：US81095
申请日：1987-08-03
申请人： Ichiro Tomioka , Kazuhiro Sakashita , Satoru Kishida , Toshiaki Hanibuchi , Takahiko Arakawa
发明人： Ichiro Tomioka , Kazuhiro Sakashita , Satoru Kishida , Toshiaki Hanibuchi , Takahiko Arakawa
IPC分类号： G01R31/3185
CPC分类号： G01R31/318536
摘要： A semiconductor integrated circuit includes cascaded asynchronous sequential logic circuits. Scanning shift registers are provided between the asynchronous sequential circuits to permit test data to be applied to the inputs of the circuits and to latch and shift out output data provided by the circuits in response to the test data. Additional gating circuitry is provided between the scanning shift registers and the inputs of the asynchronous sequential circuits to prevent new data latched into the scanning shift register from causing the asynchronous sequential circuit connected to the scanning shift register output from changing state during testing. This same additional circuitry may be used to provide pulses of controlled width and/or timing to asynchronous sequential circuit inputs in response to externally generated gating control signals.
摘要翻译：半导体集成电路包括级联异步顺序逻辑电路。在异步时序电路之间提供扫描移位寄存器，以允许将测试数据应用于电路的输入，并根据测试数据锁存和移出由电路提供的输出数据。在扫描移位寄存器和异步顺序电路的输入之间提供附加的选通电路，以防止锁存在扫描移位寄存器中的新数据使测试期间连接到扫描移位寄存器输出的异步时序电路变化。可以使用相同的附加电路来响应于外部产生的门控控制信号来提供受控宽度和/或定时到异步顺序电路输入的脉冲。

5. 发明授权

US4856002A Semiconductor integrated circuit apparatus 失效
标题翻译：半导体集成电路装置
公开(公告)号：US4856002A
公开(公告)日：1989-08-08
申请号：US062439
申请日：1987-06-12
申请人： Kazuhiro Sakashita , Satoru Kishida , Toshiaki Hanibuchi , Ichiro Tomioka , Takahiko Arakawa
发明人： Kazuhiro Sakashita , Satoru Kishida , Toshiaki Hanibuchi , Ichiro Tomioka , Takahiko Arakawa
IPC分类号： G01R31/28 , G01R31/3185 , G06F11/22
CPC分类号： G01R31/31816 , G01R31/318533
摘要： A test circuit of a semiconductor integrated circuit apparatus comprising a latch circuit connected to an output terminal of a scan register for holding output data of the scan register stored before scanning in a scan mode during the test operation.
摘要翻译：一种半导体集成电路装置的测试电路，包括连接到扫描寄存器的输出端的锁存电路，用于在测试操作期间以扫描模式保持在扫描之前存储的扫描寄存器的输出数据。

6. 发明授权

US5471095A Semiconductor integrated circuit device and method of fabricating same 失效
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US5471095A
公开(公告)日：1995-11-28
申请号：US237309
申请日：1994-05-03
申请人： Isamu Kaminaga , Shuuichi Matsue , Takahiko Arakawa , Shuuichi Katoh , Masahiro Ueda
发明人： Isamu Kaminaga , Shuuichi Matsue , Takahiko Arakawa , Shuuichi Katoh , Masahiro Ueda
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/522 , H01L23/528 , H01L23/48 , H01L29/62
CPC分类号： H01L23/5222 , H01L23/5283 , H01L2924/0002
摘要： There is disclosed a semiconductor integrated circuit device including an element-to-element line (10A) of a quadrangular (rectangular) configuration in cross section having horizontal upper and lower surfaces, with its lower surface corners on the side of a semiconductor substrate (1) chamfered on the slant. This increases the horizontal distance between adjacent lines and decreases the height of the line, permitting the adjacent line-to-line parasitic capacitance to be lower than that of the prior art line of a quadrangular configuration in cross section under the same height and line-to-line horizontal distance conditions. The line-to-substrate parasitic capacitance is also permitted to be lower for similar reasons. The semiconductor integrated circuit device is thus provided in which the parasitic capacitances generated by forming lines are minimized.
摘要翻译：公开了一种半导体集成电路器件，其包括具有水平上表面和下表面的横截面的四边形（矩形）构造的元件间元件线（10A），其下表面拐角位于半导体衬底（1））在斜面上倒角。这增加了相邻线之间的水平距离并且降低了线的高度，允许相邻的线对线寄生电容低于在相同高度和线宽处的横截面中的四边形配置的现有技术线的相邻线对线寄生电容，线间水平距离条件。由于类似的原因，线对衬底寄生电容也被允许更低。因此，提供了通过形成线产生的寄生电容最小化的半导体集成电路器件。

7. 发明授权

US4825273A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US4825273A
公开(公告)日：1989-04-25
申请号：US24010
申请日：1987-03-10
申请人： Takahiko Arakawa
发明人： Takahiko Arakawa
IPC分类号： H01L27/092 , H01L21/82 , H01L21/8238 , H01L27/118 , H01L27/02
CPC分类号： H01L27/11807
摘要： A basic cell for semiconductor integrated circuit devices comprises at least one MOS transistor of a first type of electric conduction and at least one MOS transistor of a second type of electric conduction. On both sides of the source/drain region of the MOS transistor of the first type, diffusion contact regions of the second type of electric conduction are disposed, and, on both sides of the source/drain region of the MOS transistor of the second type, diffusion contact regions of the first type of electric conduction are disposed. In the respective MOS transistors, gate electrode contact regions are provided on either side of the diffusion contact regions. These MOS transistors are symmetrical with respect to the transverse axis running through the center of the respective source/drain regions. Disclosure is also made of a semiconductor integrated circuit device of the master slice type including a plurality of such basic cells arranged at regular intervals.
摘要翻译：用于半导体集成电路器件的基本单元包括至少一个第一类型的导电MOS晶体管和至少一个第二类导电MOS晶体管。在第一类型的MOS晶体管的源极/漏极区域的两侧，设置第二类型导电的扩散接触区域，并且在第二类型的MOS晶体管的源极/漏极区域的两侧设置第一类导电的扩散接触区域。在各个MOS晶体管中，栅电极接触区设置在扩散接触区的两侧。这些MOS晶体管相对于穿过相应源极/漏极区域的中心的横轴是对称的。还公开了包括以规则间隔布置的多个这样的基本单元的主切片类型的半导体集成电路器件。

8. 发明授权

US07716410B2 Information device including main processing circuit, interface circuit, and microcomputer 有权
标题翻译：信息设备包括主处理电路，接口电路和微机
公开(公告)号：US07716410B2
公开(公告)日：2010-05-11
申请号：US11584550
申请日：2006-10-23
申请人： Hideo Nagano , Kikuo Muramatsu , Masayuki Koyama , Tomoko Ando , Motoki Higashida , Takahiko Arakawa , Makoto Hatakenaka
发明人： Hideo Nagano , Kikuo Muramatsu , Masayuki Koyama , Tomoko Ando , Motoki Higashida , Takahiko Arakawa , Makoto Hatakenaka
IPC分类号： G06F13/14
CPC分类号： H04N5/04 , G09G5/006 , H04N5/775 , H04N5/85
摘要： An information device includes a main processing circuit for executing signal processing related to a main function in the information device, a main microcomputer for controlling the main processing circuit, a receiver circuit for interfacing with the outside of the information device, and an interface microcomputer for controlling the receiver circuit, the interface microcomputer being provided separately from the main microcomputer.
摘要翻译：信息装置包括用于执行与信息装置中的主要功能相关的信号处理的主处理电路，用于控制主处理电路的主微型计算机，用于与信息装置的外部进行接口的接收机电路，以及用于控制接收机电路，接口微型计算机与主微型计算机分开设置。

9. 发明授权

US5291043A Semiconductor integrated circuit device having gate array 失效
标题翻译：具有门阵列的半导体集成电路器件
公开(公告)号：US5291043A
公开(公告)日：1994-03-01
申请号：US879103
申请日：1992-05-04
申请人： Takahiko Arakawa
发明人： Takahiko Arakawa
IPC分类号： H01L27/118 , H01L27/02 , H01L27/10
CPC分类号： H01L27/11807
摘要： A gate array semiconductor integrated circuit device allowing less clock skews is disclosed. The device includes a clock signal driver formed in the part under a power supply interconnection for input-output buffer in a power supply pin region or a ground pin region. The clock signal driver is formed in the power supply pin region and so on which, conventionally, was not utilized, so that the clock signal driver can be large enough to provide a clock signal to each basic cell column. Therefore, the input-output buffer region is not unduly occupied by the clock signal driver, and the connecting pads do not become useless.
摘要翻译：公开了一种允许较少时钟偏移的门阵列半导体集成电路器件。该器件包括在电源引脚区域或接地引脚区域内的输入输出缓冲器的电源互连部分下方形成的时钟信号驱动器。时钟信号驱动器形成在通常未被使用的电源引脚区域等中，使得时钟信号驱动器可以足够大以向每个基本单元列提供时钟信号。因此，输入输出缓冲区域不会被时钟信号驱动器过度占用，并且连接焊盘不会变得无用。

10. 发明授权

US07984223B2 Information device including main processing circuit, interface circuit, and microcomputer 有权
标题翻译：信息设备包括主处理电路，接口电路和微机
公开(公告)号：US07984223B2
公开(公告)日：2011-07-19
申请号：US12659545
申请日：2010-03-12
申请人： Hideo Nagano , Kikuo Muramatsu , Masayuki Koyama , Tomoko Ando , Motoki Higashida , Takahiko Arakawa , Makoto Hatakenaka
发明人： Hideo Nagano , Kikuo Muramatsu , Masayuki Koyama , Tomoko Ando , Motoki Higashida , Takahiko Arakawa , Makoto Hatakenaka
IPC分类号： G06F13/14
CPC分类号： H04N5/04 , G09G5/006 , H04N5/775 , H04N5/85
摘要： An information device packaged in one package includes a main function unit and an interface function unit. The main function unit includes a main processing circuit for executing signal processing related to a main function in the information device and a first microcomputer for controlling the main processing circuit by executing a first firmware program. The interface function unit includes an interface function unit including a first interface circuit for receiving data from an exterior device located outside of the information device to provide to the main function unit, a second interface circuit for performing an authentication operation with the exterior device, a second microcomputer for controlling the first interface circuit, and a memory for storing a second firmware program for controlling the first interface circuit.
摘要翻译：包装在一个包装中的信息装置包括主功能单元和接口功能单元。主功能单元包括用于执行与信息装置中的主要功能相关的信号处理的主处理电路和用于通过执行第一固件程序来控制主处理电路的第一微型计算机。接口功能单元包括接口功能单元，其包括第一接口电路，用于从位于信息设备外部的外部设备接收数据，以向主功能单元提供用于与外部设备进行认证操作的第二接口电路，用于控制第一接口电路的第二微型计算机，以及用于存储用于控制第一接口电路的第二固件程序的存储器。

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