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    • 1. 发明授权
      US5148514A Neural network integrated circuit device having self-organizing function 失效
    • Neural network integrated circuit device having self-organizing function
    • 具有自组织功能的神经网络集成电路器件
    • US5148514A
    • 1992-09-15
    • US515476
    • 1990-04-24
    • Yutaka Arima , Ichiro Tomioka , Toshiaki Hanibuchi
    • Yutaka Arima , Ichiro Tomioka , Toshiaki Hanibuchi
    • G06N3/063
    • G06N3/063
    • An extension directed integrated circuit device having a learning function on a Boltzmann model, includes a plurality of synapse representing units arrayed in a matrix to form a rectangle including a first and second triangles on a semiconductor chip, a plurality of neuron representing units and a plurality of educator signal control circuits which are arranged along first and second sides of the rectangle, and a plurality of buffer circuits arranged along third and fourth sides of the rectangle. The first side is opposite to the third side, and the second side is opposite to the fourth side. Axon signal transfer lines and dendrite signal lines are so arranged that the neuron representing units are full-connected in each of the first right triangle the second right triangle. Alternatively, axon signal lines and dendrite signal ines are arranged in parallel with rows and columns of the synapse representing unit matrix, so that the neuron representing units are full-connected in the rectangle. Each synapse representing unit is connected to a pair of axon signal transfer lines and a pair of dendrite signal transfer lines.
    • 具有Boltzmann模型学习功能的延伸定向集成电路装置包括多个突触，其表示以矩阵排列的单元，以形成包括半导体芯片上的第一和第二三角形的矩形，多个神经元表示单元和多个 沿矩形的第一和第二侧布置的教育者信号控制电路以及沿矩形的第三和第四侧布置的多个缓冲电路。 第一面与第三面相反，第二面与第四面相反。 轴突信号传输线和枝晶信号线被布置成使得表示单元的神经元在第二直角三角形的第一直角三角形的每一个中是全连接的。 或者，轴突信号线和枝晶信号与突触表示单位矩阵的行和列平行布置，使得表示单元的神经元表示在矩形中。 每个突触代表单元连接到一对轴突信号传输线和一对枝晶信号传输线。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 2. 发明授权
      US5293457A Neural network integrated circuit device having self-organizing function 失效
    • Neural network integrated circuit device having self-organizing function
    • 具有自组织功能的神经网络集成电路器件
    • US5293457A
    • 1994-03-08
    • US877514
    • 1992-05-01
    • Yutaka Arima , Ichiro Tomioka , Toshiaki Hanibuchi
    • Yutaka Arima , Ichiro Tomioka , Toshiaki Hanibuchi
    • G06G7/60 , G06F15/18 , G06N3/063 , G06N99/00 , H01L21/822 , H01L27/04 , G06F7/00
    • G06N3/063
    • An extension directed integrated circuit device having a learning function on a Boltzmann model, includes a plurality of synapse representing units arrayed in a matrix, a plurality of neuron representing units, a plurality of educator signal control circuits, and a plurality of buffer circuits. Each synapse representing unit is connected to a pair of axon signal transfer lines and a pair of dendrite signal transfer lines. Each synapse representing unit includes a learning control circuit which derives synapse load change value data in accordance with predetermined learning rules in response to a first axon signal Si and a second axon signal Sj, a synapse load representing circuit which corrects a synapse load in response to the synapse load change valued data and holds the corrected synapse load value Wij, a first synapse coupling operating circuit which derives a current signal indicating a product Wij.multidot.Si from the synapse load Wij and the first axon signal Si and transfers the same to a first dendrite signal line, and a second product signal indicating a product Wij.multidot.Sj from the synapse load Wij and the second axon signal Sj and transfers the same onto a second dendrite signal line.
    • 具有Boltzmann模型学习功能的延伸定向集成电路器件包括表示以矩阵排列的单元的多个突触，多个神经元表示单元，多个教育者信号控制电路和多个缓冲电路。 每个突触代表单元连接到一对轴突信号传输线和一对枝晶信号传输线。 每个突触表示单元包括学习控制电路，该学习控制电路响应于第一轴突信号Si和第二轴突信号Sj，根据预定的学习规则导出突触负荷变化值数据，突变负载表示电路响应于 突触负荷改变数值数据并保持校正的突触负载值Wij，第一突触耦合操作电路从突触负载Wij和第一轴突信号Si导出指示产品Wij * Si的电流信号，并将其转移到第一 枝晶信号线和第二产品信号，其从突触载荷Wij和第二轴突信号Sj指示乘积Wij * Sj，并将其传送到第二枝晶信号线。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 6. 发明授权
      US4870345A Semiconductor intergrated circuit device 失效
    • Semiconductor intergrated circuit device
    • 半导体集成电路器件
    • US4870345A
    • 1989-09-26
    • US81095
    • 1987-08-03
    • Ichiro Tomioka , Kazuhiro Sakashita , Satoru Kishida , Toshiaki Hanibuchi , Takahiko Arakawa
    • Ichiro Tomioka , Kazuhiro Sakashita , Satoru Kishida , Toshiaki Hanibuchi , Takahiko Arakawa
    • G01R31/3185
    • G01R31/318536
    • A semiconductor integrated circuit includes cascaded asynchronous sequential logic circuits. Scanning shift registers are provided between the asynchronous sequential circuits to permit test data to be applied to the inputs of the circuits and to latch and shift out output data provided by the circuits in response to the test data. Additional gating circuitry is provided between the scanning shift registers and the inputs of the asynchronous sequential circuits to prevent new data latched into the scanning shift register from causing the asynchronous sequential circuit connected to the scanning shift register output from changing state during testing. This same additional circuitry may be used to provide pulses of controlled width and/or timing to asynchronous sequential circuit inputs in response to externally generated gating control signals.
    • 半导体集成电路包括级联异步顺序逻辑电路。 在异步时序电路之间提供扫描移位寄存器，以允许将测试数据应用于电路的输入，并根据测试数据锁存和移出由电路提供的输出数据。 在扫描移位寄存器和异步顺序电路的输入之间提供附加的选通电路，以防止锁存在扫描移位寄存器中的新数据使测试期间连接到扫描移位寄存器输出的异步时序电路变化。 可以使用相同的附加电路来响应于外部产生的门控控制信号来提供受控宽度和/或定时到异步顺序电路输入的脉冲。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 8. 发明授权
      US4864579A Semiconductor integrated circuit device 失效
    • Semiconductor integrated circuit device
    • 半导体集成电路器件
    • US4864579A
    • 1989-09-05
    • US81094
    • 1987-08-03
    • Satoru Kishida , Kazuhiro Sakashita , Ichiro Tomioka
    • Satoru Kishida , Kazuhiro Sakashita , Ichiro Tomioka
    • G06F11/16 , G01R31/3185 , G06F11/22
    • G01R31/318541
    • A semiconductor integrated circuit device for transmitting data between a plurality of circuit blocks at least one thereof including a sequential circuit and enabling the circuit blocks to test in a scan testing type which has a plurality of scan registers provided between the plurality of circuit blocks corresponding to the number of bits of data to be transmitted for outputting the output data of the previous stage circuit block as it is at ordinary operating time and for holding and outputting the output data of the previous circuit block or test data for scan test synchronously with an external clock at testing time so that the circuits are connected by a shift register pass in such a manner that the entirety has one shaft register function, and a latch circuit provided at its data input terminal to the data output terminal of the corresponding scan register for outputtting the output data of the corresponding scan register as it is to the circuit block of next stage at ordinary operation time and holding the output data of the corresponding scan register before the scanning operation in a scan mode at testing time to continuously apply the data to the circuit block of next stage and holding and outputting the output data of the corresponding scan register in a test mode synchronously with the external clock, test data setting means for setting serial data of test from the exterior of the circuit device to each of the scan registers, test result outputting means for sequentially outputting the data of each scan register as serial data out of the circuit device, and operation switching means for switching the ordinary operation and the testing operation and switching the scan mode and the test mode, thereby enabling the semiconductor integrated circuit device to be readily subjected to a scan test together with circuit blocks including asynchronous sequential circuits.
    • 一种半导体集成电路装置，用于在多个电路块之间传输数据，其中至少一个电路块包括时序电路，并使电路块能够以扫描测试类型进行测试，该扫描测试类型具有多个扫描寄存器，该扫描寄存器设置在与 要发送的数据的比特数，用于在正常操作时间输出前一级电路块的输出数据，并且用于保持和输出前一个电路块的输出数据或与外部的同步的扫描测试的测试数据 时钟，使得电路通过移位寄存器通过连接，使得整体具有一个轴寄存器功能，以及锁存电路，在其数据输入端提供到相应扫描寄存器的数据输出端，用于输出 相应的扫描寄存器的输出数据与普通操作下一级的电路块相同 并且在测试时间内以扫描模式扫描操作之前保持相应扫描寄存器的输出数据，以将数据连续地施加到下一级的电路块，并在测试中保存和输出相应的扫描寄存器的输出数据 与外部时钟同步的模式的测试数据设置装置，用于将测试的串行数据从电路设备的外部设置到每个扫描寄存器;测试结果输出装置，用于将每个扫描寄存器的数据顺序地输出为 电路装置和用于切换普通操作和测试操作以及切换扫描模式和测试模式的操作切换装置，从而使得半导体集成电路器件能够容易地与包括异步时序电路的电路块一起进行扫描测试。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 9. 发明授权
      US4995039A Circuit for transparent scan path testing of integrated circuit devices 失效
    • Circuit for transparent scan path testing of integrated circuit devices
    • 集成电路器件透明扫描路径测试电路
    • US4995039A
    • 1991-02-19
    • US247289
    • 1988-09-22
    • Kazuhiro Sakashita , Ichiro Tomioka , Takeshi Hashizume
    • Kazuhiro Sakashita , Ichiro Tomioka , Takeshi Hashizume
    • G01R31/28 , G01R31/3185 , G06F11/22 , H01L21/66
    • G01R31/318552
    • In a circuit for testing integrated circuit devices, scan registers (8.about.16) and data selecting circuits (20-28) are connected between a plurality of circuit blocks (29.about.31) in correspondence with the number of bits of the data, with the scan registers connected to each other by a shift register path so as to have a function of one shift register as a whole. A register selecting circuit (20.about.28) is connected to a clock input terminal (T1, T2) of the scan register. The scan registers other than those corresponding to the logic circuit block to be tested are selected by the register selecting circuit. Consequently, clocks for scanning scan registers other than those provided before and after the required circuit block are eliminated, enabling reduction of time required for scan test.
    • 在用于测试集成电路器件的电路中，扫描寄存器（8差分16）和数据选择电路（20-28）根据数据的位数连接在多个电路块（29差分31）之间， 扫描寄存器通过移位寄存器路径彼此连接，从而整体上具有一个移位寄存器的功能。 寄存器选择电路（20差分28）连接到扫描寄存器的时钟输入端（T1，T2）。 除了与要测试的逻辑电路块相对应的扫描寄存器之外的扫描寄存器由寄存器选择电路选择。 因此，消除了除所需电路块之前和之后提供的扫描寄存器之外的扫描寄存器的时钟，从而可以减少扫描测试所需的时间。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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