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1. 发明授权

US5552618A Multi-voltage-lever master-slice integrated circuit 失效
公开(公告)号：US5552618A
公开(公告)日：1996-09-03
申请号：US326086
申请日：1994-10-19
申请人： Hideki Taniguchi , Ichiro Tomioka , Kunihiko Sanada , Masatomi Okabe
发明人： Hideki Taniguchi , Ichiro Tomioka , Kunihiko Sanada , Masatomi Okabe
IPC分类号： H01L21/82 , H01L27/118 , H01L27/10 , H01L27/02
CPC分类号： H01L27/11898 , H01L2224/05554
摘要： A master-slice semiconductor integrated circuit device includes a substrate for an input/output circuit section, which is segmented into a plurality of segments during a master processing step. In a slice processing step, slice cells are formed, using different substrate segments. Input/output circuits are formed by respective slice cells so that desired different supply voltages can be applied to input/output circuits on different substrate segments.

2. 发明授权

US4810900A ECL circuit with improved .alpha.-ray resistant properties 失效
标题翻译： ECL电路具有改进的耐γ射线特性
公开(公告)号：US4810900A
公开(公告)日：1989-03-07
申请号：US40252
申请日：1987-04-20
申请人： Masatomi Okabe
发明人： Masatomi Okabe
IPC分类号： H03K3/286 , H03K3/013 , H03K3/037 , H03K3/2885 , H03K19/003 , H03K19/086 , H03K3/00
CPC分类号： H03K3/013 , H03K3/0375 , H03K3/2885
摘要： A semiconductor integrated circuit device with an ECL sequential circuit is disclosed, which comprises a data holding circuit provided the ECL sequential circuit for holding the output thereof, and an emitter follower for feeding the output of the data holding circuit as an input thereof, and an emitter follower circuit control circuit thereto. The emitter follower current when the emitter potential on the emitter follower is at a high level, is set to be lower than the emitter follower current when the emitter potential is at a low level.
摘要翻译：公开了一种具有ECL时序电路的半导体集成电路器件，其包括一个数据保持电路，该数据保持电路提供有用于保持其输出的ECL时序电路，以及用于馈送数据保持电路的输出作为其输入的射极跟随器，射极跟随器电路控制电路。当发射极电位处于低电平时，发射极跟随器处的发射极电位处于高电平时的射极跟随器电流被设定为低于射极跟随器电流。

3. 发明授权

US5602406A Semiconductor integrated circuit device with reduced clock signal line noise 失效
标题翻译：半导体集成电路器件具有降低的时钟信号线噪声
公开(公告)号：US5602406A
公开(公告)日：1997-02-11
申请号：US517193
申请日：1995-08-21
申请人： Masatomi Okabe
发明人： Masatomi Okabe
IPC分类号： H01L21/82 , H01L21/822 , H01L23/522 , H01L23/528 , H01L27/04 , H01L27/118 , H01L27/10 , H01L23/552
CPC分类号： H01L27/11803 , H01L23/5222 , H01L23/5225 , H01L23/528 , H01L2924/0002
摘要： It is an object of the present invention to design in a short period of time a semiconductor integrated circuit device capable of stable operation with high noise margin by reducing effects of noise caused by coupling capacitance between clock signal lines and other signal lines in a semiconductor integrated circuit device with a finer structure. A macro-cell (1a) used in designing with a Computer Aided Design system has a structure in which a clock signal line (6) is interposed and shielded between V.sub.DD power-supply lines (4 and 4a). By using such a basic macro-cell (1a) with the shielded clock signal line (6), coupling capacitance can always be reduced between the clock signal lines and other signal lines formed in interconnection spaces even when using the Computer Aided Design.
摘要翻译：本发明的目的是在短时间内设计半导体集成电路器件，其能够通过减少由半导体集成的时钟信号线和其它信号线之间的耦合电容引起的噪声的影响而具有高噪声容限的稳定操作电路设备结构更精细。用于用计算机辅助设计系统进行设计的宏单元（1a）具有在VDD电源线（4和4a）之间插入和屏蔽时钟信号线（6）的结构。通过使用具有屏蔽时钟信号线（6）的这种基本宏单元（1a），即使在使用计算机辅助设计时，也可以在时钟信号线和互连空间中形成的其它信号线之间总是减小耦合电容。

4. 发明授权

US5619048A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US5619048A
公开(公告)日：1997-04-08
申请号：US495022
申请日：1995-06-27
申请人： Miho Yokota , Masatomi Okabe
发明人： Miho Yokota , Masatomi Okabe
IPC分类号： H01L21/82 , H01L27/118 , H01L27/02
CPC分类号： H01L27/11898
摘要： In order to lay out a driver circuit having high drivability without increasing a semiconductor chip area, a macro cell (22) such as a clock driver having a large fan-out is arranged under a feeder line (20). It is possible to feed the macro cell (22) from the feeder line (20), which is a second layer aluminum wire, in a short distance. An input signal line (23) and an output signal line (24) which are connected to input and output pins of the macro cell (22) are provided in positions not to be in contact with the feeder line (20). Since the macro cell (22) is arranged in a portion of an internal region which is located under the feeder line (20), it is possible to suppress increase of the layout area as well as electromigration caused by feeding to the macro cell (22).
摘要翻译：为了在不增加半导体芯片面积的情况下布置具有高驱动能力的驱动电路，在馈线（20）下方布置有具有大扇出的时钟驱动器的宏单元（22）。可以在短距离内从作为第二层铝线的馈线（20）馈送宏电池（22）。连接到宏单元（22）的输入和输出引脚的输入信号线（23）和输出信号线（24）设置在不与馈线（20）接触的位置。由于宏单元（22）布置在位于馈线（20）下方的内部区域的一部分中，所以可以抑制布局区域的增加以及由馈送到宏单元（22）导致的电迁移）。

5. 发明授权

US5444276A Semiconductor integrated circuit macro cells with wide lines 失效
标题翻译：半导体集成电路宏单元格宽线
公开(公告)号：US5444276A
公开(公告)日：1995-08-22
申请号：US165944
申请日：1993-12-14
申请人： Miho Yokota , Masatomi Okabe
发明人： Miho Yokota , Masatomi Okabe
IPC分类号： H01L21/82 , H01L27/118 , H01L27/02
CPC分类号： H01L27/11898
摘要： In order to lay out a driver circuit having high drivability without increasing a semiconductor chip area, a macro cell (22) such as a clock driver having a large fan-out is arranged under a feeder line (20). It is possible to feed the macro cell (22) from the feeder line (20), which is a second layer aluminum wire, in a short distance. An input signal line (23) and an output signal line (24) which are connected to input and output pins of the macro cell (22) are provided in positions not to be in contact with the feeder line (20). Since the macro cell (22) is arranged in a portion of an internal region which is located under the feeder line (20), it is possible to suppress increase of the layout area as well as electromigration caused by feeding to the macro cell (22).
摘要翻译：为了在不增加半导体芯片面积的情况下布置具有高驱动能力的驱动电路，在馈线（20）下方布置有具有大扇出的时钟驱动器的宏单元（22）。可以在短距离内从作为第二层铝线的馈线（20）馈送宏电池（22）。连接到宏单元（22）的输入和输出引脚的输入信号线（23）和输出信号线（24）设置在不与馈线（20）接触的位置。由于宏单元（22）布置在位于馈线（20）下方的内部区域的一部分中，所以可以抑制布局区域的增加以及由馈送到宏单元（22）导致的电迁移）。

6. 发明授权

US5404035A Multi-voltage-level master-slice integrated circuit 失效
标题翻译：多电压级主片集成电路
公开(公告)号：US5404035A
公开(公告)日：1995-04-04
申请号：US75211
申请日：1993-06-10
申请人： Hideki Taniguchi , Ichiro Tomioka , Kunihiko Sanada , Masatomi Okabe
发明人： Hideki Taniguchi , Ichiro Tomioka , Kunihiko Sanada , Masatomi Okabe
IPC分类号： H01L21/82 , H01L27/118 , H01L27/10 , H01L27/02
CPC分类号： H01L27/11898 , H01L2224/05554
摘要： A master-slice semiconductor integrated circuit device includes a substrate for an input/output circuit section, which is segmented into a plurality of segments during a master processing step. In a slice processing step, slice cells are formed, using different substrate segments. Input/output circuits are formed by respective slice cells so that desired different supply voltages can be applied to input/output circuits on different substrate segments.
摘要翻译：主切片半导体集成电路器件包括用于输入/输出电路部分的衬底，其在主处理步骤期间被分割成多个段。在切片处理步骤中，使用不同的基底片段形成切片单元。输入/输出电路由相应的切片单元形成，从而可以将期望的不同电源电压施加到不同基片段上的输入/输出电路。

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