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1. 发明申请

US20090240995A1 METHOD AND APPARATUS FOR IMPROVING RANDOM PATTERN TESTING OF LOGIC STRUCTURES 有权
标题翻译：改进逻辑结构随机模式测试的方法和装置
公开(公告)号：US20090240995A1
公开(公告)日：2009-09-24
申请号：US12051744
申请日：2008-03-19
申请人： Mary P. Kusko , Barry W. Krumm , Patrick Meaney , Bryan J. Robbins
发明人： Mary P. Kusko , Barry W. Krumm , Patrick Meaney , Bryan J. Robbins
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/3177 , G01R31/318385
摘要： A test method and apparatus for randomly testing logic structures. The method includes identifying and analyzing a functional behavior of a logic structure to be covered during the random testing, modifying the logic structure such that the logic structure behaves in a functional manner during random testing, and generating patterns to exercise the modified logic structure.
摘要翻译：一种用于随机测试逻辑结构的测试方法和设备。该方法包括识别和分析在随机测试期间要覆盖的逻辑结构的功能行为，修改逻辑结构，使得逻辑结构在随机测试期间以功能方式行为，以及生成用于执行修改的逻辑结构的模式。

2. 发明授权

US08095837B2 Method and apparatus for improving random pattern testing of logic structures 有权
标题翻译：改进逻辑结构随机模式测试的方法和装置
公开(公告)号：US08095837B2
公开(公告)日：2012-01-10
申请号：US12051744
申请日：2008-03-19
申请人： Mary P. Kusko , Barry W. Krumm , Patrick Meaney , Bryan J. Robbins
发明人： Mary P. Kusko , Barry W. Krumm , Patrick Meaney , Bryan J. Robbins
IPC分类号： G01R31/28
CPC分类号： G01R31/3177 , G01R31/318385
摘要： A test method and apparatus for randomly testing logic structures. The method includes identifying and analyzing a functional behavior of a logic structure to be covered during the random testing, modifying the logic structure such that the logic structure behaves in a functional manner during random testing, and generating patterns to exercise the modified logic structure.
摘要翻译：一种用于随机测试逻辑结构的测试方法和设备。该方法包括识别和分析在随机测试期间要覆盖的逻辑结构的功能行为，修改逻辑结构，使得逻辑结构在随机测试期间以功能方式行为，以及生成用于执行修改的逻辑结构的模式。

3. 发明授权

US06314540B1 Partitioned pseudo-random logic test for improved manufacturability of semiconductor chips 失效
标题翻译：分区伪随机逻辑测试，以提高半导体芯片的可制造性
公开(公告)号：US06314540B1
公开(公告)日：2001-11-06
申请号：US09290516
申请日：1999-04-12
申请人： William V. Huott , Mary P. Kusko , Gregory O'Malley , Bryan J. Robbins
发明人： William V. Huott , Mary P. Kusko , Gregory O'Malley , Bryan J. Robbins
IPC分类号： G01R3128
CPC分类号： G01R31/31813 , G01R31/318385
摘要： A partitioned pseudo-random logic test (PRLT) for integrated circuit chips for improving manufacturability is disclosed. The technique makes available previously difficult-to-collect empirical data to accurately improve test effectiveness while significantly lowering test time and test cost. An embodiment includes a method for testing IC chips, including generating values for latches for a complete test pattern set, partitioning the test pattern set into a plurality of partitioned test pattern subsets, and running the subsets against a chip. Another embodiment is directed to a system that tests IC chips, having a latch value generator that generates values for latches for a complete test pattern set, a test pattern divider that partitions the complete test pattern set into a plurality of partitioned test pattern subsets, and a tester that runs the partitioned test pattern subsets against the chip.
摘要翻译：公开了一种用于提高可制造性的集成电路芯片的分区伪随机逻辑测试（PRLT）。该技术使以前难以收集的经验数据可以准确地提高测试效果，同时显着降低测试时间和测试成本。一个实施例包括一种用于测试IC芯片的方法，包括产生用于完整测试模式集合的锁存器的值，将测试模式集划分成多个分割测试模式子集，以及针对芯片运行子集。另一个实施例涉及测试IC芯片的系统，具有为整个测试模式集合产生锁存器的值的锁存值产生器，将完整测试模式集分成多个分区测试模式子集的测试模式分割器，以及运行分区的测试器针对芯片的测试模式子集。

4. 发明授权

US06671838B1 Method and apparatus for programmable LBIST channel weighting 有权
标题翻译：用于可编程LBIST通道加权的方法和装置
公开(公告)号：US06671838B1
公开(公告)日：2003-12-30
申请号：US09671413
申请日：2000-09-27
申请人： Timothy J. Koprowski , Mary P. Kusko , Lawrence K. Lange , Bryan J. Robbins
发明人： Timothy J. Koprowski , Mary P. Kusko , Lawrence K. Lange , Bryan J. Robbins
IPC分类号： G11C2900
CPC分类号： G06F11/27 , G01R31/31835 , G01R31/318385 , G01R31/318547
摘要： An exemplary embodiment of the invention is a built-in self-test (BIST) method and apparatus for testing the logic circuits on an integrated circuit. Random test pattern data is generated by a random pattern generator. A random resistant fault analysis (RRFA) program is used to determine the weighting requirements, on a per channel basis, for testing the logic circuits. The weighting requirements from the RRFA program are applied to the random test pattern data resulting in weighted test pattern data. The weighted test pattern data is then programmably applied to the scan chain.
摘要翻译：本发明的示例性实施例是用于测试集成电路上的逻辑电路的内置自检（BIST）方法和装置。随机测试图案数据由随机图案生成器生成。随机阻抗故障分析（RRFA）程序用于确定每个通道的加权要求，用于测试逻辑电路。来自RRFA程序的权重要求应用于随机测试模式数据，从而产生加权测试模式数据。加权测试图案数据然后可编程地应用于扫描链。

5. 发明授权

US06836865B2 Method and apparatus for facilitating random pattern testing of logic structures 失效
标题翻译：用于促进逻辑结构的随机模式测试的方法和装置
公开(公告)号：US06836865B2
公开(公告)日：2004-12-28
申请号：US09973398
申请日：2001-10-09
申请人： Mary P. Kusko , William V. Huott , Bryan J. Robbins , Timothy Charest
发明人： Mary P. Kusko , William V. Huott , Bryan J. Robbins , Timothy Charest
IPC分类号： G01R3128
CPC分类号： G01R31/318385 , G01R31/31813 , G01R31/318544
摘要： A method for preparing a logic structure for random pattern testing is disclosed. In an exemplary embodiment of the invention, the method includes configuring a select mechanism within a data scan chain, the select mechanism configured between a first register in the data scan chain and a second register. A parallel data path is routed within the scan chain, the parallel data path beginning from an input side of the first register, running through the select mechanism, and ending at an input side of the second register. Thus configured, the select mechanism is capable of switching a source path of input data to said second register from a normal data path to the parallel data path. When the parallel data path is selected as the source path of input data to the second register, data loaded into the second register matches data loaded into the first register.
摘要翻译：公开了一种用于准备用于随机模式测试的逻辑结构的方法。在本发明的示例性实施例中，该方法包括配置数据扫描链内的选择机制，所述选择机制配置在数据扫描链中的第一寄存器和第二寄存器之间。平行数据路径在扫描链内路由，并行数据路径从第一寄存器的输入侧开始，通过选择机制运行，并在第二寄存器的输入端结束。如此配置，选择机制能够将来自正常数据路径的输入数据的源路径切换到所述第二寄存器到并行数据路径。当选择并行数据路径作为第二寄存器的输入数据的源路径时，加载到第二寄存器中的数据匹配加载到第一寄存器中的数据。

6. 发明授权

US08443313B2 Circuit design optimization 失效
标题翻译：电路设计优化
公开(公告)号：US08443313B2
公开(公告)日：2013-05-14
申请号：US12858522
申请日：2010-08-18
申请人： Samuel I. Ward , Kevin F. Reick , Bryan J. Robbins , Thomas E. Rosser , Robert J. Shadowen
发明人： Samuel I. Ward , Kevin F. Reick , Bryan J. Robbins , Thomas E. Rosser , Robert J. Shadowen
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A method comprises generating a first behavioral model of a circuit describing a physical circuit in a first configuration. The first configuration comprises a first master latch, a first fanout path, and a logic cone. The first master latch couples to the first fanout path and is configured to receive a first data input signal. The first fanout path comprises a plurality of output sinks, each coupled to the logic cone. The first behavioral model is modified to generate a second behavioral model describing the physical circuit in a second configuration. The second configuration comprises an error circuit and an abstract latch clone based on the first master latch. A configuration file is generated based on the second behavioral model. The configuration file comprises information representing a plurality of instantiated latch clones based on the abstract latch clone, each configured to couple to the first data input signal and to one or more output sinks of the plurality of output sinks. The second behavioral model and the configuration file are together configured for input to a synthesis tool.
摘要翻译：一种方法包括生成描述第一配置中的物理电路的电路的第一行为模型。第一配置包括第一主锁存器，第一扇出通路和逻辑锥。第一主锁存器耦合到第一扇出通道并被配置为接收第一数据输入信号。第一扇出路径包括多个输出接收器，每个输出接收器耦合到逻辑锥。修改第一行为模型以产生描述第二配置中的物理电路的第二行为模型。第二配置包括基于第一主锁存器的错误电路和抽象锁存器克隆。基于第二行为模型生成配置文件。配置文件包括基于抽象锁存克隆的表示多个实例化锁存克隆的信息，每个被配置为耦合到第一数据输入信号和多个输出汇的一个或多个输出汇。第二行为模型和配置文件一起配置为输入到综合工具。

7. 发明申请

US20120047476A1 CIRCUIT DESIGN OPTIMIZATION 失效
标题翻译：电路设计优化
公开(公告)号：US20120047476A1
公开(公告)日：2012-02-23
申请号：US12858522
申请日：2010-08-18
申请人： Samuel I. Ward , Kevin F. Reick , Bryan J. Robbins , Thomas E. Rosser , Robert J. Shadowen
发明人： Samuel I. Ward , Kevin F. Reick , Bryan J. Robbins , Thomas E. Rosser , Robert J. Shadowen
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A method comprises generating a first behavioral model of a circuit describing a physical circuit in a first configuration. The first configuration comprises a first master latch, a first fanout path, and a logic cone. The first master latch couples to the first fanout path and is configured to receive a first data input signal. The first fanout path comprises a plurality of output sinks, each coupled to the logic cone. The first behavioral model is modified to generate a second behavioral model describing the physical circuit in a second configuration. The second configuration comprises an error circuit and an abstract latch clone based on the first master latch. A configuration file is generated based on the second behavioral model. The configuration file comprises information representing a plurality of instantiated latch clones based on the abstract latch clone, each configured to couple to the first data input signal and to one or more output sinks of the plurality of output sinks. The second behavioral model and the configuration file are together configured for input to a synthesis tool.
摘要翻译：一种方法包括生成描述第一配置中的物理电路的电路的第一行为模型。第一配置包括第一主锁存器，第一扇出通路和逻辑锥。第一主锁存器耦合到第一扇出通道并被配置为接收第一数据输入信号。第一扇出路径包括多个输出接收器，每个输出接收器耦合到逻辑锥。修改第一行为模型以产生描述第二配置中的物理电路的第二行为模型。第二配置包括基于第一主锁存器的错误电路和抽象锁存器克隆。基于第二行为模型生成配置文件。配置文件包括基于抽象锁存克隆的表示多个实例化锁存克隆的信息，每个被配置为耦合到第一数据输入信号和多个输出汇的一个或多个输出汇。第二行为模型和配置文件一起配置为输入到综合工具。

8. 发明申请

US20090307548A1 METHOD AND APPARATUS FOR PERFORMING LOGIC BUILT-IN SELF-TESTING OF AN INTEGRATED CIRCUIT 有权
标题翻译：用于执行集成电路逻辑内置自检的方法和装置
公开(公告)号：US20090307548A1
公开(公告)日：2009-12-10
申请号：US12133830
申请日：2008-06-05
申请人： Donato O. Forlenza , Orazio P. Forlenza , Bryan J. Robbins , Phong T. Tran
发明人： Donato O. Forlenza , Orazio P. Forlenza , Bryan J. Robbins , Phong T. Tran
IPC分类号： G01R31/3187 , G06F11/00
CPC分类号： G01R31/318533
摘要： A method for performing a logical built-in self-test of an integrated circuit is disclosed. The method includes performing a flush and scan test to determine whether the scan chains function correctly. If one of the scan chains does not function correctly, the logical built-in self-test is terminated. If each of the scan chains functions correctly, a structural test of the design-for-test logic supporting LBIST is performed to determine whether the LBIST design-for-test logic functions correctly. If the LBIST design-for-test logic does not function correctly, the logical built-in self-test is terminated. If the LBIST design-for-test logic functions correctly, a level sensitive scan design test of the functional combinational logic is performed using the logic supporting LBIST design-for-test to determine if the integrated circuit functions correctly.
摘要翻译：公开了一种用于执行集成电路的逻辑内置自检的方法。该方法包括执行刷新和扫描测试以确定扫描链是否正常工作。如果其中一个扫描链无法正常工作，则逻辑内置自检终止。如果每个扫描链都正常工作，则执行支持LBIST的测试用设计逻辑的结构测试，以确定LBIST设计测试逻辑是否正确运行。如果LBIST设计测试逻辑不能正常工作，则逻辑内置自检终止。如果LBIST设计测试逻辑正常工作，则使用支持LBIST设计测试的逻辑执行功能组合逻辑的电平敏感扫描设计测试，以确定集成电路是否正常工作。

9. 发明授权

US08386230B2 Circuit design optimization 失效
标题翻译：电路设计优化
公开(公告)号：US08386230B2
公开(公告)日：2013-02-26
申请号：US12858562
申请日：2010-08-18
申请人： Samuel I. Ward , Kevin F. Reick , Bryan J. Robbins , Thomas E. Rosser , Robert J. Shadowen
发明人： Samuel I. Ward , Kevin F. Reick , Bryan J. Robbins , Thomas E. Rosser , Robert J. Shadowen
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/14
摘要： A method includes generating a first behavioral model of a circuit, the first behavioral model describing a physical circuit in a first configuration. The first configuration comprises a first logic structure configured to generate a first intermediate signal based on a received first plurality of inputs. The first configuration further comprises a logic cone configured to generate a scan output based on the first intermediate signal and a plurality of scan inputs. The first behavioral model is modified to generate a second behavioral model describing the physical circuit in a second configuration. The second configuration comprises an error circuit configured to receive the scan output and the first intermediate signal. A testability model is generated based on the second behavioral model, the testability model comprising a first structural representation of the first logic structure. In the event the first logic structure causes a coverage problem, the testability model is modified to include an inversion structure. The inversion structure is configured based on the first logic structure. The inversion structure is configured to generate an inversion structure output. The testability model is modified to couple the inversion structure output as an input to the error circuit.
摘要翻译：一种方法包括生成电路的第一行为模型，第一行为模型描述第一配置中的物理电路。第一配置包括被配置为基于接收的第一多个输入生成第一中间信号的第一逻辑结构。第一配置还包括被配置为基于第一中间信号和多个扫描输入产生扫描输出的逻辑锥。修改第一行为模型以产生描述第二配置中的物理电路的第二行为模型。第二配置包括被配置为接收扫描输出和第一中间信号的误差电路。基于第二行为模型生成可测试性模型，可测性模型包括第一逻辑结构的第一结构表示。在第一逻辑结构引起覆盖问题的情况下，可修改性模型被修改为包括反演结构。基于第一逻辑结构配置反转结构。反演结构被配置为产生反演结构输出。修改可测试性模型，将反演结构输出作为输入耦合到误差电路。

10. 发明授权

US07117415B2 Automated BIST test pattern sequence generator software system and method 失效
标题翻译：自动BIST测试模式序列发生器软件系统及方法
公开(公告)号：US07117415B2
公开(公告)日：2006-10-03
申请号：US10757781
申请日：2004-01-15
申请人： Donato O. Forlenza , Orazio P. Forlenza , William J. Hurley , Bryan J. Robbins
发明人： Donato O. Forlenza , Orazio P. Forlenza , William J. Hurley , Bryan J. Robbins
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/318371 , G01R31/318342
摘要： Methods and systems for reducing the volume of test data associated with built in self testing (BIST) test methodologies (e.g., logical BIST, array BIST, etc.) and pattern structures are provided. Embodiments of the present invention store a limited number of “dynamic” test parameters for each test sequence that have changed relative to a previous test sequence.
摘要翻译：提供了用于减少与内置自检（BIST）测试方法（例如，逻辑BIST，阵列BIST等）和模式结构相关联的测试数据量的方法和系统。本发明的实施例存储针对相对于先前测试序列而改变的每个测试序列的有限数量的“动态”测试参数。

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