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1. 发明申请

US20090307548A1 METHOD AND APPARATUS FOR PERFORMING LOGIC BUILT-IN SELF-TESTING OF AN INTEGRATED CIRCUIT 有权
标题翻译：用于执行集成电路逻辑内置自检的方法和装置
公开(公告)号：US20090307548A1
公开(公告)日：2009-12-10
申请号：US12133830
申请日：2008-06-05
申请人： Donato O. Forlenza , Orazio P. Forlenza , Bryan J. Robbins , Phong T. Tran
发明人： Donato O. Forlenza , Orazio P. Forlenza , Bryan J. Robbins , Phong T. Tran
IPC分类号： G01R31/3187 , G06F11/00
CPC分类号： G01R31/318533
摘要： A method for performing a logical built-in self-test of an integrated circuit is disclosed. The method includes performing a flush and scan test to determine whether the scan chains function correctly. If one of the scan chains does not function correctly, the logical built-in self-test is terminated. If each of the scan chains functions correctly, a structural test of the design-for-test logic supporting LBIST is performed to determine whether the LBIST design-for-test logic functions correctly. If the LBIST design-for-test logic does not function correctly, the logical built-in self-test is terminated. If the LBIST design-for-test logic functions correctly, a level sensitive scan design test of the functional combinational logic is performed using the logic supporting LBIST design-for-test to determine if the integrated circuit functions correctly.
摘要翻译：公开了一种用于执行集成电路的逻辑内置自检的方法。该方法包括执行刷新和扫描测试以确定扫描链是否正常工作。如果其中一个扫描链无法正常工作，则逻辑内置自检终止。如果每个扫描链都正常工作，则执行支持LBIST的测试用设计逻辑的结构测试，以确定LBIST设计测试逻辑是否正确运行。如果LBIST设计测试逻辑不能正常工作，则逻辑内置自检终止。如果LBIST设计测试逻辑正常工作，则使用支持LBIST设计测试的逻辑执行功能组合逻辑的电平敏感扫描设计测试，以确定集成电路是否正常工作。

2. 发明授权

US07934134B2 Method and apparatus for performing logic built-in self-testing of an integrated circuit 有权
标题翻译：用于执行集成电路内置自检的逻辑的方法和装置
公开(公告)号：US07934134B2
公开(公告)日：2011-04-26
申请号：US12133830
申请日：2008-06-05
申请人： Donato O. Forlenza , Orazio P. Forlenza , Bryan J. Robbins , Phong T. Tran
发明人： Donato O. Forlenza , Orazio P. Forlenza , Bryan J. Robbins , Phong T. Tran
IPC分类号： G01R31/28
CPC分类号： G01R31/318533
摘要： A method for performing a logical built-in self-test of an integrated circuit is disclosed. The method includes performing a flush and scan test to determine whether the scan chains function correctly. If one of the scan chains does not function correctly, the logical built-in self-test is terminated. If each of the scan chains functions correctly, a structural test of the design-for-test logic supporting LBIST is performed to determine whether the LBIST design-for-test logic functions correctly. If the LBIST design-for-test logic does not function correctly, the logical built-in self-test is terminated. If the LBIST design-for-test logic functions correctly, a level sensitive scan design test of the functional combinational logic is performed using the logic supporting LBIST design-for-test to determine if the integrated circuit functions correctly.
摘要翻译：公开了一种用于执行集成电路的逻辑内置自检的方法。该方法包括执行刷新和扫描测试以确定扫描链是否正常工作。如果其中一个扫描链无法正常工作，则逻辑内置自检终止。如果每个扫描链都正常工作，则执行支持LBIST的测试用设计逻辑的结构测试，以确定LBIST设计测试逻辑是否正确运行。如果LBIST设计测试逻辑不能正常工作，则逻辑内置自检终止。如果LBIST设计测试逻辑正常工作，则使用支持LBIST设计测试的逻辑执行功能组合逻辑的电平敏感扫描设计测试，以确定集成电路是否正常工作。

3. 发明授权

US07395470B2 Method, apparatus, and computer program product for diagnosing a scan chain failure employing fuses coupled to the scan chain 失效
公开(公告)号：US07395470B2
公开(公告)日：2008-07-01
申请号：US11149483
申请日：2005-06-09
申请人： Todd M. Burdine , Donato O. Forlenza , Orazio P. Forlenza , William J. Hurley , Phong T. Tran
发明人： Todd M. Burdine , Donato O. Forlenza , Orazio P. Forlenza , William J. Hurley , Phong T. Tran
IPC分类号： G01R31/28
CPC分类号： G06F11/2215
摘要： A method, apparatus and computer program product are provided implementing a scan chain diagnostics technique. The diagnostics technique includes employing fuses coupled to latches of the scan chain to load a known logic value into the latches at known locations of the scan chain, and then unloading values from the scan chain, and if the scan chain is defective (for example, based on the unloaded logic values), then localizing a defect in the scan chain from the unloaded logic values by comparison thereof with the known locations of the latches of the scan chain loaded with the known logic value via the fuses. The scan chain may be predesigned with fuses spaced periodically across the chain every n latches to facilitate subsequent localization of a detected defect in the scan chain.

4. 发明授权

US07930601B2 AC ABIST diagnostic method, apparatus and program product 失效
标题翻译： AC ABIST诊断方法，仪器和程序产品
公开(公告)号：US07930601B2
公开(公告)日：2011-04-19
申请号：US12035515
申请日：2008-02-22
申请人： Joseph Eckelman , Donato O. Forlenza , Orazio P. Forlenza , William J. Hurley , Thomas J. Knips , Gary William Maier , Phong T. Tran
发明人： Joseph Eckelman , Donato O. Forlenza , Orazio P. Forlenza , William J. Hurley , Thomas J. Knips , Gary William Maier , Phong T. Tran
IPC分类号： G11C29/00
CPC分类号： G11C29/14 , G11C29/12015 , G11C29/56012 , G11C2029/0405
摘要： A method for implementing at speed bit fail mapping of an embedded memory system having ABIST (Array Built In Self Testing), comprises using a high speed multiplied clock which is a multiple of an external clock of an external tester to sequence ABIST bit fail testing of the embedded memory system. Collect store fail data during ABIST testing of the embedded memory system. Perform a predetermined number of ABIST runs before issuing a bypass order substituting the external clock for the high speed multiplied clock. Use the external clock of the tester to read bit fail data out to the external tester.
摘要翻译：一种用于实现具有ABIST（Array Built In Self Testing阵列）的嵌入式存储器系统的速率位故障映射的方法，包括使用作为外部测试器的外部时钟的倍数的高速倍增时钟来对ABIST位故障测试进行排序嵌入式内存系统。在嵌入式存储系统的ABIST测试期间收集存储失败数据。在发出旁路命令之前，执行预定数量的ABIST运行，将外部时钟替换为高速倍增时钟。使用测试仪的外部时钟将位故障数据读出外部测试仪。

5. 发明申请

US20090210763A1 Automated System and Processing for Expedient Diagnosis of Broken Shift Registers Latch Chains Using JTAG 有权
标题翻译：自动系统和处理，以便使用JTAG来切换移位寄存器锁存链
公开(公告)号：US20090210763A1
公开(公告)日：2009-08-20
申请号：US12032655
申请日：2008-02-16
申请人： Joseph Eckelman , Donato O. Forlenza , Orazio P. Forlenza , Robert B. Gass , Phong T. Tran
发明人： Joseph Eckelman , Donato O. Forlenza , Orazio P. Forlenza , Robert B. Gass , Phong T. Tran
IPC分类号： G01R31/3187 , G06F11/00
CPC分类号： G01R31/318544 , G01R31/318536
摘要： This invention involves the use of the JTAG functional test patterns and exercisors to solve the problem of diagnosing broken scan chains in either a serial or a lateral broadside insertion manner across all latch system ports and to analyze the response data efficiently for the purpose of readily identifying switching and non-switching latches with the next to last non-switching latch being the point of the break within a defective scan chain(s). This comprehensive latch perturbation, in conjunction with iterative diagnostic algorithms is used to identify and to pinpoint the defective location in such a broken scan chain(s). This JTAG Functional test function and the JTAG test patterns ultimately derived therefrom, can take on different forms and origins, some external to a product and some internal to a product.
摘要翻译：本发明涉及使用JTAG功能测试模式和执行者来解决在所有锁存系统端口中以串行或侧向宽边插入方式诊断断层扫描链的问题，并且有效地分析响应数据以便容易地识别切换和非切换锁存器与下一个最后一个非切换锁存器是故障扫描链中的断点。这种综合的锁定扰动结合迭代诊断算法用于识别并确定在这种断开的扫描链中的有缺陷的位置。这种JTAG功能测试功能和最终从其导出的JTAG测试模式可以承载不同的形式和起源，一些产品外部和产品内部。

6. 发明授权

US07908532B2 Automated system and processing for expedient diagnosis of broken shift registers latch chains 有权
标题翻译：自动化系统和处理方便诊断破碎的移位寄存器锁链
公开(公告)号：US07908532B2
公开(公告)日：2011-03-15
申请号：US12032655
申请日：2008-02-16
申请人： Joseph Eckelman , Donato O. Forlenza , Orazio P. Forlenza , Robert B. Gass , Phong T. Tran
发明人： Joseph Eckelman , Donato O. Forlenza , Orazio P. Forlenza , Robert B. Gass , Phong T. Tran
IPC分类号： G01R31/28
CPC分类号： G01R31/318544 , G01R31/318536
摘要： This invention involves the use of the JTAG functional test patterns and exercisors to solve the problem of diagnosing broken scan chains in either a serial or a lateral broadside insertion manner across all latch system ports and to analyze the response data efficiently for the purpose of readily identifying switching and non-switching latches with the next to last non-switching latch being the point of the break within a defective scan chain(s). This comprehensive latch perturbation, in conjunction with iterative diagnostic algorithms is used to identify and to pinpoint the defective location in such a broken scan chain(s). This JTAG Functional test function and the JTAG test patterns ultimately derived therefrom, can take on different forms and origins, some external to a product and some internal to a product.
摘要翻译：本发明涉及使用JTAG功能测试模式和执行者来解决在所有锁存系统端口中以串行或侧向宽边插入方式诊断断层扫描链的问题，并且有效地分析响应数据以便容易地识别切换和非切换锁存器与下一个最后一个非切换锁存器是故障扫描链中的断点。这种综合的锁定扰动结合迭代诊断算法用于识别并确定在这种断开的扫描链中的有缺陷的位置。这种JTAG功能测试功能和最终从其导出的JTAG测试模式可以承载不同的形式和起源，一些产品外部和产品内部。

7. 发明申请

US20090217112A1 AC ABIST Diagnostic Method, Apparatus and Program Product 失效
标题翻译： AC ABIST诊断方法，仪器和程序产品
公开(公告)号：US20090217112A1
公开(公告)日：2009-08-27
申请号：US12035515
申请日：2008-02-22
申请人： Joseph Eckelman , Donato O. Forlenza , Orazio P. Forlenza , William J. Hurley , Thomas J. Knips , Gary William Maier , Phong T. Tran
发明人： Joseph Eckelman , Donato O. Forlenza , Orazio P. Forlenza , William J. Hurley , Thomas J. Knips , Gary William Maier , Phong T. Tran
IPC分类号： G11C29/12 , G06F11/27
CPC分类号： G11C29/14 , G11C29/12015 , G11C29/56012 , G11C2029/0405
摘要： A method for implementing at speed bit fail mapping of an embedded memory system having ABIST (Array Built In Self Testing), comprises using a high speed multiplied clock which is a multiple of an external clock of an external tester to sequence ABIST bit fail testing of the embedded memory system. Collect store fail data during ABIST testing of the embedded memory system. Perform a predetermined number of ABIST runs before issuing a bypass order substituting the external clock for the high speed multiplied clock. Use the external clock of the tester to read bit fail data out to the external tester.
摘要翻译：一种用于实现具有ABIST（Array Built In Self Testing阵列）的嵌入式存储器系统的速率位故障映射的方法，包括使用作为外部测试器的外部时钟的倍数的高速倍增时钟来对ABIST位故障测试进行排序嵌入式内存系统。在嵌入式存储系统的ABIST测试期间收集存储失败数据。在发出旁路命令之前，执行预定数量的ABIST运行，将外部时钟替换为高速倍增时钟。使用测试仪的外部时钟将位故障数据读出外部测试仪。

8. 发明申请

US20090210761A1 AC Scan Diagnostic Method and Apparatus Utilizing Functional Architecture Verification Patterns 审中-公开
标题翻译： AC扫描诊断方法和利用功能体系结构验证模式的设备
公开(公告)号：US20090210761A1
公开(公告)日：2009-08-20
申请号：US12031930
申请日：2008-02-15
申请人： Donato O. Forlenza , Orazio P. Forlenza , Phong T. Tran
发明人： Donato O. Forlenza , Orazio P. Forlenza , Phong T. Tran
IPC分类号： G06F11/25 , G06F11/27 , G06F11/263
CPC分类号： G06F11/267 , G01R31/318544
摘要： A method, apparatus and computer program product are provided for implementing AC scan diagnostic of delay and AC scan chain defects in an integrated circuit chip under test using Functional Architecture Verification Patterns (AVPs) for enabling rapidly localizing identified defects to a failing Shift Register Latch (SRL). An Architecture Verification Pattern (AVP) test pattern set is generated using a chip design input and simulation. AVP test vectors are applied for starting chip clocks and initiating testing, such as Logic Built-In-Self-Test (LBIST).
摘要翻译：提供了一种方法，装置和计算机程序产品，用于实现使用功能架构验证模式（AVP）的待测集成电路芯片中的延迟和AC扫描链缺陷的AC扫描诊断，以使快速定位故障移位寄存器锁存器 SRL）。使用芯片设计输入和仿真生成架构验证模式（AVP）测试模式集。应用AVP测试矢量启动芯片时钟并启动测试，如逻辑内置自检（LBIST）。

9. 发明授权

US07392449B2 Method, apparatus, and computer program product for diagnosing a scan chain failure employing fuses coupled to the scan chain 失效
标题翻译：用于使用耦合到扫描链的保险丝诊断扫描链故障的方法，装置和计算机程序产品
公开(公告)号：US07392449B2
公开(公告)日：2008-06-24
申请号：US11956480
申请日：2007-12-14
申请人： Todd M. Burdine , Donato O. Forlenza , Orazio P. Forlenza , William J. Hurley , Phong T. Tran
发明人： Todd M. Burdine , Donato O. Forlenza , Orazio P. Forlenza , William J. Hurley , Phong T. Tran
IPC分类号： G01R31/28
CPC分类号： G06F11/2215
摘要： A method, apparatus and computer program product are provided implementing a scan chain diagnostics technique. The diagnostics technique includes employing fuses coupled to latches of the scan chain to load a known logic value into the latches at known locations of the scan chain, and then unloading values from the scan chain, and if the scan chain is defective (for example, based on the unloaded logic values), then localizing a defect in the scan chain from the unloaded logic values by comparison thereof with the known locations of the latches of the scan chain loaded with the known logic value via the fuses. The scan chain may be predesigned with fuses spaced periodically across the chain every n latches to facilitate subsequent localization of a detected defect in the scan chain.
摘要翻译：提供了实现扫描链诊断技术的方法，装置和计算机程序产品。诊断技术包括使用耦合到扫描链的锁存器的熔丝将已知逻辑值加载到扫描链的已知位置处的锁存器中，然后从扫描链中卸载值，并且如果扫描链有缺陷（例如，基于卸载的逻辑值），然后通过与已加载逻辑值的扫描链中的缺陷通过经由保险丝加载了已知逻辑值的扫描链的锁存器的已知位置进行比较来定位扫描链中的缺陷。可以使用每n个锁存器在链上周期性间隔的保险丝对扫描链进行预先设计，以便于扫描链中检测到的缺陷的随后定位。

10. 发明授权

US07117415B2 Automated BIST test pattern sequence generator software system and method 失效
标题翻译：自动BIST测试模式序列发生器软件系统及方法
公开(公告)号：US07117415B2
公开(公告)日：2006-10-03
申请号：US10757781
申请日：2004-01-15
申请人： Donato O. Forlenza , Orazio P. Forlenza , William J. Hurley , Bryan J. Robbins
发明人： Donato O. Forlenza , Orazio P. Forlenza , William J. Hurley , Bryan J. Robbins
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/318371 , G01R31/318342
摘要： Methods and systems for reducing the volume of test data associated with built in self testing (BIST) test methodologies (e.g., logical BIST, array BIST, etc.) and pattern structures are provided. Embodiments of the present invention store a limited number of “dynamic” test parameters for each test sequence that have changed relative to a previous test sequence.
摘要翻译：提供了用于减少与内置自检（BIST）测试方法（例如，逻辑BIST，阵列BIST等）和模式结构相关联的测试数据量的方法和系统。本发明的实施例存储针对相对于先前测试序列而改变的每个测试序列的有限数量的“动态”测试参数。

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