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1. 发明授权

US08386230B2 Circuit design optimization 失效
标题翻译：电路设计优化
公开(公告)号：US08386230B2
公开(公告)日：2013-02-26
申请号：US12858562
申请日：2010-08-18
申请人： Samuel I. Ward , Kevin F. Reick , Bryan J. Robbins , Thomas E. Rosser , Robert J. Shadowen
发明人： Samuel I. Ward , Kevin F. Reick , Bryan J. Robbins , Thomas E. Rosser , Robert J. Shadowen
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/14
摘要： A method includes generating a first behavioral model of a circuit, the first behavioral model describing a physical circuit in a first configuration. The first configuration comprises a first logic structure configured to generate a first intermediate signal based on a received first plurality of inputs. The first configuration further comprises a logic cone configured to generate a scan output based on the first intermediate signal and a plurality of scan inputs. The first behavioral model is modified to generate a second behavioral model describing the physical circuit in a second configuration. The second configuration comprises an error circuit configured to receive the scan output and the first intermediate signal. A testability model is generated based on the second behavioral model, the testability model comprising a first structural representation of the first logic structure. In the event the first logic structure causes a coverage problem, the testability model is modified to include an inversion structure. The inversion structure is configured based on the first logic structure. The inversion structure is configured to generate an inversion structure output. The testability model is modified to couple the inversion structure output as an input to the error circuit.
摘要翻译：一种方法包括生成电路的第一行为模型，第一行为模型描述第一配置中的物理电路。第一配置包括被配置为基于接收的第一多个输入生成第一中间信号的第一逻辑结构。第一配置还包括被配置为基于第一中间信号和多个扫描输入产生扫描输出的逻辑锥。修改第一行为模型以产生描述第二配置中的物理电路的第二行为模型。第二配置包括被配置为接收扫描输出和第一中间信号的误差电路。基于第二行为模型生成可测试性模型，可测性模型包括第一逻辑结构的第一结构表示。在第一逻辑结构引起覆盖问题的情况下，可修改性模型被修改为包括反演结构。基于第一逻辑结构配置反转结构。反演结构被配置为产生反演结构输出。修改可测试性模型，将反演结构输出作为输入耦合到误差电路。

2. 发明申请

US20120046921A1 CIRCUIT DESIGN OPTIMIZATION 失效
标题翻译：电路设计优化
公开(公告)号：US20120046921A1
公开(公告)日：2012-02-23
申请号：US12858562
申请日：2010-08-18
申请人： Samuel I. Ward , Kevin F. Reick , Bryan J. Robbins , Thomas E. Rosser , Robert J. Shadowen
发明人： Samuel I. Ward , Kevin F. Reick , Bryan J. Robbins , Thomas E. Rosser , Robert J. Shadowen
IPC分类号： G06F17/10
CPC分类号： G06F17/5045 , G06F2217/14
摘要： A method includes generating a first behavioral model of a circuit, the first behavioral model describing a physical circuit in a first configuration. The first configuration comprises a first logic structure configured to generate a first intermediate signal based on a received first plurality of inputs. The first configuration further comprises a logic cone configured to generate a scan output based on the first intermediate signal and a plurality of scan inputs. The first behavioral model is modified to generate a second behavioral model describing the physical circuit in a second configuration. The second configuration comprises an error circuit configured to receive the scan output and the first intermediate signal. A testability model is generated based on the second behavioral model, the testability model comprising a first structural representation of the first logic structure. In the event the first logic structure causes a coverage problem, the testability model is modified to include an inversion structure. The inversion structure is configured based on the first logic structure. The inversion structure is configured to generate an inversion structure output. The testability model is modified to couple the inversion structure output as an input to the error circuit.
摘要翻译：一种方法包括生成电路的第一行为模型，第一行为模型描述第一配置中的物理电路。第一配置包括被配置为基于接收的第一多个输入生成第一中间信号的第一逻辑结构。第一配置还包括被配置为基于第一中间信号和多个扫描输入产生扫描输出的逻辑锥。修改第一行为模型以产生描述第二配置中的物理电路的第二行为模型。第二配置包括被配置为接收扫描输出和第一中间信号的误差电路。基于第二行为模型生成可测试性模型，可测性模型包括第一逻辑结构的第一结构表示。在第一逻辑结构引起覆盖问题的情况下，可修改性模型被修改为包括反演结构。基于第一逻辑结构配置反转结构。反演结构被配置为产生反演结构输出。修改可测试性模型，将反演结构输出作为输入耦合到误差电路。

3. 发明授权

US08443313B2 Circuit design optimization 失效
标题翻译：电路设计优化
公开(公告)号：US08443313B2
公开(公告)日：2013-05-14
申请号：US12858522
申请日：2010-08-18
申请人： Samuel I. Ward , Kevin F. Reick , Bryan J. Robbins , Thomas E. Rosser , Robert J. Shadowen
发明人： Samuel I. Ward , Kevin F. Reick , Bryan J. Robbins , Thomas E. Rosser , Robert J. Shadowen
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A method comprises generating a first behavioral model of a circuit describing a physical circuit in a first configuration. The first configuration comprises a first master latch, a first fanout path, and a logic cone. The first master latch couples to the first fanout path and is configured to receive a first data input signal. The first fanout path comprises a plurality of output sinks, each coupled to the logic cone. The first behavioral model is modified to generate a second behavioral model describing the physical circuit in a second configuration. The second configuration comprises an error circuit and an abstract latch clone based on the first master latch. A configuration file is generated based on the second behavioral model. The configuration file comprises information representing a plurality of instantiated latch clones based on the abstract latch clone, each configured to couple to the first data input signal and to one or more output sinks of the plurality of output sinks. The second behavioral model and the configuration file are together configured for input to a synthesis tool.
摘要翻译：一种方法包括生成描述第一配置中的物理电路的电路的第一行为模型。第一配置包括第一主锁存器，第一扇出通路和逻辑锥。第一主锁存器耦合到第一扇出通道并被配置为接收第一数据输入信号。第一扇出路径包括多个输出接收器，每个输出接收器耦合到逻辑锥。修改第一行为模型以产生描述第二配置中的物理电路的第二行为模型。第二配置包括基于第一主锁存器的错误电路和抽象锁存器克隆。基于第二行为模型生成配置文件。配置文件包括基于抽象锁存克隆的表示多个实例化锁存克隆的信息，每个被配置为耦合到第一数据输入信号和多个输出汇的一个或多个输出汇。第二行为模型和配置文件一起配置为输入到综合工具。

4. 发明申请

US20120047476A1 CIRCUIT DESIGN OPTIMIZATION 失效
标题翻译：电路设计优化
公开(公告)号：US20120047476A1
公开(公告)日：2012-02-23
申请号：US12858522
申请日：2010-08-18
申请人： Samuel I. Ward , Kevin F. Reick , Bryan J. Robbins , Thomas E. Rosser , Robert J. Shadowen
发明人： Samuel I. Ward , Kevin F. Reick , Bryan J. Robbins , Thomas E. Rosser , Robert J. Shadowen
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A method comprises generating a first behavioral model of a circuit describing a physical circuit in a first configuration. The first configuration comprises a first master latch, a first fanout path, and a logic cone. The first master latch couples to the first fanout path and is configured to receive a first data input signal. The first fanout path comprises a plurality of output sinks, each coupled to the logic cone. The first behavioral model is modified to generate a second behavioral model describing the physical circuit in a second configuration. The second configuration comprises an error circuit and an abstract latch clone based on the first master latch. A configuration file is generated based on the second behavioral model. The configuration file comprises information representing a plurality of instantiated latch clones based on the abstract latch clone, each configured to couple to the first data input signal and to one or more output sinks of the plurality of output sinks. The second behavioral model and the configuration file are together configured for input to a synthesis tool.
摘要翻译：一种方法包括生成描述第一配置中的物理电路的电路的第一行为模型。第一配置包括第一主锁存器，第一扇出通路和逻辑锥。第一主锁存器耦合到第一扇出通道并被配置为接收第一数据输入信号。第一扇出路径包括多个输出接收器，每个输出接收器耦合到逻辑锥。修改第一行为模型以产生描述第二配置中的物理电路的第二行为模型。第二配置包括基于第一主锁存器的错误电路和抽象锁存器克隆。基于第二行为模型生成配置文件。配置文件包括基于抽象锁存克隆的表示多个实例化锁存克隆的信息，每个被配置为耦合到第一数据输入信号和多个输出汇的一个或多个输出汇。第二行为模型和配置文件一起配置为输入到综合工具。

5. 发明授权

US5524082A Redundancy removal using quasi-algebraic methods 失效
标题翻译：使用准代数方法进行冗余删除
公开(公告)号：US5524082A
公开(公告)日：1996-06-04
申请号：US723121
申请日：1991-06-28
申请人： Paul W. Horstmann , Thomas E. Rosser , Prashant S. Sawkar
发明人： Paul W. Horstmann , Thomas E. Rosser , Prashant S. Sawkar
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A method is provided to remove redundancies in multi-level logic networks caused by reconverging signals at Boolean sum and product nodes. Generally, sum and product nodes which have potential redundancies are first identified. For each reconvergent signal at each of the nodes, it is determined whether it introduces redundancies using nondestructive Boolean analysis. No two-level expansion is made of the logic network. Moreover, for each confirmed redundancy, a redundant term is identified using Boolean analysis. Finally, the redundancy is removed, if desirable.
摘要翻译：提供了一种方法，用于消除由布尔和和乘积节点重新收敛信号引起的多级逻辑网络中的冗余。通常，首先确定具有潜在冗余度的总和和产品节点。对于每个节点的每个再生信号，确定是否使用非破坏性布尔分析引入冗余。逻辑网络没有两级扩展。此外，对于每个确认的冗余，使用布尔分析来识别冗余项。最后，如果需要，冗余被去除。

6. 发明申请

US20100175038A1 Techniques for Implementing an Engineering Change Order in an Integrated Circuit Design 审中-公开
标题翻译：在集成电路设计中实施工程变更订单的技术
公开(公告)号：US20100175038A1
公开(公告)日：2010-07-08
申请号：US12349289
申请日：2009-01-06
申请人： Jeremy T. Hopkins , Thomas E. Rosser
发明人： Jeremy T. Hopkins , Thomas E. Rosser
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/504
摘要： A technique for implementing an engineering change order (ECO) includes comparing a first hardware description language (HDL) design with a second HDL design. In this case, the second HDL design corresponds to the first HDL design with at least one implemented ECO. The technique identifies differences in latch points, primary inputs, and primary outputs between the first and second HDL designs. The second HDL design is converted to a non-optimized netlist. Logical cones (cones of logic) that feed the latch points, the primary inputs, and the primary outputs are extracted from the non-optimized netlist. Based on the extracted logical cones and the non-optimized netlist, a physical implementation of the second HDL design is synthesized.
摘要翻译：实现工程变更单（ECO）的技术包括将第一硬件描述语言（HDL）设计与第二HDL设计进行比较。在这种情况下，第二HDL设计对应于具有至少一个实现的ECO的第一HDL设计。该技术识别第一和第二HDL设计之间的锁存点，主输入和主输出的差异。第二个HDL设计被转换为非优化的网表。从非优化网表中提取提供锁存点，主输入和主输出的逻辑锥（逻辑锥）。基于提取的逻辑锥和非优化网表，合成了第二HDL设计的物理实现。

7. 发明申请

US20090013206A1 Efficient Utilization of a Multi-Source Network of Control Logic to Achieve Timing Closure in a Clocked Logic Circuit 有权
标题翻译：控制逻辑的多源网络的高效利用在时钟逻辑电路中实现定时闭合
公开(公告)号：US20090013206A1
公开(公告)日：2009-01-08
申请号：US11772908
申请日：2007-07-03
申请人： Lawrence D. Curley , John M. Isakson , Arjen Mets , Travis W. Pouarz , Thomas E. Rosser , Kristen M. Tucker
发明人： Lawrence D. Curley , John M. Isakson , Arjen Mets , Travis W. Pouarz , Thomas E. Rosser , Kristen M. Tucker
IPC分类号： G06F1/14
CPC分类号： G06F17/505 , G06F2217/62
摘要： A method, system, and computer program product are provided for achieving timing closure in a clocked logic circuit. For each local clock buffer in a set of local clock buffers, a logic synthesis tool determines a clock control signal input from a set of clock control signal inputs that will drive a clock control signal to the local clock buffer at a target frequency such that a first timing constraint may be met. The operation performed by the logic synthesis tool forms a determined clock control signal input. Responsive to the logic synthesis tool determining the determined clock control signal input, the logic synthesis tool couples the local clock buffer to the determined clock control signal input that drives the clock control signal to the local clock buffer at the target frequency to achieve timing closure in the clocked logic circuit.
摘要翻译：提供了一种方法，系统和计算机程序产品，用于实现时钟逻辑电路中的定时关闭。对于一组本地时钟缓冲器中的每个本地时钟缓冲器，逻辑综合工具确定从一组时钟控制信号输入端输入的时钟控制信号，该时钟控制信号输入将以目标频率将时钟控制信号驱动到本地时钟缓冲器，可以满足第一时间约束。由逻辑综合工具执行的操作形成确定的时钟控制信号输入。响应于确定所确定的时钟控制信号输入的逻辑综合工具，逻辑综合工具将本地时钟缓冲器耦合到所确定的时钟控制信号输入端，该时钟控制信号输入以目标频率驱动时钟控制信号到本地时钟缓冲器，以实现定时闭合时钟逻辑电路。

8. 发明申请

US20130080989A1 SPARE LATCH DISTRIBUTION 失效
标题翻译：备用分配
公开(公告)号：US20130080989A1
公开(公告)日：2013-03-28
申请号：US13246038
申请日：2011-09-27
申请人： George Antony , Sridhar H. Rangarajan , Thomas E. Rosser
发明人： George Antony , Sridhar H. Rangarajan , Thomas E. Rosser
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F2217/72
摘要： Aspects of the invention provide for spare latch distribution for an integrated circuit design. In one embodiment, aspects of the invention include a method of generating a computer system for spare latch distribution in an integration circuit design, the method including: providing a computer system operable to: receive design data for the integrated circuit design, the design data including a plurality of latches; segment the integrated circuit design into a plurality of equal sections; determine a latch density within each of the equal sections; and determine a number of spare latches, based on the latch density, for each of the equal sections. Further, it is understood that the above are performed for each clock domain within the integrated circuit design.
摘要翻译：本发明的方面提供用于集成电路设计的备用锁存器分配。在一个实施例中，本发明的方面包括在集成电路设计中产生用于备用锁存器分配的计算机系统的方法，所述方法包括：提供计算机系统，其可操作以：接收所述集成电路设计的设计数据，所述设计数据包括多个闩锁; 将集成电路设计分段成多个相等的部分; 确定每个相等部分内的锁存密度; 并且基于每个相等部分的锁存密度来确定多个备用锁存器。此外，应当理解，在集成电路设计中对于每个时钟域执行上述操作。

9. 发明授权

US08166439B2 Techniques for selecting spares to implement a design change in an integrated circuit 有权
标题翻译：选择备件以实现集成电路中的设计变更的技术
公开(公告)号：US08166439B2
公开(公告)日：2012-04-24
申请号：US11966043
申请日：2007-12-28
申请人： Jeremy T. Hopkins , Thomas E. Rosser
发明人： Jeremy T. Hopkins , Thomas E. Rosser
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/72
摘要： A technique for implementing an engineering change order includes determining spares that are available to implement a modification to a circuit design. One of the available spares is then selected to implement the modification to the circuit design based on performance criteria associated with each of the available spares.
摘要翻译：实现工程变更订单的技术包括确定可用于实现对电路设计的修改的备件。然后选择一个可用备件，以根据与每个可用备件相关联的性能标准来实现对电路设计的修改。

10. 发明授权

US07979819B2 Minterm tracing and reporting 有权
标题翻译： Minterm跟踪和报告
公开(公告)号：US07979819B2
公开(公告)日：2011-07-12
申请号：US12358793
申请日：2009-01-23
申请人： Jeremy T. Hopkins , Thomas E. Rosser
发明人： Jeremy T. Hopkins , Thomas E. Rosser
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Disclosed are a method, a system and a computer program product for determining and reporting minterms to aid in implementing an engineering change order (ECO). A Minterm Tracing and Reporting (MTR) utility, which executes on a computer system, receives two or more timing points of an optimized netlist, where one or more of the two or more timing points are received from one or more of a user, a memory medium, and/or a network. For example, a timing point is a primary input, a primary output, or a latch point. After receiving the two or more timing points of the optimized netlist, the MTR utility determines two or more minterms of the optimized netlist. In determining the minterms, from one timing point to a next timing point: a polarity at the timing point may be determined, and a forward trace from the timing point to the next timing point is performed to determine the two or more minterms of the optimized netlist. In the forward trace from the timing point to the next timing point, the MTR utility determines two or more logical cones and one or more intersections of the logical cones. The MTR utility reports (e.g., communicates) each of the determined minterms, the determined polarities, and the one or more intersections of logical cones to one or more of a computer-executable application, a network, a memory medium, and/or a display.
摘要翻译：公开了一种方法，系统和计算机程序产品，用于确定和报告子项以帮助实施工程变更单（ECO）。在计算机系统上执行的Minterm跟踪和报告（MTR）实用程序接收优化网表的两个或更多个定时点，其中两个或多个定时点中的一个或多个从用户的一个或多个接收，存储介质和/或网络。例如，定时点是主输入，主输出或锁存点。在接收到优化网表的两个或多个时间点之后，MTR实用程序确定优化网表的两个或更多个minterms。在从一个定时点到下一个定时点的确定中，可以确定定时点处的极性，并且执行从定时点到下一定时点的前向跟踪，以确定优化的时间点的两个或更多个小区网表。在从定时点到下一定时点的前向跟踪中，MTR实用程序确定逻辑锥的两个或更多个逻辑锥和一个或多个交集。 MTR实用程序将计算机可执行应用程序，网络，存储介质和/或其中的一个或多个报告（例如，通信）所确定的最小值，所确定的极性以及逻辑锥的一个或多个交叉点显示。

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