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1. 发明授权

US07415378B2 Methods for analyzing critical defects in analog integrated circuits 有权
标题翻译：分析模拟集成电路中的关键缺陷的方法
公开(公告)号：US07415378B2
公开(公告)日：2008-08-19
申请号：US11048027
申请日：2005-01-31
申请人： Martin B. Mollat , Milind V. Khandekar , Tony T. Phan , Kyle M. Flessner
发明人： Martin B. Mollat , Milind V. Khandekar , Tony T. Phan , Kyle M. Flessner
IPC分类号： G06F19/00
CPC分类号： G01R31/2894 , G01R31/311
摘要： The present invention provides a method for analyzing critical defects in analog integrated circuits. The method for analyzing critical defects, among other possible steps, may include fault testing a power field effect transistor (120) portion of an analog integrated circuit (115) to obtain electrical failure data. The method may further include performing an in-line optical inspection of the analog integrated circuit (115) to obtain physical defect data, and correlating the electrical failure data and physical defect data to analyze critical defects.
摘要翻译：本发明提供了一种用于分析模拟集成电路中的关键缺陷的方法。用于分析关键缺陷的方法以及其他可能的步骤可以包括对模拟集成电路（115）的功率场效应晶体管（120）部分进行故障测试以获得电气故障数据。该方法还可以包括执行模拟集成电路（115）的在线光学检查以获得物理缺陷数据，以及将电故障数据和物理缺陷数据相关联以分析关键缺陷。

2. 发明授权

US07262109B2 Integrated circuit having a transistor level top side wafer contact and a method of manufacture therefor 有权
公开(公告)号：US07262109B2
公开(公告)日：2007-08-28
申请号：US11196087
申请日：2005-08-03
申请人： John Lin , Tony T. Phan , Philip L. Hower , William C. Loftin , Martin B. Mollat
发明人： John Lin , Tony T. Phan , Philip L. Hower , William C. Loftin , Martin B. Mollat
IPC分类号： H01L21/76
CPC分类号： H01L27/1203 , H01L21/743 , H01L21/84 , H01L23/481 , H01L23/5226 , H01L23/535 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides an integrated circuit and a method of manufacture therefor. The integrated circuit (100), in one embodiment without limitation, includes a dielectric layer (120) located over a wafer substrate (110), and a semiconductor substrate (130) located over the dielectric layer (120), the semiconductor substrate (130) having one or more transistor devices (160) located therein or thereon. The integrated circuit (100) may further include an interconnect (180) extending entirely through the semiconductor substrate (130) and the dielectric layer (120), thereby electrically contacting the wafer substrate (110), and one or more isolation structures (150) extending entirely through the semiconductor substrate (130) to the dielectric layer (120).

3. 发明授权

US07118958B2 Method of manufacturing a metal-insulator-metal capacitor using an etchback process 有权
标题翻译：使用回蚀工艺制造金属 - 绝缘体 - 金属电容器的方法
公开(公告)号：US07118958B2
公开(公告)日：2006-10-10
申请号：US11071036
申请日：2005-03-03
申请人： Tony T. Phan , Martin B. Mollat
发明人： Tony T. Phan , Martin B. Mollat
IPC分类号： H01L21/8242 , H01L29/76
CPC分类号： H01L27/0629 , H01L28/40
摘要： The present invention provides a method for manufacturing a metal-insulator-metal (MIM) capacitor, a method for manufacturing an integrated circuit having a metal-insulator-metal (MIM) capacitor, and an integrated circuit having a metal-insulator-metal (MIM) capacitor. The method for manufacturing the metal-insulator-metal (MIM) capacitor, among other steps and without limitation, includes providing a material layer (185) over a substrate (110), and forming a refractory metal layer (210) having a thickness (t1) over the substrate (110), at least a portion of the refractory metal layer (210) extending over the material layer (185). The method further includes reducing the thickness (t2) of the portion of the refractory metal layer (210) extending over the material layer (185), thereby forming a thinned refractory metal layer (310), and reacting the thinned refractory metal layer (310) with at least a portion of the material layer (185) to form an electrode (440) for use in a capacitor.
摘要翻译：本发明提供一种金属 - 绝缘体 - 金属（MIM）电容器的制造方法，具有金属 - 绝缘体 - 金属（MIM）电容器的集成电路的制造方法和具有金属 - 绝缘体 - 金属 MIM）电容器。金属 - 绝缘体 - 金属（MIM）电容器的制造方法以及其它步骤，但不限于此，包括在衬底（110）上方提供材料层（185），并且形成具有厚度的难熔金属层（210）（110）上的至少一部分难熔金属层（210）延伸到材料层（185）上。该方法还包括减小在材料层（185）上延伸的难熔金属层（210）的部分的厚度（t 2> 2），由此形成变薄的难熔金属层（310），以及使稀薄的难熔金属层（310）与材料层（185）的至少一部分反应以形成用于电容器的电极（440）。

4. 发明授权

US06689668B1 Methods to improve density and uniformity of hemispherical grain silicon layers 失效
标题翻译：提高半球形硅层密度和均匀性的方法
公开(公告)号：US06689668B1
公开(公告)日：2004-02-10
申请号：US09652650
申请日：2000-08-31
申请人： Mohamed el-Hamdi , Tony T. Phan , Luther Hendrix , Bradley T. Moore
发明人： Mohamed el-Hamdi , Tony T. Phan , Luther Hendrix , Bradley T. Moore
IPC分类号： H01L2120
CPC分类号： H01L28/84 , H01L27/10852
摘要： Various methods are provided of forming capacitor electrodes for integrated circuit memory cells in which out-diffusion of dopant from doped silicon layers is controlled by deposition of barrier layers, such as layers of undoped silicon and/or oxide. In one aspect, a method of forming hemispherical grain silicon on a substrate is provided that includes forming a first doped silicon layer on the substrate and a first barrier layer on the doped silicon layer. A hemispherical grain polysilicon source layer is formed on the first barrier layer and a hemispherical grain silicon layer on the hemispherical grain polysilicon source layer. By controlling out-diffusion of dopant, HSG grain size, density and uniformity, as well as DRAM memory cell capacitance, may be enhanced, while at the same time maintaining reactor throughput.
摘要翻译：提供了形成用于集成电路存储单元的电容器电极的各种方法，其中通过沉积阻挡层（例如未掺杂的硅和/或氧化物层）来控制来自掺杂硅层的掺杂剂的外扩散。一方面，提供一种在衬底上形成半球形晶粒硅的方法，其包括在衬底上形成第一掺杂硅层和在掺杂硅层上形成第一势垒层。半球形晶粒多晶硅源层形成在半球形晶粒多晶硅源层上的第一势垒层和半球状晶粒硅层上。通过控制掺杂剂的扩散，可以提高HSG晶粒尺寸，密度和均匀性以及DRAM存储单元电容，同时保持反应器的生产量。

5. 发明授权

US07902055B2 Method of manufacturing a dual metal Schottky diode 有权
标题翻译：制造双金属肖特基二极管的方法
公开(公告)号：US07902055B2
公开(公告)日：2011-03-08
申请号：US11095245
申请日：2005-03-30
申请人： Richard B. Irwin , Tony T. Phan , Hong-Ryong Kim , Ming-Yeh Chuang , Jennifer S. Dumin , Patrick J. Jones , Fredric D. Bailey
发明人： Richard B. Irwin , Tony T. Phan , Hong-Ryong Kim , Ming-Yeh Chuang , Jennifer S. Dumin , Patrick J. Jones , Fredric D. Bailey
IPC分类号： H01L29/872 , H01L29/47
CPC分类号： H01L29/66143 , H01L29/47 , H01L29/872
摘要： An embodiment of the invention is a Schottky diode 22 having a semiconductor substrate 3, a first metal 24, a barrier layer 26, and second metal 28. Another embodiment of the invention is a method of manufacturing a Schottky diode 22 that includes providing a semiconductor substrate 3, forming a barrier layer 26 over the semiconductor substrate 3, forming a first metal layer 23 over the semiconductor substrate 3, annealing the semiconductor substrate 3 to form areas 24 of reacted first metal and areas 23 of un-reacted first metal, and removing selected areas 23 of the un-reacted first metal. The method further includes forming a second metal layer 30 over the semiconductor substrate 3 and annealing the semiconductor substrate 3 to form areas 28 of reacted second metal and areas 30 of un-reacted second metal.
摘要翻译：本发明的一个实施例是具有半导体衬底3，第一金属24，势垒层26和第二金属28的肖特基二极管22.本发明的另一实施例是制造肖特基二极管22的方法，其包括提供半导体衬底3，在半导体衬底3上形成阻挡层26，在半导体衬底3上形成第一金属层23，退火半导体衬底3，形成反应的第一金属的区域24和未反应的第一金属的区域23;以及去除未反应的第一金属的选定区域23。该方法还包括在半导体衬底3上形成第二金属层30并退火半导体衬底3以形成反应的第二金属的区域28和未反应的第二金属的区域30。

6. 发明授权

US06972470B2 Dual metal Schottky diode 有权
标题翻译：双金属肖特基二极管
公开(公告)号：US06972470B2
公开(公告)日：2005-12-06
申请号：US10814673
申请日：2004-03-30
申请人： Richard B. Irwin , Tony T. Phan , Hong-Ryong Kim , Ming-Yeh Chuang , Jennifer S. Dumin , Patrick J. Jones , Fredric D. Bailey
发明人： Richard B. Irwin , Tony T. Phan , Hong-Ryong Kim , Ming-Yeh Chuang , Jennifer S. Dumin , Patrick J. Jones , Fredric D. Bailey
IPC分类号： H01L21/20 , H01L21/329 , H01L29/47 , H01L29/80 , H01L29/872 , H01L29/93 , H01L31/112 , H01L27/95
CPC分类号： H01L29/66143 , H01L29/47 , H01L29/872
摘要： An embodiment of the invention is a Schottky diode 22 having a semiconductor substrate 3, a first metal 24, a barrier layer 26, and second metal 28. Another embodiment of the invention is a method of manufacturing a Schottky diode 22 that includes providing a semiconductor substrate 3, forming a barrier layer 26 over the semiconductor substrate 3, forming a first metal layer 23 over the semiconductor substrate 3, annealing the semiconductor substrate 3 to form areas 24 of reacted first metal and areas 23 of un-reacted first metal, and removing selected areas 23 of the un-reacted first metal. The method further includes forming a second metal layer 30 over the semiconductor substrate 3 and annealing the semiconductor substrate 3 to form areas 28 of reacted second metal and areas 30 of un-reacted second metal.
摘要翻译：本发明的实施例是具有半导体衬底3，第一金属24，阻挡层26和第二金属28的肖特基二极管22。本发明的另一实施例是制造肖特基二极管22的方法，其包括提供半导体衬底3，在半导体衬底3上形成阻挡层26，在半导体衬底3上方形成第一金属层23，退火半导体衬底3 以形成反应的第一金属的区域24和未反应的第一金属的区域23，并且去除未反应的第一金属的选定区域23。该方法还包括在半导体衬底3上形成第二金属层30并退火半导体衬底3以形成反应的第二金属的区域28和未反应的第二金属的区域30。

7. 发明授权

US07593923B1 Functional operations for accessing and/or building interlocking trees datastores to enable their use with applications software 有权
标题翻译：用于访问和/或构建互锁树数据存储的功能操作，以使其能够与应用软件一起使用
公开(公告)号：US07593923B1
公开(公告)日：2009-09-22
申请号：US10879329
申请日：2004-06-29
申请人： Jane Campbell Mazzagatti , Jane Van Keuren Claar , Tony T. Phan
发明人： Jane Campbell Mazzagatti , Jane Van Keuren Claar , Tony T. Phan
IPC分类号： G06F17/30
CPC分类号： G06N5/022 , G06F17/30327 , Y10S707/99933
摘要： A set of mechanisms handles communication with a Knowledge Store and its K Engine(s). The Knowledge Store (Kstore) does not need indexes or tables to support it but instead is formed by the construction of interlocking trees of pointers in nodes of the interlocking trees. The K Engine builds and is used to query a KStore by using threads that use software objects together with a K Engine to learn particlized events, thus building the KStore, and these or other software objects can be used to make queries and get answers from the KStore, usually with the help of a K Engine. Under some circumstances, information can be obtained directly from the KStore, but is generally only available through the actions of the K Engine. The mechanisms provide communications pathways for users and applications software to build and/or query the KStore. Both these processes can proceed simultaneously, and in multiple instances. There can be a plurality of engines operating on a KStore essentially simultaneously. Additionally a mechanism for providing triggers allows for automatic reporting of events, conditions and occurrences to users and applications.
摘要翻译：一组机制处理与知识库及其K引擎的通信。知识库（Kstore）不需要索引或表来支持它，而是通过在互锁树的节点中构建指针的互锁树形成。 K引擎构建并用于通过使用与K引擎一起使用软件对象的线程来查询KStore来学习特定事件，从而构建KStore，并且可以使用这些或其他软件对象进行查询并从 KStore，通常在K引擎的帮助下。在某些情况下，可以直接从KStore获得信息，但通常只能通过K Engine的操作获得。这些机制为用户和应用软件提供了构建和/或查询KStore的通信路径。这两个过程可以同时进行，并且在多个情况下。基本上可以同时在KStore上操作多个引擎。另外，提供触发器的机制允许自动报告用户和应用程序的事件，状况和事件。

8. 发明授权

US06190518B1 Device for reducing plasma etch damage and method for manufacturing same 失效
标题翻译：减少等离子体蚀刻损伤的装置及其制造方法
公开(公告)号：US06190518B1
公开(公告)日：2001-02-20
申请号：US08095147
申请日：1993-07-20
申请人： Tony T. Phan , Tom J. Goodwin , John K. Lowell
发明人： Tony T. Phan , Tom J. Goodwin , John K. Lowell
IPC分类号： C23C1434
CPC分类号： H01L21/31116 , H01J2237/0206
摘要： An improved sputter etching technique is provided for substantially preventing or reducing plasma etch damages associated with sputter etching. The plasma etch technique can utilize a semiconductor wafer having at least one diode formed within an inactive region of the wafer near the outer periphery of the wafer. The diode is capable of preventing charge transfer or arcing between the grounded anode and the p-channel gate region. By placing a diode within the inactive region of the wafer, problems such as gate oxide breakdown, threshold voltage skew, flat-band voltage skew, etc. can be minimized or substantially reduced. Alternatively, a standard wafer not having an implanted or diffused diode can be utilized to obtain similar beneficial results provided the sputter etch anode is retrofitted to include a diode placed between the anode and the ground terminal. Similar to the diode placed on the wafer, the retrofitted anode is used to provide a depletion region for preventing charge transfer therethrough.
摘要翻译：提供了一种改进的溅射蚀刻技术，用于基本上防止或减少与溅射蚀刻相关的等离子体蚀刻损伤。等离子体蚀刻技术可以利用在晶片的外周附近形成有至少一个二极管的半导体晶片，该二极管形成在晶片的非活动区域内。二极管能够防止接地阳极和p沟道栅极区域之间的电荷转移或电弧。通过将二极管放置在晶片的非活性区域内，可以最小化或显着降低诸如栅极氧化物击穿，阈值电压偏移，平带电压偏移等问题。或者，可以使用不具有注入或扩散二极管的标准晶片来获得类似的有益结果，只要溅射蚀刻阳极被改进以包括置于阳极和接地端子之间的二极管即可。类似于放置在晶片上的二极管，改进的阳极用于提供用于防止电荷转移通过的耗尽区域。

9. 发明申请

US20080132066A1 Integrated Circuit Having a Top Side Wafer Contact and a Method of Manufacture Therefor 有权
标题翻译：具有顶侧晶片接触的集成电路及其制造方法
公开(公告)号：US20080132066A1
公开(公告)日：2008-06-05
申请号：US12016443
申请日：2008-01-18
申请人： Tony T. Phan , William C. Loftin , John Lin , Philip L. Hower
发明人： Tony T. Phan , William C. Loftin , John Lin , Philip L. Hower
IPC分类号： H01L21/768
CPC分类号： H01L27/1203 , H01L21/743 , H01L21/76838
摘要： The present invention provides an integrated circuit and a method of manufacture therefore. The integrated circuit (100, 1000), in one embodiment without limitation, includes a dielectric layer (120, 1020) located over a wafer substrate (110, 1010), and a semiconductor substrate (130, 1030) located over the dielectric layer (120, 1020), the semiconductor substrate (130, 1030) having one or more transistor devices (140, 1040) located therein or thereon. The integrated circuit (100, 1000) may further include an interconnect (170, 1053) extending entirely through the semiconductor substrate (130, 1030) and the dielectric layer (120, 1020), thereby electrically contacting the wafer substrate (110, 1010).
摘要翻译：因此，本发明提供一种集成电路及其制造方法。在一个实施例中，集成电路（100,1000）没有限制地包括位于晶片衬底（110,1010）之上的电介质层（120,1020），以及位于介电层上的半导体衬底（130,1030） 120,120），具有位于其中或其上的一个或多个晶体管器件（140,1040）的半导体衬底（130,1030）。集成电路（100,1000）还可以包括完全延伸穿过半导体衬底（130,1030）和介电层（120,1020）的互连（170,1053），从而与晶片衬底（110,1010）电接触，。

10. 发明授权

US07345343B2 Integrated circuit having a top side wafer contact and a method of manufacture therefor 有权
标题翻译：具有顶侧晶片接触的集成电路及其制造方法
公开(公告)号：US07345343B2
公开(公告)日：2008-03-18
申请号：US11195283
申请日：2005-08-02
申请人： Tony T. Phan , William C. Loftin , John Lin , Philip L. Hower
发明人： Tony T. Phan , William C. Loftin , John Lin , Philip L. Hower
IPC分类号： H01L21/84
CPC分类号： H01L27/1203 , H01L21/743 , H01L21/76838
摘要： The present invention provides an integrated circuit and a method of manufacture therefore. The integrated circuit (100, 1000), in one embodiment without limitation, includes a dielectric layer (120, 1020) located over a wafer substrate (110, 1010), and a semiconductor substrate (130, 1030) located over the dielectric layer (120, 1020), the semiconductor substrate (130, 1030) having one or more transistor devices (140, 1040) located therein or thereon. The integrated circuit (100, 1000) may further include an interconnect (170, 1053) extending entirely through the semiconductor substrate (130, 1030) and the dielectric layer (120, 1020), thereby electrically contacting the wafer substrate (110, 1010).
摘要翻译：因此，本发明提供一种集成电路及其制造方法。在一个实施例中，集成电路（100,1000）没有限制地包括位于晶片衬底（110,1010）之上的电介质层（120,1020），以及位于介电层上的半导体衬底（130,1030） 120,120），具有位于其中或其上的一个或多个晶体管器件（140,1040）的半导体衬底（130,1030）。集成电路（100,1000）还可以包括完全延伸穿过半导体衬底（130,1030）和介电层（120,1020）的互连（170,1053），从而与晶片衬底（110,1010）电接触，。

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