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1. 发明授权

US07986010B2 High-voltage variable breakdown voltage (BV) diode for electrostatic discharge (ESD) applications 有权
标题翻译：用于静电放电（ESD）应用的高压可变击穿电压（BV）二极管
公开(公告)号：US07986010B2
公开(公告)日：2011-07-26
申请号：US12759391
申请日：2010-04-13
申请人： Martin B. Mollat , Tony Thanh Phan
发明人： Martin B. Mollat , Tony Thanh Phan
IPC分类号： H01L23/62
CPC分类号： H01L29/8611 , H01L29/0649
摘要： Formation of an electrostatic discharge (ESD) protection device having a desired breakdown voltage (BV) is disclosed. The breakdown voltage (BV) of the device can be set, at least in part, by varying the degree to which a surface junction between two doped areas is covered. This junction can be covered in one embodiment by a dielectric material and/or a semiconductor material. Moreover, a variable breakdown voltage can be established by concurrently forming, in a single process flow, multiple diodes that have different breakdown voltages, where the diodes are also formed concurrently with circuitry that is to be protected. To generate the variable or different breakdown voltages, respective edges of isolation regions can be extended to cover more of the surface junctions of different diodes. In this manner, a first diode can have a first breakdown voltage (BV1), a second diode can have a second breakdown voltage (BV2), a third diode can have a third breakdown voltage (BV3), etc. This can provide substantial efficiency and cost savings where there may be varying ESD requirements.
摘要翻译：公开了具有期望的击穿电压（BV）的静电放电（ESD）保护装置的形成。器件的击穿电压（BV）可以至少部分地通过改变覆盖两个掺杂区域之间的表面结的程度来设定。在一个实施例中，可以通过介电材料和/或半导体材料来覆盖该结。此外，可以通过在单个工艺流程中同时形成具有不同击穿电压的多个二极管来建立可变击穿电压，其中二极管也与要保护的电路同时形成。为了产生可变的或不同的击穿电压，隔离区域的各个边缘可以被扩展以覆盖不同二极管的更多的表面结。以这种方式，第一二极管可以具有第一击穿电压（BV1），第二二极管可以具有第二击穿电压（BV2），第三二极管可以具有第三击穿电压（BV3）等。这可以提供显着的效率以及可能存在不同ESD要求的成本节约。

2. 发明申请

US20110050275A1 SEMICONDUCTOR WAFER HAVING TEST MODULES INCLUDING PIN MATRIX SELECTABLE TEST DEVICES 有权
标题翻译：具有PIN矩阵选择性测试设备的测试模块的半导体晶体管
公开(公告)号：US20110050275A1
公开(公告)日：2011-03-03
申请号：US12552215
申请日：2009-09-01
申请人： MARTIN B. MOLLAT , DOUG WEISER , FAN-CHI FRANK HOU
发明人： MARTIN B. MOLLAT , DOUG WEISER , FAN-CHI FRANK HOU
IPC分类号： G01R31/26 , G01R31/02
CPC分类号： G01R31/2884 , G01R31/2831
摘要： A semiconductor wafer includes a plurality of die areas including circuit elements, and at least one test module (TM) on the wafer outside the die areas. The TMs include a test circuit including plurality of test transistors arranged in a plurality of rows and columns. The plurality of test transistors include at least three terminals (G, S, D and B). The TMs each include a plurality of pads. The pads include a first plurality of locally shared first pads each coupled to respective ones of a first of the three terminals, a second plurality of locally shared second pads each coupled to respective ones of a second of the three terminals, and at least one of the plurality of pads coupled to a third of the three terminals. The TM provides at least 2 pin transistor selection for uniquely selecting from the plurality of test transistors for testing.
摘要翻译：半导体晶片包括包括电路元件的多个管芯区域，以及在管芯区域外的晶片上的至少一个测试模块（TM）。 TM包括测试电路，该测试电路包括以多行和多列排列的多个测试晶体管。多个测试晶体管包括至少三个端子（G，S，D和B）。 TM各自包括多个垫。焊盘包括第一多个局部共享的第一焊盘，每个第一焊盘耦合到三个端子中的第一个端子中的相应的第一焊盘，第二多个局部共享的第二焊盘，每个第二焊盘都耦合到三个端子中的第二个的相应的一个，所述多个焊盘耦合到三个端子中的三分之一。 TM提供至少2针晶体管选择，用于从多个测试晶体管中唯一地选择用于测试。

3. 发明授权

US08436635B2 Semiconductor wafer having test modules including pin matrix selectable test devices 有权
标题翻译：具有测试模块的半导体晶片包括引脚矩阵可选择的测试设备
公开(公告)号：US08436635B2
公开(公告)日：2013-05-07
申请号：US12552215
申请日：2009-09-01
申请人： Martin B. Mollat , Doug Weiser , Fan-Chi Hou
发明人： Martin B. Mollat , Doug Weiser , Fan-Chi Hou
IPC分类号： G01R31/02
CPC分类号： G01R31/2884 , G01R31/2831
摘要： A semiconductor wafer includes a plurality of die areas including circuit elements, and at least one test module (TM) on the wafer outside the die areas. The TMs include a test circuit including plurality of test transistors arranged in a plurality of rows and columns. The plurality of test transistors include at least three terminals (G, S, D and B). The TMs each include a plurality of pads. The pads include a first plurality of locally shared first pads each coupled to respective ones of a first of the three terminals, a second plurality of locally shared second pads each coupled to respective ones of a second of the three terminals, and at least one of the plurality of pads coupled to a third of the three terminals. The TM provides at least 2 pin transistor selection for uniquely selecting from the plurality of test transistors for testing.
摘要翻译：半导体晶片包括包括电路元件的多个管芯区域，以及在管芯区域外的晶片上的至少一个测试模块（TM）。 TM包括测试电路，该测试电路包括以多行和多列排列的多个测试晶体管。多个测试晶体管包括至少三个端子（G，S，D和B）。 TM各自包括多个垫。焊盘包括第一多个局部共享的第一焊盘，每个第一焊盘耦合到三个端子中的第一个端子中的相应的第一焊盘，第二多个局部共享的第二焊盘，每个第二焊盘耦合到三个端子中的第二个的相应的一个，所述多个焊盘耦合到三个端子中的三分之一。 TM提供至少2针晶体管选择，用于从多个测试晶体管中唯一地选择用于测试。

4. 发明授权

US07776625B2 Method for locating a sub-surface feature using a scatterometer 有权
标题翻译：使用散射仪定位子表面特征的方法
公开(公告)号：US07776625B2
公开(公告)日：2010-08-17
申请号：US11423209
申请日：2006-06-09
申请人： Martin B. Mollat , Christopher C. Baum , Jonathan W. VanBuskirk
发明人： Martin B. Mollat , Christopher C. Baum , Jonathan W. VanBuskirk
IPC分类号： H01L21/66
CPC分类号： G01N21/9505 , G01N21/4788
摘要： The present invention provides a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device, without limitation, may include providing a substrate having a sub-surface feature and a surface feature, and determining a location of the sub-surface feature relative to the surface feature using a scatterometer.
摘要翻译：本发明提供一种制造半导体器件的方法。制造半导体器件的方法，但不限于，可以包括提供具有子表面特征和表面特征的衬底，以及使用散射仪来确定子表面特征相对于表面特征的位置。

5. 发明申请

US20100193868A1 HIGH-VOLTAGE VARIABLE BREAKDOWN VOLTAGE (BV) DIODE FOR ELECTROSTATIC DISCHARGE (ESD) APPLICATIONS 有权
标题翻译：用于静电放电（ESD）应用的高电压可变电压（BV）二极管
公开(公告)号：US20100193868A1
公开(公告)日：2010-08-05
申请号：US12759391
申请日：2010-04-13
申请人： Martin B. Mollat , Tony Thanh Phan
发明人： Martin B. Mollat , Tony Thanh Phan
IPC分类号： H01L23/60 , H01L27/06
CPC分类号： H01L29/8611 , H01L29/0649
摘要： Formation of an electrostatic discharge (ESD) protection device having a desired breakdown voltage (BV) is disclosed. The breakdown voltage (BV) of the device can be set, at least in part, by varying the degree to which a surface junction between two doped areas is covered. This junction can be covered in one embodiment by a dielectric material and/or a semiconductor material. Moreover, a variable breakdown voltage can be established by concurrently forming, in a single process flow, multiple diodes that have different breakdown voltages, where the diodes are also formed concurrently with circuitry that is to be protected. To generate the variable or different breakdown voltages, respective edges of isolation regions can be extended to cover more of the surface junctions of different diodes. In this manner, a first diode can have a first breakdown voltage (BV1), a second diode can have a second breakdown voltage (BV2), a third diode can have a third breakdown voltage (BV3), etc. This can provide substantial efficiency and cost savings where there may be varying ESD requirements.
摘要翻译：公开了具有期望的击穿电压（BV）的静电放电（ESD）保护装置的形成。器件的击穿电压（BV）可以至少部分地通过改变覆盖两个掺杂区域之间的表面结的程度来设定。在一个实施例中，可以通过介电材料和/或半导体材料来覆盖该结。此外，可以通过在单个工艺流程中同时形成具有不同击穿电压的多个二极管来建立可变击穿电压，其中二极管也与要保护的电路同时形成。为了产生可变的或不同的击穿电压，隔离区域的各个边缘可以被扩展以覆盖不同二极管的更多的表面结。以这种方式，第一二极管可以具有第一击穿电压（BV1），第二二极管可以具有第二击穿电压（BV2），第三二极管可以具有第三击穿电压（BV3）等。这可以提供显着的效率以及可能存在不同ESD要求的成本节约。

6. 发明授权

US07709329B2 High-voltage variable breakdown voltage (BV) diode for electrostatic discharge (ESD) applications 有权
标题翻译：用于静电放电（ESD）应用的高压可变击穿电压（BV）二极管
公开(公告)号：US07709329B2
公开(公告)日：2010-05-04
申请号：US11708190
申请日：2007-02-20
申请人： Martin B. Mollat , Tony Thanh Phan
发明人： Martin B. Mollat , Tony Thanh Phan
IPC分类号： H01L21/8234
CPC分类号： H01L29/8611 , H01L29/0649
摘要： Formation of an electrostatic discharge (ESD) protection device having a desired breakdown voltage (BV) is disclosed. The breakdown voltage (BV) of the device can be set, at least in part, by varying the degree to which a surface junction between two doped areas is covered. This junction can be covered in one embodiment by a dielectric material and/or a semiconductor material. Moreover, a variable breakdown voltage can be established by concurrently forming, in a single process flow, multiple diodes that have different breakdown voltages, where the diodes are also formed concurrently with circuitry that is to be protected. To generate the variable or different breakdown voltages, respective edges of isolation regions can be extended to cover more of the surface junctions of different diodes. In this manner, a first diode can have a first breakdown voltage (BV1), a second diode can have a second breakdown voltage (BV2), a third diode can have a third breakdown voltage (BV3), etc. This can provide substantial efficiency and cost savings where there may be varying ESD requirements.
摘要翻译：公开了具有期望的击穿电压（BV）的静电放电（ESD）保护装置的形成。器件的击穿电压（BV）可以至少部分地通过改变覆盖两个掺杂区域之间的表面结的程度来设定。在一个实施例中，可以通过介电材料和/或半导体材料来覆盖该结。此外，可以通过在单个工艺流程中同时形成具有不同击穿电压的多个二极管来建立可变击穿电压，其中二极管也与要保护的电路同时形成。为了产生可变的或不同的击穿电压，隔离区域的各个边缘可以被扩展以覆盖不同二极管的更多的表面结。以这种方式，第一二极管可以具有第一击穿电压（BV1），第二二极管可以具有第二击穿电压（BV2），第三二极管可以具有第三击穿电压（BV3）等。这可以提供显着的效率以及可能存在不同ESD要求的成本节约。

7. 发明申请

US20090023263A1 METHOD TO MANUFACTURE A THIN FILM RESISTOR 有权
标题翻译：制造薄膜电阻的方法
公开(公告)号：US20090023263A1
公开(公告)日：2009-01-22
申请号：US11779465
申请日：2007-07-18
申请人： Tony Phan , Kyle M. Flessner , Martin B. Mollat , Connie Wang , Arthur Pan , Eric William Beach , Michelle R. Keramidas , Karen Elizabeth Burks
发明人： Tony Phan , Kyle M. Flessner , Martin B. Mollat , Connie Wang , Arthur Pan , Eric William Beach , Michelle R. Keramidas , Karen Elizabeth Burks
IPC分类号： H01L21/02
CPC分类号： H01L28/20 , H01L21/8221 , H01L27/0688
摘要： A method for manufacturing a semiconductor device that method comprises forming a thin film resistor by a process that includes depositing a resistive material layer on a semiconductor substrate. The process also includes depositing an insulating layer on the resistive material layer, and performing a first dry etch process on the insulating layer to form an insulative body. The process further includes performing a second dry etch process on the resistive material layer to form a resistive body. The resistive body and the insulative body have substantially identical perimeters.
摘要翻译：一种用于制造半导体器件的方法，该方法包括通过包括在半导体衬底上沉积电阻材料层的工艺来形成薄膜电阻器。该方法还包括在电阻材料层上沉积绝缘层，以及在绝缘层上进行第一干蚀刻工艺以形成绝缘体。该方法还包括在电阻材料层上执行第二干蚀刻工艺以形成电阻体。电阻体和绝缘体具有基本相同的周长。

8. 发明申请

US20080197451A1 High-voltage variable breakdown voltage (BV) diode for electrostatic discharge (ESD) applications 有权
标题翻译：用于静电放电（ESD）应用的高压可变击穿电压（BV）二极管
公开(公告)号：US20080197451A1
公开(公告)日：2008-08-21
申请号：US11708190
申请日：2007-02-20
申请人： Martin B. Mollat , Tony Thanh Phan
发明人： Martin B. Mollat , Tony Thanh Phan
IPC分类号： H01L29/00 , H01L21/76
CPC分类号： H01L29/8611 , H01L29/0649
摘要： Formation of an electrostatic discharge (ESD) protection device having a desired breakdown voltage (BV) is disclosed. The breakdown voltage (BV) of the device can be set, at least in part, by varying the degree to which a surface junction between two doped areas is covered. This junction can be covered in one embodiment by a dielectric material and/or a semiconductor material. Moreover, a variable breakdown voltage can be established by concurrently forming, in a single process flow, multiple diodes that have different breakdown voltages, where the diodes are also formed concurrently with circuitry that is to be protected. To generate the variable or different breakdown voltages, respective edges of isolation regions can be extended to cover more of the surface junctions of different diodes. In this manner, a first diode can have a first breakdown voltage (BV1), a second diode can have a second breakdown voltage (BV2), a third diode can have a third breakdown voltage (BV3), etc. This can provide substantial efficiency and cost savings where there may be varying ESD requirements.
摘要翻译：公开了具有期望的击穿电压（BV）的静电放电（ESD）保护装置的形成。器件的击穿电压（BV）可以至少部分地通过改变覆盖两个掺杂区域之间的表面结的程度来设定。在一个实施例中，可以通过介电材料和/或半导体材料来覆盖该结。此外，可以通过在单个工艺流程中同时形成具有不同击穿电压的多个二极管来建立可变击穿电压，其中二极管也与要保护的电路同时形成。为了产生可变的或不同的击穿电压，隔离区域的各个边缘可以被扩展以覆盖不同二极管的更多的表面结。以这种方式，第一二极管可以具有第一击穿电压（BV 1），第二二极管可以具有第二击穿电压（BV 2），第三二极管可以具有第三击穿电压（BV 3）等。这可以在可能会有不同的ESD要求的情况下，提供显着的效率和成本节约。

9. 发明授权

US07262109B2 Integrated circuit having a transistor level top side wafer contact and a method of manufacture therefor 有权
公开(公告)号：US07262109B2
公开(公告)日：2007-08-28
申请号：US11196087
申请日：2005-08-03
申请人： John Lin , Tony T. Phan , Philip L. Hower , William C. Loftin , Martin B. Mollat
发明人： John Lin , Tony T. Phan , Philip L. Hower , William C. Loftin , Martin B. Mollat
IPC分类号： H01L21/76
CPC分类号： H01L27/1203 , H01L21/743 , H01L21/84 , H01L23/481 , H01L23/5226 , H01L23/535 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides an integrated circuit and a method of manufacture therefor. The integrated circuit (100), in one embodiment without limitation, includes a dielectric layer (120) located over a wafer substrate (110), and a semiconductor substrate (130) located over the dielectric layer (120), the semiconductor substrate (130) having one or more transistor devices (160) located therein or thereon. The integrated circuit (100) may further include an interconnect (180) extending entirely through the semiconductor substrate (130) and the dielectric layer (120), thereby electrically contacting the wafer substrate (110), and one or more isolation structures (150) extending entirely through the semiconductor substrate (130) to the dielectric layer (120).

10. 发明授权

US07118958B2 Method of manufacturing a metal-insulator-metal capacitor using an etchback process 有权
标题翻译：使用回蚀工艺制造金属 - 绝缘体 - 金属电容器的方法
公开(公告)号：US07118958B2
公开(公告)日：2006-10-10
申请号：US11071036
申请日：2005-03-03
申请人： Tony T. Phan , Martin B. Mollat
发明人： Tony T. Phan , Martin B. Mollat
IPC分类号： H01L21/8242 , H01L29/76
CPC分类号： H01L27/0629 , H01L28/40
摘要： The present invention provides a method for manufacturing a metal-insulator-metal (MIM) capacitor, a method for manufacturing an integrated circuit having a metal-insulator-metal (MIM) capacitor, and an integrated circuit having a metal-insulator-metal (MIM) capacitor. The method for manufacturing the metal-insulator-metal (MIM) capacitor, among other steps and without limitation, includes providing a material layer (185) over a substrate (110), and forming a refractory metal layer (210) having a thickness (t1) over the substrate (110), at least a portion of the refractory metal layer (210) extending over the material layer (185). The method further includes reducing the thickness (t2) of the portion of the refractory metal layer (210) extending over the material layer (185), thereby forming a thinned refractory metal layer (310), and reacting the thinned refractory metal layer (310) with at least a portion of the material layer (185) to form an electrode (440) for use in a capacitor.
摘要翻译：本发明提供一种金属 - 绝缘体 - 金属（MIM）电容器的制造方法，具有金属 - 绝缘体 - 金属（MIM）电容器的集成电路的制造方法和具有金属 - 绝缘体 - 金属 MIM）电容器。金属 - 绝缘体 - 金属（MIM）电容器的制造方法以及其它步骤，但不限于此，包括在衬底（110）上方提供材料层（185），并且形成具有厚度的难熔金属层（210）（110）上的至少一部分难熔金属层（210）延伸到材料层（185）上。该方法还包括减小在材料层（185）上延伸的难熔金属层（210）的部分的厚度（t 2> 2），由此形成变薄的难熔金属层（310），以及使稀薄的难熔金属层（310）与材料层（185）的至少一部分反应以形成用于电容器的电极（440）。

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