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1. 发明授权

US07141860B2 LDMOS transistor 有权
标题翻译： LDMOS晶体管
公开(公告)号：US07141860B2
公开(公告)日：2006-11-28
申请号：US10875105
申请日：2004-06-23
申请人： Vishnu K. Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose
发明人： Vishnu K. Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose
IPC分类号： H01L27/95 , H01L29/47
CPC分类号： H01L29/782 , H01L27/0727 , H01L29/0619 , H01L29/0653 , H01L29/47 , H01L29/66659 , H01L29/66681 , H01L29/7835
摘要： An LDMOS transistor has a Schottky diode inserted at the center of a doped region of the LDMOS transistor. A Typical LDMOS transistor has a drift region in the center. In this case a Schottky diode is inserted at the center of this drift region which has the effect of providing a Schottky diode connected from source to drain in the forward direction so that the drain voltage is clamped to a voltage that is lower than the PN junction threshold, thereby avoiding forward biasing the PN junction. An alternative is to insert the Schottky diode at the well in which the source is formed, which is on the periphery of the LDMOS transistor. In such case the Schottky diode is formed differently but still is connected from source to drain in the forward direction to achieve the desired voltage clamping at the drain.
摘要翻译： LDMOS晶体管具有插入在LDMOS晶体管的掺杂区域的中心处的肖特基二极管。典型的LDMOS晶体管在中心具有漂移区域。在这种情况下，肖特基二极管被插入该漂移区的中心，其具有在正向上提供从源极到漏极连接的肖特基二极管的作用，使得漏极电压被钳位到低于PN结的电压阈值，从而避免正向偏置PN结。一种替代方案是将肖特基二极管插入其中形成源的阱，其位于LDMOS晶体管的外围。在这种情况下，肖特基二极管的形成方式不同，但仍然在正向方向上从源极到漏极连接，以在漏极处实现所需的电压钳位。

2. 发明授权

US07112865B2 Diode and method for manufacturing the same 有权
公开(公告)号：US07112865B2
公开(公告)日：2006-09-26
申请号：US11071650
申请日：2005-03-03
申请人： Tatsuhiko Fujihira , Yasushi Miyasaka
发明人： Tatsuhiko Fujihira , Yasushi Miyasaka
IPC分类号： H01L27/95
CPC分类号： H01L29/66136 , H01L29/0619 , H01L29/0692 , H01L29/36 , H01L29/417 , H01L29/66143 , H01L29/8611 , H01L29/872 , Y10S257/928
摘要： A diode is provided which includes a first-conductivity-type cathode layer, a first-conductivity-type drift layer placed on the cathode region and having a lower concentration than the cathode layer, a generally ring-like second-conductivity-type ring region formed in the drift layer, second-conductivity-type anode region formed in the drift layer located inside the ring region, a cathode electrode formed in contact with the cathode layer, and an anode electrode formed in contact with the anode region, wherein the lowest resistivity of the second-conductivity-type anode region is at least 1/100 of the resistivity of the drift layer, and the thickness of the anode region is smaller than the diffusion depth of the ring region.

3. 发明授权

US07420255B2 Semiconductor device incorporating protective diode with stable ESD protection capabilities 失效
标题翻译：具有稳定ESD保护功能的保护二极管的半导体器件
公开(公告)号：US07420255B2
公开(公告)日：2008-09-02
申请号：US11396192
申请日：2006-03-30
申请人： Akira Shimizu
发明人： Akira Shimizu
IPC分类号： H01L27/95
CPC分类号： H01L27/0255 , H01L29/0638 , H01L29/0696 , H01L29/0878 , H01L29/42368 , H01L29/66568 , H01L29/66659 , H01L29/66681 , H01L29/7818 , H01L29/7821 , H01L29/7835 , H01L29/7836
摘要： A semiconductor device provided with stable ESD protection capabilities, incorporating a transistor and a protective diode to form a power control IC. The semiconductor device includes a semiconductor substrate of a first conductivity type; a well region of a second conductivity type, formed in the semiconductor substrate; the transistor formed in the well region; a guard ring region of the second conductivity type having an impurity concentration higher than the well region, formed on the surface of the semiconductor substrate inside the periphery of, and spatially separated from the boundary of, the well region; a substrate pickup region of the first conductivity type having an impurity concentration higher than the semiconductor substrate, formed on the periphery of the well region in contact with the well region and the semiconductor substrate; and a thick oxide film formed on the surface of the semiconductor substrate between the guard ring region and the substrate pickup region. The protective diode is formed including the well region, the guard ring region, and the substrate pickup region.
摘要翻译：具有稳定的ESD保护能力的半导体器件，结合了晶体管和保护二极管以形成功率控制IC。半导体器件包括第一导电类型的半导体衬底; 形成在所述半导体衬底中的第二导电类型的阱区; 所述晶体管形成在所述阱区中; 第二导电类型的保护环区域，具有比阱区高的杂质浓度，形成在半导体衬底的外围的表面上，并且与该区域的边界在空间上分离; 形成在与阱区和半导体衬底接触的阱区的周围的具有比半导体衬底高的杂质浓度的第一导电类型的衬底拾取区; 以及在保护环区域和基板拾取区域之间形成在半导体衬底的表面上的厚氧化膜。保护二极管形成包括阱区，保护环区和衬底拾取区。

4. 发明授权

US06921958B2 IGBT with a Schottky barrier diode 有权
标题翻译：具有肖特基势垒二极管的IGBT
公开(公告)号：US06921958B2
公开(公告)日：2005-07-26
申请号：US10689058
申请日：2003-10-21
申请人： Yukio Yasuda
发明人： Yukio Yasuda
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8234 , H01L27/06 , H01L27/07 , H01L27/088 , H01L29/78 , H01L31/0328 , H03K17/04 , H03K17/0812 , H01L27/95
CPC分类号： H01L27/0716 , H03K17/0406 , H03K17/08128
摘要： A semiconductor device which IGBT (Z1) and a control circuit (B1) for driving the IGBT (Z1) are formed on the same semiconductor substrate by using a junction isolation technology, includes an input terminal (P1) for inputting a drive signal of the IGBT (Z1), a Schottky barrier diode (D2) having an anode connected to the input terminal (P1) and a cathode connected to an input terminal (B11) of the control circuit (B1), and a p-channel MOSFET (T1) for shorting both ends of the Schottky barrier diode (D2) when the voltage of the drive signal input to the input terminal (P1) is higher than a predetermined voltage, thereby latch-up of the parasitic element is prevented and a transmission loss of the input signal can be reduced.
摘要翻译：通过使用结隔离技术，在同一半导体衬底上形成用于驱动IGBT（Z 1）的IGBT（Z 1）和控制电路（B 1）的半导体装置包括：输入端子（P1） IGBT（Z 1）的驱动信号，具有连接到输入端子（P 1）的阳极的肖特基势垒二极管（D 2）和连接到控制电路（B1）的输入端子（B11）的阴极，以及当输入到输入端子（P1）的驱动信号的电压高于预定电压时，用于短路肖特基势垒二极管（D 2）两端的p沟道MOSFET（T 1）防止寄生元件的上升，并且可以减小输入信号的传输损耗。

5. 发明授权

US06972470B2 Dual metal Schottky diode 有权
标题翻译：双金属肖特基二极管
公开(公告)号：US06972470B2
公开(公告)日：2005-12-06
申请号：US10814673
申请日：2004-03-30
申请人： Richard B. Irwin , Tony T. Phan , Hong-Ryong Kim , Ming-Yeh Chuang , Jennifer S. Dumin , Patrick J. Jones , Fredric D. Bailey
发明人： Richard B. Irwin , Tony T. Phan , Hong-Ryong Kim , Ming-Yeh Chuang , Jennifer S. Dumin , Patrick J. Jones , Fredric D. Bailey
IPC分类号： H01L21/20 , H01L21/329 , H01L29/47 , H01L29/80 , H01L29/872 , H01L29/93 , H01L31/112 , H01L27/95
CPC分类号： H01L29/66143 , H01L29/47 , H01L29/872
摘要： An embodiment of the invention is a Schottky diode 22 having a semiconductor substrate 3, a first metal 24, a barrier layer 26, and second metal 28. Another embodiment of the invention is a method of manufacturing a Schottky diode 22 that includes providing a semiconductor substrate 3, forming a barrier layer 26 over the semiconductor substrate 3, forming a first metal layer 23 over the semiconductor substrate 3, annealing the semiconductor substrate 3 to form areas 24 of reacted first metal and areas 23 of un-reacted first metal, and removing selected areas 23 of the un-reacted first metal. The method further includes forming a second metal layer 30 over the semiconductor substrate 3 and annealing the semiconductor substrate 3 to form areas 28 of reacted second metal and areas 30 of un-reacted second metal.
摘要翻译：本发明的实施例是具有半导体衬底3，第一金属24，阻挡层26和第二金属28的肖特基二极管22。本发明的另一实施例是制造肖特基二极管22的方法，其包括提供半导体衬底3，在半导体衬底3上形成阻挡层26，在半导体衬底3上方形成第一金属层23，退火半导体衬底3 以形成反应的第一金属的区域24和未反应的第一金属的区域23，并且去除未反应的第一金属的选定区域23。该方法还包括在半导体衬底3上形成第二金属层30并退火半导体衬底3以形成反应的第二金属的区域28和未反应的第二金属的区域30。

6. 发明授权

US06949787B2 Transistor having high dielectric constant gate insulating layer and source and drain forming Schottky contact with substrate 失效
标题翻译：晶体管具有高介电常数栅极绝缘层，源极与漏极形成肖特基接触衬底
公开(公告)号：US06949787B2
公开(公告)日：2005-09-27
申请号：US10215447
申请日：2002-08-09
申请人： John P. Snyder , John M. Larson
发明人： John P. Snyder , John M. Larson
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8234 , H01L27/095 , H01L29/10 , H01L29/417 , H01L29/47 , H01L29/51 , H01L29/78 , H01L27/95
CPC分类号： H01L21/28194 , H01L21/26513 , H01L21/28167 , H01L21/28176 , H01L21/28185 , H01L21/823412 , H01L27/095 , H01L29/105 , H01L29/1054 , H01L29/47 , H01L29/51 , H01L29/511 , H01L29/512 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/66643 , H01L29/7839
摘要： The invention is directed to a device for regulating the flow of electric current with high dielectric constant gate insulating layer and a source and/or drain forming a Schottky contact or Schottky-like region with a substrate and its fabrication method. In one aspect, the gate insulating layer has a dielectric constant greater than the dielectric constant of silicon. In another aspect, the current regulating device may be a MOSFET device, optionally a planar P-type or N-type MOSFET, having any orientation. In another aspect, the source and/or drain may consist partially or fully of a silicide.
摘要翻译：本发明涉及一种用于通过高介电常数栅极绝缘层和形成具有衬底的肖特基接触或肖特基状区域的源极和/或漏极来调节电流的装置及其制造方法。在一个方面，栅极绝缘层的介电常数大于硅的介电常数。在另一方面，电流调节装置可以是具有任何取向的MOSFET器件，可选地是平面P型或N型MOSFET。在另一方面，源极和/或漏极可部分或全部由硅化物组成。

7. 发明公开

KR1019910016094A 반도체장치 및 그 제조방법 失效
公开(公告)号：KR1019910016094A
公开(公告)日：1991-09-30
申请号：KR1019910002434
申请日：1991-02-13
申请人： 스미토모덴키고교가부시키가이샤
发明人： 쿠와따노부히로
IPC分类号： H01L27/95 , H01L21/82

8. 发明授权

KR1019960000522B1 반도체장치 및 그 제조방법 失效
标题翻译：一种半导体器件和一种用于制造该器件的器件
公开(公告)号：KR1019960000522B1
公开(公告)日：1996-01-08
申请号：KR1019910002434
申请日：1991-02-13
申请人： 스미토모덴키고교가부시키가이샤
发明人： 쿠와따노부히로
IPC分类号： H01L27/95 , H01L21/82
摘要： 내용 없음.

9. 发明授权

KR100099906B1 반도체장치 및 그 제조방법 失效
公开(公告)号：KR100099906B1
公开(公告)日：1996-05-27
申请号：KR1019910002434
申请日：1991-02-13
申请人： 스미토모덴키고교가부시키가이샤
发明人： 쿠와따노부히로
IPC分类号： H01L27/95 , H01L21/82

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