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1. 发明授权

US06232630B1 Light floating gate doping to improve tunnel oxide reliability 有权
标题翻译：光浮栅掺杂提高隧道氧化可靠性
公开(公告)号：US06232630B1
公开(公告)日：2001-05-15
申请号：US09348583
申请日：1999-07-07
申请人： Mark T. Ramsbey , Tuan Pham , Yu Sun , Kenneth Wo-Wai Au , David H. Chi
发明人： Mark T. Ramsbey , Tuan Pham , Yu Sun , Kenneth Wo-Wai Au , David H. Chi
IPC分类号： H01L2972
CPC分类号： H01L29/42324
摘要： The reliability of a tunnel oxide is improved by light doping of the floating gate, as with phosphorous or arsenic atoms. Doping can be implemented by ion implantation or by in situ deposition. The relatively low dopant concentration further enhances charge retention on the floating gate.
摘要翻译：隧道氧化物的可靠性通过浮栅的轻掺杂而改善，如同磷或砷原子一样。掺杂可以通过离子注入或原位沉积来实现。相对低的掺杂剂浓度进一步增强了浮栅上的电荷保持。

2. 发明授权

US06465303B1 Method of manufacturing spacer etch mask for silicon-oxide-nitride-oxide-silicon (SONOS) type nonvolatile memory 有权
标题翻译：制造用于氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）型非易失性存储器的间隔物蚀刻掩模的方法
公开(公告)号：US06465303B1
公开(公告)日：2002-10-15
申请号：US09885490
申请日：2001-06-20
申请人： Mark T. Ramsbey , Narbeh Derhacobian , Janet Wang , Angela Hui , Tuan Pham , Ravi Sunkavalli , Mark Randolph
发明人： Mark T. Ramsbey , Narbeh Derhacobian , Janet Wang , Angela Hui , Tuan Pham , Ravi Sunkavalli , Mark Randolph
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/11573
摘要： One aspect of the present invention relates to a method of forming spacers in a silicon-oxide-nitride-oxide-silicon (SONOS) type nonvolatile semiconductor memory device, involving the steps of providing a semiconductor substrate having a core region and periphery region, the core region containing SONOS type memory cells and the periphery region containing gate transistors; implanting a first implant into the core region and a first implant into the periphery region of the semiconductor substrate; forming a spacer material over the semiconductor substrate; masking the core region and forming spacers adjacent the gate transistors in the periphery region; and implanting a second implant into the periphery region of the semiconductor substrate.
摘要翻译：本发明的一个方面涉及一种在氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）型非易失性半导体存储器件中形成间隔物的方法，包括以下步骤：提供具有核心区域和外围区域的半导体衬底，包含SONOS型存储单元的核心区域和包含栅极晶体管的外围区域; 将第一注入植入到所述芯区域中，并将第一注入植入所述半导体衬底的周边区域; 在所述半导体衬底上形成隔离材料; 掩蔽所述芯区域并在所述周边区域中形成与所述栅极晶体管相邻的间隔物; 以及将第二植入物植入所述半导体衬底的周边区域。

3. 发明授权

US06730564B1 Salicided gate for virtual ground arrays 有权
标题翻译：用于虚拟地面阵列的闸门
公开(公告)号：US06730564B1
公开(公告)日：2004-05-04
申请号：US10217821
申请日：2002-08-12
申请人： Mark T. Ramsbey , Yu Sun , Chi Chang , Hidehiko Shiraiwa
发明人： Mark T. Ramsbey , Yu Sun , Chi Chang , Hidehiko Shiraiwa
IPC分类号： H01L218247
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11534 , Y10S438/954
摘要： The present invention provides a process for saliciding word lines in a virtual ground array flash memory device without causing shorting between bit lines. According to one aspect of the invention, saliciding takes place prior to patterning one or more layers of a memory cell stack. The unpatterned layers protect the substrate between word lines from becoming salicided. The invention provides virtual ground array flash memory devices with doped and salicided word lines, but no shorting between bit lines, even in virtual ground arrays where there are no oxide island isolation regions between word lines. Potential advantages of such structures include reduced size, reduced number of processing steps, and reduced exposure to high temperature cycling.
摘要翻译：本发明提供了一种在虚拟接地阵列闪存器件中对字线进行水印处理，而不引起位线之间的短路。根据本发明的一个方面，在对存储单元堆叠的一层或多层进行构图之前进行水化。未图案化的层保护字线之间的基板不会变成水银。本发明提供具有掺杂和含水字线的虚拟接地阵列闪存器件，但是即使在字线之间没有氧化物岛隔离区域的虚拟接地阵列中也不会在位线之间发生短路。这种结构的潜在优点包括减小的尺寸，减少的加工步骤数量以及降低暴露于高温循环。

4. 发明授权

US06630384B1 Method of fabricating double densed core gates in sonos flash memory 有权
标题翻译：在sonos闪存中制造双激光核心门的方法
公开(公告)号：US06630384B1
公开(公告)日：2003-10-07
申请号：US09971483
申请日：2001-10-05
申请人： Yu Sun , Michael A. Van Buskirk , Mark T. Ramsbey
发明人： Yu Sun , Michael A. Van Buskirk , Mark T. Ramsbey
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L27/115
摘要： One aspect of the present invention relates to a method of forming a non-volatile semiconductor memory device, involving forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; forming a first set of memory cell gates over the charge trapping dielectric in the core region; forming a conformal insulation material layer around the first set of memory cell gates; and forming a second set of memory cell gates in the core region, wherein each memory cell gate of the second set of memory cell gates is adjacent to at least one memory cell gate of the first set of memory cell gates, each memory cell gate of the first set of memory cell gates is adjacent at least one memory cell gate of the second set of memory cell gates, and the conformal insulation material layer is positioned between each adjacent memory cell gate.
摘要翻译：本发明的一个方面涉及一种形成非易失性半导体存储器件的方法，包括在衬底上形成电荷俘获电介质，所述衬底具有芯区域和外围区域; 在芯区域中的电荷俘获电介质上形成第一组存储单元栅极; 在所述第一组存储单元栅极周围形成保形绝缘材料层; 以及在所述核心区域中形成第二组存储器单元栅极，其中所述第二组存储单元栅极的每个存储单元栅极与所述第一组存储单元栅极的至少一个存储单元栅极相邻，第一组存储单元栅极与第二组存储单元栅极的至少一个存储单元栅极相邻，并且保形绝缘材料层位于每个相邻的存储单元栅极之间。

5. 发明授权

US06455373B1 Semiconductor device having gate edges protected from charge gain/loss 有权
标题翻译：具有防止电荷增益/损耗的栅极边缘的半导体器件
公开(公告)号：US06455373B1
公开(公告)日：2002-09-24
申请号：US09834419
申请日：2001-04-12
申请人： Tuan D. Pham , Mark T. Ramsbey , Sameer S. Haddad , Angela T. Hui , Yu Sun , Chi Chang
发明人： Tuan D. Pham , Mark T. Ramsbey , Sameer S. Haddad , Angela T. Hui , Yu Sun , Chi Chang
IPC分类号： H01L21336
CPC分类号： H01L27/11526 , H01L21/823468 , H01L27/105 , H01L27/11536
摘要： A plurality of core gate stacks and periphery gates on the substrate, each core gate stack and periphery gate having at least one side and first and second protective shoulders formed on said plurality of core gate stacks and periphery gates, such that a dopant can be implanted sequentially into source and drain regions of a substrate supporting the stacks to establish transistors and such that charge migration into said at least one side of the gate stacks during interlayer dielectric (ILD) formation and device metallization is prevented, at least the second shoulder being frabricated from at least one material selected from a group consisting essentially of nitride and silicon oxynitride (SiON).
摘要翻译：在基板上的多个核心栅极叠层和周边栅极，每个芯栅极叠层和周边栅极具有形成在所述多个芯栅极叠层和外围栅极上的至少一个侧面和第一和第二保护肩部，使得掺杂剂可被植入顺序地进入支撑堆叠的衬底的源极和漏极区域以建立晶体管，并且防止在层间电介质（ILD）形成和器件金属化期间电荷迁移到栅极叠层的所述至少一个侧面，至少第二肩部被破坏选自由氮化物和氮氧化硅（SiON）组成的组中的至少一种材料。

6. 发明授权

US06369416B1 Semiconductor device with contacts having a sloped profile 有权
标题翻译：具有倾斜轮廓的触头的半导体器件
公开(公告)号：US06369416B1
公开(公告)日：2002-04-09
申请号：US09404394
申请日：1999-09-23
申请人： Angela T. Hui , Tuan Duc Pham , Mark T. Ramsbey , Yu Sun
发明人： Angela T. Hui , Tuan Duc Pham , Mark T. Ramsbey , Yu Sun
IPC分类号： H01L2976
CPC分类号： H01L27/115 , H01L21/76804
摘要： A method and system for providing a contact in a semiconductor device including a plurality of gates is disclosed. The method and system include providing an insulating layer substantially surrounding at least a portion of the plurality of gates and providing at least one contact within the insulating layer. The contact has a side defining a sloped profile. The sloped profile includes an angle between the side of the contact and a surface of the substrate that is less than approximately eighty-eight degrees.
摘要翻译：公开了一种用于在包括多个栅极的半导体器件中提供接触的方法和系统。该方法和系统包括提供基本上围绕多个栅极的至少一部分的绝缘层，并且在绝缘层内提供至少一个触点。触点具有限定倾斜轮廓的侧面。倾斜轮廓包括接触侧面和基体表面之间的角度小于大约八十八度。

7. 发明授权

US06342415B1 Method and system for providing reduced-sized contacts in a semiconductor device 失效
标题翻译：用于在半导体器件中提供减小尺寸的触点的方法和系统
公开(公告)号：US06342415B1
公开(公告)日：2002-01-29
申请号：US09404395
申请日：1999-09-23
申请人： Angela T. Hui , Tuan Duc Pham , Mark T. Ramsbey , Yu Sun
发明人： Angela T. Hui , Tuan Duc Pham , Mark T. Ramsbey , Yu Sun
IPC分类号： H01L218238
CPC分类号： H01L21/31144 , H01L21/76816 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： A method and system for providing a contact in a semiconductor device including a plurality of gates is disclosed. The method and system include providing an insulating layer substantially surrounding at least a portion of the plurality of gates and providing at least one contact within the insulating layer. The at least one contact has a reduced width that is less than approximately 0.28 microns
摘要翻译：公开了一种用于在包括多个栅极的半导体器件中提供接触的方法和系统。该方法和系统包括提供基本上围绕多个栅极的至少一部分的绝缘层，并且在绝缘层内提供至少一个触点。所述至少一个接触件具有小于约0.28微米的减小的宽度

8. 发明授权

US06248627B1 Method for protecting gate edges from charge gain/loss in semiconductor device 有权
标题翻译：在半导体器件中保护栅极边缘免受电荷增益/损耗的方法
公开(公告)号：US06248627B1
公开(公告)日：2001-06-19
申请号：US09376658
申请日：1999-08-18
申请人： Tuan D. Pham , Mark T. Ramsbey , Sameer S. Haddad , Angela T. Hui , Yu Sun , Chi Chang
发明人： Tuan D. Pham , Mark T. Ramsbey , Sameer S. Haddad , Angela T. Hui , Yu Sun , Chi Chang
IPC分类号： H01L21336
CPC分类号： H01L27/11526 , H01L21/823468 , H01L27/105 , H01L27/11536
摘要： A method for making a ULSI MOSFET includes covering core gate stacks with a first protective layer, etching away the first layer such that intended source regions of the substrate are exposed, and implanting dopant into the source regions. A second protective layer is then deposited over the first layer and is etched back to conform to the first layer, covering only the sides of the gate stacks, and exposing intended drain regions of the substrate. Dopant is then implanted into the drain regions. During subsequent manufacturing steps including ILD formation and metallization, mobile ions and other process-induced charges are blocked from entering the floating gates of the gate stacks by the protective layers, thereby preventing unwanted charge gain/loss.
摘要翻译：制造ULSI MOSFET的方法包括用第一保护层覆盖芯栅极叠层，蚀刻掉第一层，使得衬底的预期源极区域暴露，并将掺杂剂注入到源极区域中。然后在第一层上沉积第二保护层，并将其回蚀刻以符合第一层，仅覆盖栅极堆叠的侧面，并暴露衬底的预期漏极区域。然后将掺杂剂注入漏区。在包括ILD形成和金属化的后续制造步骤期间，阻止移动离子和其它工艺感应电荷被保护层进入栅极堆叠的浮置栅极，从而防止不必要的电荷增益/损耗。

9. 发明授权

US08673716B2 Memory manufacturing process with bitline isolation 有权
标题翻译：内存制造过程采用位线隔离
公开(公告)号：US08673716B2
公开(公告)日：2014-03-18
申请号：US10118732
申请日：2002-04-08
申请人： Mark T. Ramsbey , Tazrien Kamal , Jean Y. Yang , Emmanuil Lingunis , Hidehiko Shiraiwa , Yu Sun
发明人： Mark T. Ramsbey , Tazrien Kamal , Jean Y. Yang , Emmanuil Lingunis , Hidehiko Shiraiwa , Yu Sun
IPC分类号： H01L21/8247
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/11573
摘要： A method of manufacturing an integrated circuit is provided with a semiconductor substrate having a core region and a periphery region. A charge-trapping dielectric layer is deposited in the core region, and a gate dielectric layer is deposited in the periphery region. Bitlines are formed in the semiconductor substrate in the core region and not in the periphery region. A wordline-gate layer is formed and implanted with dopant in the core region and not in the periphery region. A wordline and gate are formed. Source/drain junctions are implanted with dopant in the semiconductor substrate around the gate, and the gate is implanted with a gate doping implantation in the periphery region and not in the core region.
摘要翻译：集成电路的制造方法具有具有芯区域和周边区域的半导体基板。在芯区域中沉积电荷捕获电介质层，并且在周边区域中沉积栅极电介质层。位线在芯区域中的半导体衬底中而不是在周边区域中形成。在芯区域而不是周边区域中形成并注入掺杂剂的字线栅层。形成了一条字和门。源极/漏极结在栅极周围的半导体衬底中注入掺杂剂，栅极注入栅极掺杂注入在外围区域而不在核心区域。

10. 发明授权

US07012008B1 Dual spacer process for non-volatile memory devices 有权
标题翻译：用于非易失性存储器件的双间隔器工艺
公开(公告)号：US07012008B1
公开(公告)日：2006-03-14
申请号：US09728554
申请日：2000-12-01
申请人： Jeffrey A. Shields , Tuan D. Pham , Mark T. Ramsbey , Yu Sun , Angela T. Hui , Maria Chow Chan
发明人： Jeffrey A. Shields , Tuan D. Pham , Mark T. Ramsbey , Yu Sun , Angela T. Hui , Maria Chow Chan
IPC分类号： H01L21/31
CPC分类号： H01L27/11568 , H01L27/11526 , H01L27/11531
摘要： In a two-step spacer fabrication process for a non-volatile memory device, a thin oxide layer is deposited on a wafer substrate leaving a gap in the core of the non-volatile memory device. Implantation and/or oxide-nitride-oxide removal can be accomplished through this gap. After implantation, a second spacer is deposited. After the second spacer deposition, a periphery spacer etch is performed. By the above method, a spacer is formed.
摘要翻译：在用于非易失性存储器件的两步间隔件制造工艺中，薄的氧化物层沉积在晶片衬底上，在非易失性存储器件的芯中留下间隙。可通过该间隙实现植入和/或氧化氮化物 - 氧化物去除。植入后，沉积第二间隔物。在第二间隔物沉积之后，执行外围间隔物蚀刻。通过上述方法，形成间隔物。

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