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1. 发明授权

US06232630B1 Light floating gate doping to improve tunnel oxide reliability 有权
标题翻译：光浮栅掺杂提高隧道氧化可靠性
公开(公告)号：US06232630B1
公开(公告)日：2001-05-15
申请号：US09348583
申请日：1999-07-07
申请人： Mark T. Ramsbey , Tuan Pham , Yu Sun , Kenneth Wo-Wai Au , David H. Chi
发明人： Mark T. Ramsbey , Tuan Pham , Yu Sun , Kenneth Wo-Wai Au , David H. Chi
IPC分类号： H01L2972
CPC分类号： H01L29/42324
摘要： The reliability of a tunnel oxide is improved by light doping of the floating gate, as with phosphorous or arsenic atoms. Doping can be implemented by ion implantation or by in situ deposition. The relatively low dopant concentration further enhances charge retention on the floating gate.
摘要翻译：隧道氧化物的可靠性通过浮栅的轻掺杂而改善，如同磷或砷原子一样。掺杂可以通过离子注入或原位沉积来实现。相对低的掺杂剂浓度进一步增强了浮栅上的电荷保持。

2. 发明授权

US06465303B1 Method of manufacturing spacer etch mask for silicon-oxide-nitride-oxide-silicon (SONOS) type nonvolatile memory 有权
标题翻译：制造用于氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）型非易失性存储器的间隔物蚀刻掩模的方法
公开(公告)号：US06465303B1
公开(公告)日：2002-10-15
申请号：US09885490
申请日：2001-06-20
申请人： Mark T. Ramsbey , Narbeh Derhacobian , Janet Wang , Angela Hui , Tuan Pham , Ravi Sunkavalli , Mark Randolph
发明人： Mark T. Ramsbey , Narbeh Derhacobian , Janet Wang , Angela Hui , Tuan Pham , Ravi Sunkavalli , Mark Randolph
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/11573
摘要： One aspect of the present invention relates to a method of forming spacers in a silicon-oxide-nitride-oxide-silicon (SONOS) type nonvolatile semiconductor memory device, involving the steps of providing a semiconductor substrate having a core region and periphery region, the core region containing SONOS type memory cells and the periphery region containing gate transistors; implanting a first implant into the core region and a first implant into the periphery region of the semiconductor substrate; forming a spacer material over the semiconductor substrate; masking the core region and forming spacers adjacent the gate transistors in the periphery region; and implanting a second implant into the periphery region of the semiconductor substrate.
摘要翻译：本发明的一个方面涉及一种在氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）型非易失性半导体存储器件中形成间隔物的方法，包括以下步骤：提供具有核心区域和外围区域的半导体衬底，包含SONOS型存储单元的核心区域和包含栅极晶体管的外围区域; 将第一注入植入到所述芯区域中，并将第一注入植入所述半导体衬底的周边区域; 在所述半导体衬底上形成隔离材料; 掩蔽所述芯区域并在所述周边区域中形成与所述栅极晶体管相邻的间隔物; 以及将第二植入物植入所述半导体衬底的周边区域。

3. 发明授权

US09224475B2 Structures and methods for making NAND flash memory 有权
标题翻译：制造NAND闪存的结构和方法
公开(公告)号：US09224475B2
公开(公告)日：2015-12-29
申请号：US13592780
申请日：2012-08-23
申请人： Jongsun Sel , Tuan Pham , Kazuya Tokunaga , Hiro Kinoshita
发明人： Jongsun Sel , Tuan Pham , Kazuya Tokunaga , Hiro Kinoshita
IPC分类号： H01L21/336 , G11C16/04 , H01L21/28 , H01L29/66 , H01L27/115 , H01L29/788
CPC分类号： G11C16/0483 , H01L21/28273 , H01L27/11524 , H01L27/11529 , H01L27/11536 , H01L27/11541 , H01L29/66825 , H01L29/7881
摘要： A NAND flash memory chip includes wide openings in an inter-poly dielectric layer through which gaps are later etched to define structures such as select gates. Such select gates are asymmetric, with inter-poly dielectric on a side adjacent to a memory cell and no inter-poly dielectric on a side away from a memory cell. Gaps etched through such openings may also define peripheral devices.
摘要翻译： NAND闪速存储器芯片包括在多晶硅间介质层中的宽开口，通过该开口稍后刻蚀间隙以限定诸如选择栅极的结构。这种选择栅极是不对称的，在与存储器单元相邻的一侧上具有多晶硅电介质，并且在远离存储器单元的一侧上没有多晶硅电介质。通过这种开口蚀刻的间隙也可以限定外围设备。

4. 发明授权

US09153595B2 Methods of making word lines and select lines in NAND flash memory 有权
标题翻译：在NAND闪存中制作字线和选择线的方法
公开(公告)号：US09153595B2
公开(公告)日：2015-10-06
申请号：US13619553
申请日：2012-09-14
申请人： Jongsun Sel , Tuan Pham , Kazuya Tokunaga
发明人： Jongsun Sel , Tuan Pham , Kazuya Tokunaga
IPC分类号： G11C16/04 , H01L21/8239 , H01L27/115 , H01L27/02
CPC分类号： H01L27/11524 , H01L27/0207 , H01L27/11519
摘要： A NAND flash memory chip includes word lines formed by etching through concentric conductive loops and, in the same etch step, etching through a conductive strip to form select lines. A conductive loop forms two word lines which are in different erase blocks and are separately controlled by peripheral circuits.
摘要翻译： NAND闪存芯片包括通过同心导电回路蚀刻形成的字线，并且在相同的蚀刻步骤中，通过导电条进行蚀刻以形成选择线。导电环形成两个不同擦除块的字线，并由外围电路分开控制。

5. 发明授权

US07436019B2 Non-volatile memory cells shaped to increase coupling to word lines 有权
标题翻译：非易失性存储单元成形为增加与字线的耦合
公开(公告)号：US07436019B2
公开(公告)日：2008-10-14
申请号：US11622634
申请日：2007-01-12
申请人： Jeffrey W. Lutze , Tuan Pham , Masaaki Higashitani
发明人： Jeffrey W. Lutze , Tuan Pham , Masaaki Higashitani
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , H01L21/28273 , H01L27/11521
摘要： A non-volatile memory array has word lines coupled to floating gates, the floating gates having an upper portion that is adapted to provide increased surface area, and thereby, to provide increased coupling to the word lines. Shielding between floating gates is also provided. The upper portion covers part of a lower portion of the floating gate and leaves a part of the lower portion uncovered. A control gate is coplanar with a top surface of the upper portion, a vertical side of the upper portion, and the uncovered portion of the lower portion.
摘要翻译：非易失性存储器阵列具有耦合到浮动栅极的字线，浮动栅极具有适于提供增加的表面积的上部部分，从而提供增加的与字线的耦合。还提供了浮动门之间的屏蔽。上部覆盖浮动门的下部的一部分并且使下部的未被覆盖的部分离开。控制栅极与上部的上表面，上部的垂直侧和下部的未覆盖部分共面。

6. 发明申请

US20080248621A1 Integrated Non-Volatile Memory And Peripheral Circuitry Fabrication 有权
标题翻译：集成非易失性存储器和外围电路制造
公开(公告)号：US20080248621A1
公开(公告)日：2008-10-09
申请号：US12058512
申请日：2008-03-28
申请人： James Kai , Tuan Pham , Masaaki Higashitani , George Matamis , Takashi Orimoto
发明人： James Kai , Tuan Pham , Masaaki Higashitani , George Matamis , Takashi Orimoto
IPC分类号： H01L21/336
CPC分类号： H01L27/11529 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11536 , H01L27/11539
摘要： Non-volatile memory and integrated memory and peripheral circuitry fabrication processes are provided. Sets of charge storage regions, such as NAND strings including multiple non-volatile storage elements, are formed over a semiconductor substrate using a layer of charge storage material such as a first layer of polysilicon. An intermediate dielectric layer is provided over the charge storage regions. A layer of conductive material such as a second layer of polysilicon is deposited over the substrate and etched to form the control gates for the charge storage regions and the gate regions of the select transistors for the sets of storage elements. The first layer of polysilicon is removed from a portion of the substrate, facilitating fabrication of the select transistor gate regions from only the second layer of polysilicon. Peripheral circuitry formation is also incorporated into the fabrication process to form the gate regions for devices such as high voltage and logic transistors. The gate regions of these devices can be formed from the layer forming the control gates of the memory array.
摘要翻译：提供非易失性存储器和集成存储器和外围电路制造工艺。使用诸如第一多晶硅层的电荷存储材料层在半导体衬底上形成诸如包括多个非易失性存储元件的NAND串的电荷存储区的集合。中间电介质层设置在电荷存储区域的上方。将诸如第二多晶硅层的导电材料层沉积在衬底上并被蚀刻以形成用于存储元件组的选择晶体管的电荷存储区域和栅极区域的控制栅极。从衬底的一部分去除第一层多晶硅，便于仅从第二层多晶硅制造选择晶体管栅极区。外围电路形成也被并入到制造过程中以形成诸如高电压和逻辑晶体管的器件的栅极区域。这些器件的栅极区域可以由形成存储器阵列的控制栅极的层形成。

7. 发明申请

US20080074920A1 Nonvolatile Memory with Reduced Coupling Between Floating Gates 审中-公开
标题翻译：浮动闸门耦合减少的非易失性存储器
公开(公告)号：US20080074920A1
公开(公告)日：2008-03-27
申请号：US11534139
申请日：2006-09-21
申请人： Henry Chien , George Matamis , Tuan Pham , Masaaki Higashitani , Hidetaka Horiuchi , Jeffrey W. Lutze , Nima Mokhlesi , Yupin Kawing Fong
发明人： Henry Chien , George Matamis , Tuan Pham , Masaaki Higashitani , Hidetaka Horiuchi , Jeffrey W. Lutze , Nima Mokhlesi , Yupin Kawing Fong
IPC分类号： G11C5/06
CPC分类号： H01L27/115 , H01L27/11521
摘要： A nonvolatile memory array includes floating gates that have an inverted-T shape in cross section along a plane that is perpendicular to the direction along which floating cells are connected together to form a string. Adjacent strings are isolated by shallow trench isolation structures. An array having inverted-T shaped floating gates may be formed in a self-aligned manner.
摘要翻译：非易失性存储器阵列包括沿着垂直于浮动单元连接在一起以形成串的方向的平面的横截面具有倒T形的浮动栅极。相邻的串由浅沟槽隔离结构隔离。具有倒T形浮置栅极的阵列可以以自对准的方式形成。

8. 发明申请

US20070087504A1 Integration process flow for flash devices with low gap fill aspect ratio 有权
标题翻译：具有低间隙填充宽高比的闪存器件的集成工艺流程
公开(公告)号：US20070087504A1
公开(公告)日：2007-04-19
申请号：US11254142
申请日：2005-10-18
申请人： Tuan Pham , Masaaki Higashitani
发明人： Tuan Pham , Masaaki Higashitani
IPC分类号： H01L21/336 , H01L21/76
CPC分类号： H01L27/11526 , H01L21/31111 , H01L21/3212 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L27/11531
摘要： A non-volatile memory is formed having shallow trench isolation structures between floating gates and having control gates extending between floating gates where shallow trench isolation dielectric is etched. Control of etch depth is achieved using ion implantation to create a layer of dielectric with a high etch rate compared with the underlying dielectric. A conductive layer overlies the substrate during implantation. A substrate having small polysilicon features in a memory array and large polysilicon features in a peripheral area is accurately planarized using protrusions in the peripheral area and a soft chemical mechanical polishing step that stops when protrusions are removed.
摘要翻译：形成在浮动栅极之间具有浅沟槽隔离结构并且具有在浮动栅极之间延伸的控制栅极的非易失性存储器，其中浅沟槽隔离电介质被蚀刻。使用离子注入实现蚀刻深度的控制，以与下层电介质相比形成具有高蚀刻速率的电介质层。在植入期间，导电层覆盖衬底。存储器阵列中具有小的多晶硅特征的基板和外围区域中的大多晶硅特征使用周边区域中的突起精细地平坦化，并且当突起被去除时停止的软化学机械抛光步骤。

9. 发明授权

US06981965B2 Universal passive protector for an IV catheter 有权
公开(公告)号：US06981965B2
公开(公告)日：2006-01-03
申请号：US10003782
申请日：2001-10-31
申请人： Ronald B. Luther , Tuan Pham , John Muri
发明人： Ronald B. Luther , Tuan Pham , John Muri
IPC分类号： A61M5/00
CPC分类号： A61M25/0606 , A61M5/3271 , A61M25/0612 , A61M25/0625 , A61M2005/3249
摘要： A universal passive protector for an IV catheter is provided. The protector comprises an over-the-needle catheter including a proximal hub. The hub is secured within a hub trap comprising first and second interlocking arms. The hub trap is secured to a distal end of a tubular sheath. A slider is disposed about the sheath, and connected to a proximal end of the needle through a slit in the sheath. When the slider is in a distal position, the needle maintains the arms in a closed configuration wherein the hub is secured to the hub trap. When the slider is moved to a proximal position, the needle moves to a proximal position wherein the needle no longer maintains the arms in a closed position. The arms snap to an open position, releasing the hub and trapping the sharp distal tip of the needle within the sheath. Medical technicians are thus protected against accidental needle sticks.

10. 发明授权

US06680507B2 Dual bit isolation scheme for flash memory devices having polysilicon floating gates 失效
标题翻译：具有多晶硅浮动栅极的闪存器件的双位隔离方案
公开(公告)号：US06680507B2
公开(公告)日：2004-01-20
申请号：US09833307
申请日：2001-04-11
申请人： Tuan Pham , Angela T. Hui
发明人： Tuan Pham , Angela T. Hui
IPC分类号： H01L29788
CPC分类号： H01L27/11519 , G11C16/0458 , H01L27/11521
摘要： The present invention relates generally to semiconductor memory devices and more particularly to multi-bit flash electrically erasable programmable read only memory (EEPROM) devices that employ charge trapping within a floating gate to indicate a 0 or 1 bit state. A memory device is provided, according to an aspect of the invention, comprising a floating gate transistor having dual polysilicon floating gates with an isolation opening between floating gates. Processes for making the memory device according to the invention are also disclosed.
摘要翻译：本发明一般涉及半导体存储器件，更具体地说涉及在浮置栅极内采用电荷俘获来表示0或1位状态的多位闪存电可擦除可编程只读存储器（EEPROM）器件。根据本发明的一个方面，提供一种存储器件，其包括具有双重多晶硅浮动栅极的浮动栅极晶体管，在浮置栅极之间具有隔离开口。还公开了用于制造根据本发明的存储器件的工艺。

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