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1. 发明授权

US07221006B2 GeSOI transistor with low junction current and low junction capacitance and method for making the same 有权
标题翻译：具有低结电流和低结电容的GeSOI晶体管及其制造方法
公开(公告)号：US07221006B2
公开(公告)日：2007-05-22
申请号：US11110234
申请日：2005-04-20
申请人： Marius Orlowski , Sinan Goktepeli , Chun-Li Liu
发明人： Marius Orlowski , Sinan Goktepeli , Chun-Li Liu
IPC分类号： H01L31/00
CPC分类号： H01L29/7848 , H01L21/7624 , H01L29/165 , H01L29/66545 , H01L29/66636
摘要： A semiconductor device (101) is provided herein which comprises a substrate (103) comprising germanium. The substrate has source (107) and drain (109) regions defined therein. A barrier layer (111) comprising a first material that has a higher bandgap (Eg) than germanium is disposed at the boundary of at least one of said source and drain regions. At least one of the source and drain regions comprises germanium.
摘要翻译：本文提供了一种包括包含锗的衬底（103）的半导体器件（101）。衬底具有限定在其中的源极（107）和漏极（109）。包括具有比锗更高的带隙（E））的第一材料的阻挡层（111）设置在所述源极和漏极区域中的至少一个的边界处。源区和漏区中的至少一个包括锗。

2. 发明申请

US20060237746A1 GeSOI transistor with low junction current and low junction capacitance and method for making the same 有权
标题翻译：具有低结电流和低结电容的GeSOI晶体管及其制造方法
公开(公告)号：US20060237746A1
公开(公告)日：2006-10-26
申请号：US11110234
申请日：2005-04-20
申请人： Marius Orlowski , Sinan Goktepeli , Chun-Li Liu
发明人： Marius Orlowski , Sinan Goktepeli , Chun-Li Liu
IPC分类号： H01L31/00
CPC分类号： H01L29/7848 , H01L21/7624 , H01L29/165 , H01L29/66545 , H01L29/66636
摘要： A semiconductor device (101) is provided herein which comprises a substrate (103) comprising germanium. The substrate has source (107) and drain (109) regions defined therein. A barrier layer (111) comprising a first material that has a higher bandgap (Eg) than germanium is disposed at the boundary of at least one of said source and drain regions. At least one of the source and drain regions comprises germanium.
摘要翻译：本文提供了一种包括包含锗的衬底（103）的半导体器件（101）。衬底具有限定在其中的源极（107）和漏极（109）。包括具有比锗更高的带隙（E））的第一材料的阻挡层（111）设置在所述源极和漏极区域中的至少一个的边界处。源区和漏区中的至少一个包括锗。

3. 发明申请

US20070173024A1 Method for producing two gates controlling the same channel 有权
公开(公告)号：US20070173024A1
公开(公告)日：2007-07-26
申请号：US11339101
申请日：2006-01-25
申请人： Sinan Goktepeli , Alexander Hoefler , Marius Orlowski
发明人： Sinan Goktepeli , Alexander Hoefler , Marius Orlowski
IPC分类号： H01L21/336
CPC分类号： H01L21/28132 , H01L21/823437 , H01L21/823468 , H01L27/0705 , H01L29/66484 , H01L29/7831
摘要： A semiconductor process and apparatus use a predetermined sequence of patterning and etching steps to etch a gate stack (62) formed over a substrate (11) and a first spacer structure (42), thereby forming etched gate structures (72, 74) that are physically separated from one another but that control a substrate channel (71) subsequently defined in the substrate (11) by source/drain regions (82, 102, 84, 104) that are implanted around the etched gate structures (72, 74). Depending on how the first spacer structure (42) is positioned and configured, the channel (71) may be controlled to provide either a logical AND gate (100) or logical OR gate (200) functionality.

4. 发明申请

US20070077706A1 Method of making a multi-bit nov-volatile memory (NYM) cell and structure 有权
标题翻译：制造多位非易失性存储器（NYM）单元和结构的方法
公开(公告)号：US20070077706A1
公开(公告)日：2007-04-05
申请号：US11240242
申请日：2005-09-30
申请人： Marius Orlowski , Sinan Goktepeli
发明人： Marius Orlowski , Sinan Goktepeli
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , H01L29/42332
摘要： A multi-bit non volatile memory cell includes a first floating gate sidewall spacer structure and a second floating gate sidewall spacer structure physically separated from the first floating gate sidewall spacer structure. Each floating gate sidewall spacer structure stores charge for logically storing a bit. The floating gate sidewall spacer structures are formed adjacent to a patterned structure by sidewall spacer formation processes from a layer of floating gate material (e.g. polysilicon). A control gate is formed over the floating gate sidewall spacer structures by forming a layer of control gate material and then patterning the layer of control gate material.
摘要翻译：多位非易失性存储单元包括第一浮栅侧壁间隔结构和与第一浮栅侧壁间隔结构物理分离的第二浮栅侧壁间隔结构。每个浮栅侧壁间隔结构存储逻辑存储位的电荷。通过从浮置栅极材料层（例如多晶硅）的侧壁间隔物形成工艺，将浮栅侧壁间隔结构形成为与图案化结构相邻。通过形成控制栅极材料层，然后对控制栅极材料层进行图案化，在浮栅侧壁间隔结构上形成控制栅极。

5. 发明申请

US20070218640A1 SEMICONDUCTOR DEVICE HAVING A GATE WITH A THIN CONDUCTIVE LAYER 审中-公开
标题翻译：具有薄导电层的栅极的半导体器件
公开(公告)号：US20070218640A1
公开(公告)日：2007-09-20
申请号：US11752544
申请日：2007-05-23
申请人： Sinan Goktepeli , Alexander Demkov , Marius Orlowski
发明人： Sinan Goktepeli , Alexander Demkov , Marius Orlowski
IPC分类号： H01L21/336
CPC分类号： H01L29/42372
摘要： A semiconductor device having a gate with a thin conductive layer is described. As the physical dimensions of semiconductor devices are scaled below the sub-micron regime, very thin gate dielectrics are used. One problem encountered with very thin gate dielectrics is that the carriers can tunnel through the gate dielectric material, thus increasing the undesirable leakage current in the device. By using a thin layer for conductive layer, quantum confinement of carriers within conductive layer can be induced. This quantum confinement removes modes which are propagating in the direction normal to the interfacial plane from the Fermi level. Thus, the undesirable leakage current in the device can be reduced. Additional conductive layers may be used to provide more carriers.
摘要翻译：描述了具有导电层薄的栅极的半导体器件。由于半导体器件的物理尺寸缩小到亚微米级以下，所以使用非常薄的栅极电介质。非常薄的栅极电介质遇到的一个问题是载流子可以穿过栅极电介质材料，从而增加器件中不希望的泄漏电流。通过使用导电层的薄层，可以诱导导电层内的载流子的量子限制。该量子限制去除了从费米能级垂直于界面的方向传播的模式。因此，可以减少器件中不期望的泄漏电流。附加的导电层可用于提供更多的载体。

6. 发明申请

US20060060928A1 Semiconductor device having a gate with a thin conductive layer 有权
标题翻译：具有具有薄导电层的栅极的半导体器件
公开(公告)号：US20060060928A1
公开(公告)日：2006-03-23
申请号：US10944306
申请日：2004-09-17
申请人： Sinan Goktepeli , Alexander Demkov , Marius Orlowski
发明人： Sinan Goktepeli , Alexander Demkov , Marius Orlowski
IPC分类号： H01L29/76
CPC分类号： H01L29/42372
摘要： A semiconductor device (10) having a gate (16, 18 or 16, 18, 26, 28) with a thin conductive layer (18) is described. As the physical dimensions of semiconductor devices are scaled below the sub-micron regime, very thin gate dielectrics (16) are used. One problem encountered with very thin gate dielectrics is that the carriers can tunnel through the gate dielectric material, thus increasing the undesirable leakage current in the device. By using a thin layer for conductive layer (18), quantum confinement of carriers within conductive layer (18) can be induced. This quantum confinement removes modes which are propagating in the direction normal to the interfacial plane 15 from the Fermi level. Thus, the undesirable leakage current in the device (10) can be reduced. Additional conductive layers (e.g. 28) may be used to provide more carriers.
摘要翻译：描述了具有薄导电层（18）的栅极（16,18或16,18,26,28）的半导体器件（10）。由于半导体器件的物理尺寸缩小到亚微米级以下，所以使用非常薄的栅极电介质（16）。非常薄的栅极电介质遇到的一个问题是载流子可以穿过栅极电介质材料，从而增加器件中不希望的泄漏电流。通过使用用于导电层（18）的薄层，可以诱导导电层（18）内的载流子的量子限制。该量子限制去除了从费米能级垂直于界面15的方向传播的模式。因此，可以减少装置（10）中不期望的泄漏电流。附加的导电层（例如28）可用于提供更多的载体。

7. 发明申请

US20070176247A1 MOS device with multi-layer gate stack 有权
标题翻译：具有多层栅极堆叠的MOS器件
公开(公告)号：US20070176247A1
公开(公告)日：2007-08-02
申请号：US11343623
申请日：2006-01-30
申请人： Chun-Li Liu , Marius Orlowski , Matthew Stoker
发明人： Chun-Li Liu , Marius Orlowski , Matthew Stoker
IPC分类号： H01L29/94
CPC分类号： H01L29/4975 , H01L21/28097 , H01L29/517 , H01L29/518 , H01L29/78
摘要： Methods and apparatus are provided for semiconductor devices. The apparatus comprises a substrate having therein a source region and a drain region separated by a channel region extending to a first surface of the substrate, and a multilayered gate structure located above the channel region. The gate structure comprises, a gate dielectric, preferably of an oxide of Hf, Zr or HfZr substantially in contact with the channel region, a first conductor layer of, for example an oxide of MoSi overlying the gate dielectric, a second conductor layer of, e.g., poly-Si, overlying the first conductor layer and adapted to apply an electrical field to the channel region, and an impurity migration inhibiting layer (e.g., MoSi) located above or below the first conductor layer and adapted to inhibit migration of a mobile impurity, such as oxygen for example, toward the substrate.
摘要翻译：为半导体器件提供了方法和装置。该装置包括其中具有源极区和漏极区的衬底，漏极区被延伸到衬底的第一表面的沟道区分离，以及位于沟道区上方的多层栅极结构。栅极结构包括：栅极电介质，优选地与沟道区基本上接触的Hf，Zr或HfZr的氧化物，例如覆盖栅极电介质的MoSi的氧化物的第一导体层，例如多晶硅，覆盖在第一导体层上并且适于向沟道区施加电场，以及位于第一导体层上方或下方的杂质迁移抑制层（例如MoSi），并适于抑制移动杂质，例如氧气，朝向衬底。

8. 发明申请

US20060166492A1 Semiconductor fabrication process employing stress inducing source drain structures with graded impurity concentration 有权
标题翻译：采用具有渐变杂质浓度的应力诱导源极漏极结构的半导体制造工艺
公开(公告)号：US20060166492A1
公开(公告)日：2006-07-27
申请号：US11043577
申请日：2005-01-26
申请人： Marius Orlowski , Vance Adams , Chun-Li Liu , Matthew Stoker
发明人： Marius Orlowski , Vance Adams , Chun-Li Liu , Matthew Stoker
IPC分类号： H01L21/4763
CPC分类号： H01L29/66545 , H01L21/28061 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/665 , H01L29/6656 , H01L29/66636 , H01L29/7833 , H01L29/7834 , H01L29/7848
摘要： A semiconductor fabrication process has recessed stress-inducing source/drain (SISD) structures that are formed using a multiple phase formation process. The SISD structures are semiconductor structures having a lattice constant that differs from a lattice constant of the semiconductor substrate in which the source/drain structures are recessed. The SISD structures preferably include semiconductor compound having a first element (e.g., silicon) and a second element (e.g., germanium or carbon). The SISD structure has a composition gradient wherein the percentage of the second element varies from the upper surface of the source/drain structure to a lower surface of the SISD structure. The SISD structure may include a first layer with a first composition of the semiconductor compound underlying a second layer with a second composition of the semiconductor compound. The second layer may include an impurity and have a higher percentage of the second element that the first layer.
摘要翻译：半导体制造工艺具有使用多相形成工艺形成的凹陷的应力诱导源极/漏极（SISD）结构。 SISD结构是具有不同于源/漏结构凹陷的半导体衬底的晶格常数的晶格常数的半导体结构。 SISD结构优选包括具有第一元素（例如硅）和第二元素（例如锗或碳）的半导体化合物。 SISD结构具有组成梯度，其中第二元素的百分比从源极/漏极结构的上表面到SISD结构的下表面变化。 SISD结构可以包括具有半导体化合物的第一组成的第一层，位于第二层下面，半导体化合物的第二组成。第二层可以包括杂质，并且具有比第一层更高百分比的第二元素。

9. 发明申请

US20070026593A1 Diffusion barrier for nickel silicides in a semiconductor fabrication process 有权
标题翻译：半导体制造工艺中硅化镍的扩散阻挡层
公开(公告)号：US20070026593A1
公开(公告)日：2007-02-01
申请号：US11192968
申请日：2005-07-29
申请人： Dharmesh Jawarani , Chun-Li Liu , Marius Orlowski
发明人： Dharmesh Jawarani , Chun-Li Liu , Marius Orlowski
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L29/665 , H01L29/1083 , H01L29/4925 , H01L29/66636 , H01L29/7834
摘要： A semiconductor fabrication method includes forming a gate module overlying a substrate. Recesses are etched in the substrate using the gate module as a mask. A barrier layer is deposited over the wafer and anisotropically etched to form barrier “curtains” on sidewalls of the source/drain recesses. A metal layer is deposited wherein the metal layer contacts a semiconductor within the recess. The wafer is annealed to form a silicide selectively. The diffusivity of the metal with respect to the barrier structure material is an order of magnitude less than the diffusivity of the metal with respect to the semiconductor material. The etched recesses may include re-entrant sidewalls. The metal layer may be a nickel layer and the barrier layer may be a titanium nitride layer. Silicon or silicon germanium epitaxial structures may be formed in the recesses overlying the semiconductor substrate.
摘要翻译：半导体制造方法包括形成覆盖在基板上的栅极模块。使用栅极模块作为掩模在衬底中蚀刻凹陷。阻挡层沉积在晶片上并进行各向异性蚀刻以在源极/漏极凹槽的侧壁上形成屏障“窗帘”。沉积金属层，其中金属层与凹槽内的半导体接触。将晶片退火以选择性地形成硅化物。金属相对于阻挡结构材料的扩散率比金属相对于半导体材料的扩散率小一个数量级。蚀刻的凹槽可以包括再入口侧壁。金属层可以是镍层，阻挡层可以是氮化钛层。可以在覆盖半导体衬底的凹部中形成硅或硅锗外延结构。

10. 发明申请

US20060043498A1 Method and apparatus for performance enhancement in an asymmetrical semiconductor device 有权
标题翻译：用于不对称半导体器件中的性能增强的方法和装置
公开(公告)号：US20060043498A1
公开(公告)日：2006-03-02
申请号：US10924650
申请日：2004-08-24
申请人： Marius Orlowski , Vance Adams , Chun-Li Liu , Brian Winstead
发明人： Marius Orlowski , Vance Adams , Chun-Li Liu , Brian Winstead
IPC分类号： H01L29/76
CPC分类号： H01L29/0847 , H01L29/66636 , H01L29/66659 , H01L29/7835
摘要： A method and apparatus is presented that provides performance enhancement in a semiconductor device. In one embodiment, a first current region (64, 76, 23), a channel region and a second current region (75, 33, 66) are adjacent each other. The second current region (75, 33, 66) has a content of a first element of an alloy greater than a content of the first element in the first current region (64, 76, 23), wherein the second current region (75, 33, 66) has a content of the first element greater than a content of the first element in the channel region, the alloy further comprises a second element, the first element has a first valence number, and the second element has a second valence number. Furthermore, the sum of the first valence number and the second valence number is eight.
摘要翻译：提出了一种在半导体器件中提供性能增强的方法和装置。在一个实施例中，第一电流区域（64,76,23），沟道区域和第二电流区域（75,33,66）彼此相邻。第二电流区域（75,33,66）具有比第一电流区域（64,76,23）中的第一元件的含量大的合金的第一元素的含量，其中第二电流区域（75，所述第一元件的含量大于所述沟道区域中的所述第一元素的含量，所述合金还包括第二元素，所述第一元素具有第一价数，并且所述第二元素具有第二价数。此外，第一价数和第二价数之和为八。

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