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1. 发明申请

US20060043498A1 Method and apparatus for performance enhancement in an asymmetrical semiconductor device 有权
标题翻译：用于不对称半导体器件中的性能增强的方法和装置
公开(公告)号：US20060043498A1
公开(公告)日：2006-03-02
申请号：US10924650
申请日：2004-08-24
申请人： Marius Orlowski , Vance Adams , Chun-Li Liu , Brian Winstead
发明人： Marius Orlowski , Vance Adams , Chun-Li Liu , Brian Winstead
IPC分类号： H01L29/76
CPC分类号： H01L29/0847 , H01L29/66636 , H01L29/66659 , H01L29/7835
摘要： A method and apparatus is presented that provides performance enhancement in a semiconductor device. In one embodiment, a first current region (64, 76, 23), a channel region and a second current region (75, 33, 66) are adjacent each other. The second current region (75, 33, 66) has a content of a first element of an alloy greater than a content of the first element in the first current region (64, 76, 23), wherein the second current region (75, 33, 66) has a content of the first element greater than a content of the first element in the channel region, the alloy further comprises a second element, the first element has a first valence number, and the second element has a second valence number. Furthermore, the sum of the first valence number and the second valence number is eight.
摘要翻译：提出了一种在半导体器件中提供性能增强的方法和装置。在一个实施例中，第一电流区域（64,76,23），沟道区域和第二电流区域（75,33,66）彼此相邻。第二电流区域（75,33,66）具有比第一电流区域（64,76,23）中的第一元件的含量大的合金的第一元素的含量，其中第二电流区域（75，所述第一元件的含量大于所述沟道区域中的所述第一元素的含量，所述合金还包括第二元素，所述第一元素具有第一价数，并且所述第二元素具有第二价数。此外，第一价数和第二价数之和为八。

2. 发明申请

US20060166492A1 Semiconductor fabrication process employing stress inducing source drain structures with graded impurity concentration 有权
标题翻译：采用具有渐变杂质浓度的应力诱导源极漏极结构的半导体制造工艺
公开(公告)号：US20060166492A1
公开(公告)日：2006-07-27
申请号：US11043577
申请日：2005-01-26
申请人： Marius Orlowski , Vance Adams , Chun-Li Liu , Matthew Stoker
发明人： Marius Orlowski , Vance Adams , Chun-Li Liu , Matthew Stoker
IPC分类号： H01L21/4763
CPC分类号： H01L29/66545 , H01L21/28061 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/665 , H01L29/6656 , H01L29/66636 , H01L29/7833 , H01L29/7834 , H01L29/7848
摘要： A semiconductor fabrication process has recessed stress-inducing source/drain (SISD) structures that are formed using a multiple phase formation process. The SISD structures are semiconductor structures having a lattice constant that differs from a lattice constant of the semiconductor substrate in which the source/drain structures are recessed. The SISD structures preferably include semiconductor compound having a first element (e.g., silicon) and a second element (e.g., germanium or carbon). The SISD structure has a composition gradient wherein the percentage of the second element varies from the upper surface of the source/drain structure to a lower surface of the SISD structure. The SISD structure may include a first layer with a first composition of the semiconductor compound underlying a second layer with a second composition of the semiconductor compound. The second layer may include an impurity and have a higher percentage of the second element that the first layer.
摘要翻译：半导体制造工艺具有使用多相形成工艺形成的凹陷的应力诱导源极/漏极（SISD）结构。 SISD结构是具有不同于源/漏结构凹陷的半导体衬底的晶格常数的晶格常数的半导体结构。 SISD结构优选包括具有第一元素（例如硅）和第二元素（例如锗或碳）的半导体化合物。 SISD结构具有组成梯度，其中第二元素的百分比从源极/漏极结构的上表面到SISD结构的下表面变化。 SISD结构可以包括具有半导体化合物的第一组成的第一层，位于第二层下面，半导体化合物的第二组成。第二层可以包括杂质，并且具有比第一层更高百分比的第二元素。

3. 发明申请

US20070176247A1 MOS device with multi-layer gate stack 有权
标题翻译：具有多层栅极堆叠的MOS器件
公开(公告)号：US20070176247A1
公开(公告)日：2007-08-02
申请号：US11343623
申请日：2006-01-30
申请人： Chun-Li Liu , Marius Orlowski , Matthew Stoker
发明人： Chun-Li Liu , Marius Orlowski , Matthew Stoker
IPC分类号： H01L29/94
CPC分类号： H01L29/4975 , H01L21/28097 , H01L29/517 , H01L29/518 , H01L29/78
摘要： Methods and apparatus are provided for semiconductor devices. The apparatus comprises a substrate having therein a source region and a drain region separated by a channel region extending to a first surface of the substrate, and a multilayered gate structure located above the channel region. The gate structure comprises, a gate dielectric, preferably of an oxide of Hf, Zr or HfZr substantially in contact with the channel region, a first conductor layer of, for example an oxide of MoSi overlying the gate dielectric, a second conductor layer of, e.g., poly-Si, overlying the first conductor layer and adapted to apply an electrical field to the channel region, and an impurity migration inhibiting layer (e.g., MoSi) located above or below the first conductor layer and adapted to inhibit migration of a mobile impurity, such as oxygen for example, toward the substrate.
摘要翻译：为半导体器件提供了方法和装置。该装置包括其中具有源极区和漏极区的衬底，漏极区被延伸到衬底的第一表面的沟道区分离，以及位于沟道区上方的多层栅极结构。栅极结构包括：栅极电介质，优选地与沟道区基本上接触的Hf，Zr或HfZr的氧化物，例如覆盖栅极电介质的MoSi的氧化物的第一导体层，例如多晶硅，覆盖在第一导体层上并且适于向沟道区施加电场，以及位于第一导体层上方或下方的杂质迁移抑制层（例如MoSi），并适于抑制移动杂质，例如氧气，朝向衬底。

4. 发明申请

US20070026593A1 Diffusion barrier for nickel silicides in a semiconductor fabrication process 有权
标题翻译：半导体制造工艺中硅化镍的扩散阻挡层
公开(公告)号：US20070026593A1
公开(公告)日：2007-02-01
申请号：US11192968
申请日：2005-07-29
申请人： Dharmesh Jawarani , Chun-Li Liu , Marius Orlowski
发明人： Dharmesh Jawarani , Chun-Li Liu , Marius Orlowski
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L29/665 , H01L29/1083 , H01L29/4925 , H01L29/66636 , H01L29/7834
摘要： A semiconductor fabrication method includes forming a gate module overlying a substrate. Recesses are etched in the substrate using the gate module as a mask. A barrier layer is deposited over the wafer and anisotropically etched to form barrier “curtains” on sidewalls of the source/drain recesses. A metal layer is deposited wherein the metal layer contacts a semiconductor within the recess. The wafer is annealed to form a silicide selectively. The diffusivity of the metal with respect to the barrier structure material is an order of magnitude less than the diffusivity of the metal with respect to the semiconductor material. The etched recesses may include re-entrant sidewalls. The metal layer may be a nickel layer and the barrier layer may be a titanium nitride layer. Silicon or silicon germanium epitaxial structures may be formed in the recesses overlying the semiconductor substrate.
摘要翻译：半导体制造方法包括形成覆盖在基板上的栅极模块。使用栅极模块作为掩模在衬底中蚀刻凹陷。阻挡层沉积在晶片上并进行各向异性蚀刻以在源极/漏极凹槽的侧壁上形成屏障“窗帘”。沉积金属层，其中金属层与凹槽内的半导体接触。将晶片退火以选择性地形成硅化物。金属相对于阻挡结构材料的扩散率比金属相对于半导体材料的扩散率小一个数量级。蚀刻的凹槽可以包括再入口侧壁。金属层可以是镍层，阻挡层可以是氮化钛层。可以在覆盖半导体衬底的凹部中形成硅或硅锗外延结构。

5. 发明申请

US20050070056A1 SOI template layer 有权
标题翻译： SOI模板层
公开(公告)号：US20050070056A1
公开(公告)日：2005-03-31
申请号：US10670928
申请日：2003-09-25
申请人： Chun-Li Liu , Marius Orlowski , Matthew Stoker , Philip Tobin , Mariam Sadaka , Alexander Barr , Bich-Yen Nguyen , Voon-Yew Thean , Shawn Thomas , Ted White
发明人： Chun-Li Liu , Marius Orlowski , Matthew Stoker , Philip Tobin , Mariam Sadaka , Alexander Barr , Bich-Yen Nguyen , Voon-Yew Thean , Shawn Thomas , Ted White
IPC分类号： H01L20060101 , H01L21/00 , H01L21/338
CPC分类号： H01L29/161 , H01L21/26506 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L29/1054 , Y10S438/933
摘要： A vacancy injecting process for injecting vacancies in template layer material of an SOI substrate. The template layer material has a crystalline structure that includes, in some embodiments, both germanium and silicon atoms. A strained silicon layer is then epitaxially grown on the template layer material with the beneficial effects that straining has on electron and hole mobility. The vacancy injecting process is performed to inject vacancies and germanium atoms into the crystalline structure wherein germanium atoms recombine with the vacancies. One embodiment, a nitridation process is performed to grow a nitride layer on the template layer material and consume silicon in a way that injects vacancies in the crystalline structure while also allowing germanium atoms to recombine with the vacancies. Other examples of a vacancy injecting processes include silicidation processes, oxynitridation processes, oxidation processes with a chloride bearing gas, or inert gas post bake processes subsequent to an oxidation process.
摘要翻译：用于在SOI衬底的模板层材料中注入空位的空位注入工艺。模板层材料具有在一些实施方案中包括锗和硅原子的晶体结构。然后在模板层材料上外延生长应变硅层，具有应力对电子和空穴迁移率的有益效果。进行空位注入处理以将空位和锗原子注入晶格结构中，其中锗原子与空位重新组合。一个实施方案中，进行氮化处理以在模板层材料上生长氮化物层，并以注入晶体结构中的空位并且还允许锗原子与空位复合的方式消耗硅。空位注入方法的其它实例包括硅化工艺，氧氮化工艺，含氯化物气体的氧化工艺或氧化工艺之后的惰性气体后烘烤工艺。

6. 发明授权

US07221006B2 GeSOI transistor with low junction current and low junction capacitance and method for making the same 有权
标题翻译：具有低结电流和低结电容的GeSOI晶体管及其制造方法
公开(公告)号：US07221006B2
公开(公告)日：2007-05-22
申请号：US11110234
申请日：2005-04-20
申请人： Marius Orlowski , Sinan Goktepeli , Chun-Li Liu
发明人： Marius Orlowski , Sinan Goktepeli , Chun-Li Liu
IPC分类号： H01L31/00
CPC分类号： H01L29/7848 , H01L21/7624 , H01L29/165 , H01L29/66545 , H01L29/66636
摘要： A semiconductor device (101) is provided herein which comprises a substrate (103) comprising germanium. The substrate has source (107) and drain (109) regions defined therein. A barrier layer (111) comprising a first material that has a higher bandgap (Eg) than germanium is disposed at the boundary of at least one of said source and drain regions. At least one of the source and drain regions comprises germanium.
摘要翻译：本文提供了一种包括包含锗的衬底（103）的半导体器件（101）。衬底具有限定在其中的源极（107）和漏极（109）。包括具有比锗更高的带隙（E））的第一材料的阻挡层（111）设置在所述源极和漏极区域中的至少一个的边界处。源区和漏区中的至少一个包括锗。

7. 发明申请

US20070096226A1 MOSFET dielectric including a diffusion barrier 审中-公开
标题翻译： MOSFET电介质包括扩散阻挡层
公开(公告)号：US20070096226A1
公开(公告)日：2007-05-03
申请号：US11264069
申请日：2005-10-31
申请人： Chun-Li Liu , Tushar Merchant , Marius Orlowski , James Schaeffer , Matthew Stoker
发明人： Chun-Li Liu , Tushar Merchant , Marius Orlowski , James Schaeffer , Matthew Stoker
IPC分类号： H01L29/94 , H01L29/76 , H01L31/00
CPC分类号： H01L29/513 , H01L21/28194 , H01L21/28211 , H01L29/517 , H01L29/665 , H01L29/66575
摘要： A semiconductor device includes a substrate, a multilayered assembly of high k dielectric materials formed on the substrate, and a first conducting material formed on the upper layer of the assembly of high k dielectric materials. The multilayered high k dielectric assembly includes a lower layer, an upper layer, and a diffusion barrier layer formed between the lower and upper dielectric layers. The diffusion barrier layer has a greater affinity for oxygen than the upper and lower layers. The first conducting layer includes a conducting compound of at least a metal element and oxygen.
摘要翻译：半导体器件包括衬底，形成在衬底上的高k电介质材料的多层组件和形成在高k电介质材料的组件的上层上的第一导电材料。多层高k电介质组件包括下层，上层和形成在下介电层和上电介质层之间的扩散阻挡层。扩散阻挡层与上层和下层具有比氧更大的亲和性。第一导电层包括至少金属元素和氧的导电化合物。

8. 发明申请

US20070176227A1 MOS device with nano-crystal gate structure 有权
标题翻译：具有纳米晶体栅结构的MOS器件
公开(公告)号：US20070176227A1
公开(公告)日：2007-08-02
申请号：US11343624
申请日：2006-01-30
申请人： Chun-Li Liu , Tushar Merchant , Marius Orlowski , Matthew Stoker
发明人： Chun-Li Liu , Tushar Merchant , Marius Orlowski , Matthew Stoker
IPC分类号： H01L29/792 , H01L21/8238
CPC分类号： H01L29/7883 , B82Y10/00 , H01L21/28273 , H01L29/42332 , H01L29/513 , H01L29/66825 , H01L29/78
摘要： Methods and apparatus are provided for non-volatile semiconductor devices. The apparatus comprises a substrate having therein a source region and a drain region separated by a channel region extending to a first surface of the substrate, and a multilayered gate structure containing nano-crystals located above the channel region. The gate structure comprises, a gate dielectric substantially in contact with the channel region, spaced-apart nano-crystals disposed in the gate dielectric, one or more impurity blocking layers overlying the gate dielectric and a gate conductor layer overlying the one more impurity blocking layers. The blocking layer nearest the gate conductor can also be used to adjust the threshold voltage of the device and/or retard dopant out-diffusion from the gate conductor layer.
摘要翻译：为非易失性半导体器件提供了方法和装置。该装置包括其中具有源极区域和漏极区域的衬底，漏极区域被延伸到衬底的第一表面的沟道区域分开，以及包含位于沟道区域上方的纳米晶体的多层栅极结构。栅极结构包括：基本上与沟道区接触的栅极电介质，设置在栅极电介质中的间隔开的纳米晶体，覆盖栅极电介质的一个或多个杂质阻挡层和覆盖一个以上杂质阻挡层的栅极导体层。最靠近栅极导体的阻挡层也可用于调节器件的阈值电压和/或从栅极导体层延迟掺杂剂扩散。

9. 发明申请

US20060237746A1 GeSOI transistor with low junction current and low junction capacitance and method for making the same 有权
标题翻译：具有低结电流和低结电容的GeSOI晶体管及其制造方法
公开(公告)号：US20060237746A1
公开(公告)日：2006-10-26
申请号：US11110234
申请日：2005-04-20
申请人： Marius Orlowski , Sinan Goktepeli , Chun-Li Liu
发明人： Marius Orlowski , Sinan Goktepeli , Chun-Li Liu
IPC分类号： H01L31/00
CPC分类号： H01L29/7848 , H01L21/7624 , H01L29/165 , H01L29/66545 , H01L29/66636
摘要： A semiconductor device (101) is provided herein which comprises a substrate (103) comprising germanium. The substrate has source (107) and drain (109) regions defined therein. A barrier layer (111) comprising a first material that has a higher bandgap (Eg) than germanium is disposed at the boundary of at least one of said source and drain regions. At least one of the source and drain regions comprises germanium.
摘要翻译：本文提供了一种包括包含锗的衬底（103）的半导体器件（101）。衬底具有限定在其中的源极（107）和漏极（109）。包括具有比锗更高的带隙（E））的第一材料的阻挡层（111）设置在所述源极和漏极区域中的至少一个的边界处。源区和漏区中的至少一个包括锗。

10. 发明申请

US20050260807A1 Method for making a semiconductor structure using silicon germanium 有权
标题翻译：使用硅锗制造半导体结构的方法
公开(公告)号：US20050260807A1
公开(公告)日：2005-11-24
申请号：US10851347
申请日：2004-05-21
申请人： Marius Orlowski , Chun-Li Liu , Choh-Fei Yeap
发明人： Marius Orlowski , Chun-Li Liu , Choh-Fei Yeap
IPC分类号： H01L21/336 , H01L21/8234 , H01L29/08 , H01L29/10 , H01L29/78 , H01L29/786
CPC分类号： H01L29/0847 , H01L29/1033 , H01L29/66628 , H01L29/66742 , H01L29/66772 , H01L29/7834 , H01L29/78606 , H01L29/78639 , H01L29/78687
摘要： Silicon carbon is used as a diffusion barrier to germanium so that a silicon layer can be subsequently formed without being contaminated with germanium. This is useful in separating silicon layers from silicon germanium layers in situations in which both silicon and silicon germanium are desired to be present on the same semiconductor device such as for providing different materials for optimizing carrier mobility between N and P channel transistors and for a raised source/drain of silicon in the case of a silicon germanium body.
摘要翻译：硅碳被用作锗的扩散阻挡层，从而可以随后形成硅层而不被锗污染。这在硅硅层分离的同时，硅和硅锗希望存在于同一半导体器件上，例如为了提供不同的材料以优化N沟道晶体管和P沟道晶体管之间的载流子迁移率，在硅锗体的情况下硅的源极/漏极。

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