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1. 发明申请

US20070218640A1 SEMICONDUCTOR DEVICE HAVING A GATE WITH A THIN CONDUCTIVE LAYER 审中-公开
标题翻译：具有薄导电层的栅极的半导体器件
公开(公告)号：US20070218640A1
公开(公告)日：2007-09-20
申请号：US11752544
申请日：2007-05-23
申请人： Sinan Goktepeli , Alexander Demkov , Marius Orlowski
发明人： Sinan Goktepeli , Alexander Demkov , Marius Orlowski
IPC分类号： H01L21/336
CPC分类号： H01L29/42372
摘要： A semiconductor device having a gate with a thin conductive layer is described. As the physical dimensions of semiconductor devices are scaled below the sub-micron regime, very thin gate dielectrics are used. One problem encountered with very thin gate dielectrics is that the carriers can tunnel through the gate dielectric material, thus increasing the undesirable leakage current in the device. By using a thin layer for conductive layer, quantum confinement of carriers within conductive layer can be induced. This quantum confinement removes modes which are propagating in the direction normal to the interfacial plane from the Fermi level. Thus, the undesirable leakage current in the device can be reduced. Additional conductive layers may be used to provide more carriers.
摘要翻译：描述了具有导电层薄的栅极的半导体器件。由于半导体器件的物理尺寸缩小到亚微米级以下，所以使用非常薄的栅极电介质。非常薄的栅极电介质遇到的一个问题是载流子可以穿过栅极电介质材料，从而增加器件中不希望的泄漏电流。通过使用导电层的薄层，可以诱导导电层内的载流子的量子限制。该量子限制去除了从费米能级垂直于界面的方向传播的模式。因此，可以减少器件中不期望的泄漏电流。附加的导电层可用于提供更多的载体。

2. 发明申请

US20060060928A1 Semiconductor device having a gate with a thin conductive layer 有权
标题翻译：具有具有薄导电层的栅极的半导体器件
公开(公告)号：US20060060928A1
公开(公告)日：2006-03-23
申请号：US10944306
申请日：2004-09-17
申请人： Sinan Goktepeli , Alexander Demkov , Marius Orlowski
发明人： Sinan Goktepeli , Alexander Demkov , Marius Orlowski
IPC分类号： H01L29/76
CPC分类号： H01L29/42372
摘要： A semiconductor device (10) having a gate (16, 18 or 16, 18, 26, 28) with a thin conductive layer (18) is described. As the physical dimensions of semiconductor devices are scaled below the sub-micron regime, very thin gate dielectrics (16) are used. One problem encountered with very thin gate dielectrics is that the carriers can tunnel through the gate dielectric material, thus increasing the undesirable leakage current in the device. By using a thin layer for conductive layer (18), quantum confinement of carriers within conductive layer (18) can be induced. This quantum confinement removes modes which are propagating in the direction normal to the interfacial plane 15 from the Fermi level. Thus, the undesirable leakage current in the device (10) can be reduced. Additional conductive layers (e.g. 28) may be used to provide more carriers.
摘要翻译：描述了具有薄导电层（18）的栅极（16,18或16,18,26,28）的半导体器件（10）。由于半导体器件的物理尺寸缩小到亚微米级以下，所以使用非常薄的栅极电介质（16）。非常薄的栅极电介质遇到的一个问题是载流子可以穿过栅极电介质材料，从而增加器件中不希望的泄漏电流。通过使用用于导电层（18）的薄层，可以诱导导电层（18）内的载流子的量子限制。该量子限制去除了从费米能级垂直于界面15的方向传播的模式。因此，可以减少装置（10）中不期望的泄漏电流。附加的导电层（例如28）可用于提供更多的载体。

3. 发明申请

US20060131671A1 ELECTRONIC DEVICE INCLUDING DIELECTRIC LAYER, AND A PROCESS FOR FORMING THE ELECTRONIC DEVICE 有权
标题翻译：包括介电层的电子器件，以及形成电子器件的方法
公开(公告)号：US20060131671A1
公开(公告)日：2006-06-22
申请号：US11023014
申请日：2004-12-22
申请人： Rama Hegde , Alexander Demkov , Philip Tobin , Dina Triyoso
发明人： Rama Hegde , Alexander Demkov , Philip Tobin , Dina Triyoso
IPC分类号： H01L21/00 , H01L21/8242 , H01L21/336 , H01L29/76 , H01L29/94 , H01L23/48
CPC分类号： H01L29/517 , C23C16/45529 , C23C16/45531 , H01L21/02181 , H01L21/02189 , H01L21/02194 , H01L21/28185 , H01L21/28194 , H01L21/28229 , H01L21/3141 , H01L21/31641 , H01L21/31645 , H01L21/823842 , H01L29/4966
摘要： A mixture of materials can be used within a layer of an electronic device to improve electrical and physical properties of the layer. In one set of embodiments, the layer can be a dielectric layer, such as a gate dielectric layer or a capacitor dielectric layer. The dielectric layer can include O, and two or more dissimilar metallic elements. In one specific embodiment, two dissimilar elements may have the same single oxidation state and be miscible within each other. In one embodiment, the dielectric layer can include an alloy of (HfO2)(1-x)(ZrO2)x, wherein x is between 0 and 1. Each of Hf and Zr has a single oxidation state of +4. Other combinations are possible. Improved electrical and physical properties can include better control over grain size, distribution of grain sizes, thickness of the layer across a substrate, improved carrier mobility, threshold voltage stability, or any combination thereof.
摘要翻译：材料的混合物可以在电子器件的层内使用，以改善该层的电学和物理性质。在一组实施例中，该层可以是介电层，例如栅极介电层或电容器电介质层。电介质层可以包括O和两个或多个不同的金属元素。在一个具体实施方式中，两个不同的元件可以具有相同的单一氧化状态并且彼此可混溶。在一个实施例中，电介质层可以包括（HfO 2 2）（1-x）（ZrO 2 2）x 其中x在0和1之间.Hf和Zr中的每一个具有+4的单一氧化态。其他组合是可能的。改善的电学和物理性质可以包括更好地控制晶粒尺寸，晶粒尺寸分布，跨越衬底的层的厚度，改进的载流子迁移率，阈值电压稳定性或其任何组合。

4. 发明授权

US07141857B2 Semiconductor structures and methods of fabricating semiconductor structures comprising hafnium oxide modified with lanthanum, a lanthanide-series metal, or a combination thereof 有权
公开(公告)号：US07141857B2
公开(公告)日：2006-11-28
申请号：US10883180
申请日：2004-06-30
申请人： Zhiyi Yu , Jay A. Curless , Yong Liang , Alexandra Navrotsky , Sergey Ushakov , Bich-Yen Nguyen , Alexander Demkov
发明人： Zhiyi Yu , Jay A. Curless , Yong Liang , Alexandra Navrotsky , Sergey Ushakov , Bich-Yen Nguyen , Alexander Demkov
IPC分类号： H01L29/94 , H01L21/469
CPC分类号： H01L21/02181 , C23C14/0026 , C23C14/083 , H01L21/02192 , H01L21/0234 , H01L21/28194 , H01L21/3115 , H01L21/31645 , H01L29/513 , H01L29/517
摘要： Semiconductor structures and processes for fabricating semiconductor structures comprising hafnium oxide layers modified with lanthanum oxide or a lanthanide-series metal oxide are provided. A semiconductor structure in accordance with an embodiment of the invention comprises an amorphous layer of hafnium oxide overlying a substrate. A lanthanum-containing dopant or a lanthanide-series metal-containing dopant is comprised within the amorphous layer of hafnium oxide. The process comprises growing an amorphous layer of hafnium oxide overlying a substrate. The amorphous layer of hafnium oxide is doped with a dopant having the chemical formulation LnOx, where Ln is lanthanum, a lanthanide-series metal, or a combination thereof, and X is any number greater than zero. The doping step may be performed during or after growth of the amorphous layer of hafnium oxide.

5. 发明申请

US20060094249A1 Semiconductor structure having a metallic buffer layer and method for forming 有权
标题翻译：具有金属缓冲层的半导体结构和形成方法
公开(公告)号：US20060094249A1
公开(公告)日：2006-05-04
申请号：US10977727
申请日：2004-10-29
申请人： Alexander Demkov , William Taylor
发明人： Alexander Demkov , William Taylor
IPC分类号： H01L21/338 , H01L21/31 , H01L21/469
CPC分类号： H01L21/823412 , H01L21/02381 , H01L21/02491 , H01L21/02532 , H01L21/02667 , H01L29/7833
摘要： A method for forming a semiconductor structure including providing a semiconductor substrate, forming a metallic buffer layer over the semiconductor substrate, forming an amorphous semiconductor layer over the metallic buffer layer, and recrystallizing the amorphous semiconductor layer to form a crystalline semiconductor layer. A semiconductor structure includes a semiconductor substrate, a buffer layer comprising at least one of silicide and germanide formed over the semiconductor substrate, and a crystalline semiconductor layer formed over the metallic buffer layer.
摘要翻译：一种用于形成半导体结构的方法，包括：提供半导体衬底，在所述半导体衬底上形成金属缓冲层，在所述金属缓冲层上形成非晶半导体层，以及使所述非晶半导体层再结晶以形成晶体半导体层。半导体结构包括半导体衬底，包括形成在半导体衬底上的硅化物和锗化物中的至少一种的缓冲层以及形成在金属缓冲层上的晶体半导体层。

6. 发明授权

US06479173B1 Semiconductor structure having a crystalline alkaline earth metal silicon nitride/oxide interface with silicon 失效
标题翻译：具有结晶碱土金属氮化硅/氧化物与硅的界面的半导体结构
公开(公告)号：US06479173B1
公开(公告)日：2002-11-12
申请号：US09465623
申请日：1999-12-17
申请人： Zhiyi Yu , Jun Wang , Ravindranath Droopad , Alexander Demkov , Jerald Allan Hallmark , Jamal Ramdani
发明人： Zhiyi Yu , Jun Wang , Ravindranath Droopad , Alexander Demkov , Jerald Allan Hallmark , Jamal Ramdani
IPC分类号： B32B900
CPC分类号： H01L21/3144 , H01L21/31691 , H01L21/318 , H01L28/56
摘要： A semiconductor structure comprises a silicon substrate (10), one or more layers of single crystal oxides or nitrides (26), and an interface (14) between the silicon substrate and the one or more layers of single crystal oxides or nitrides, the interface manufactured with a crystalline material which matches the lattice constant of silicon. The interface comprises an atomic layer of silicon, nitrogen, and a metal in the form MSiN2, where M is a metal. In a second embodiment, the interface comprises an atomic layer of silicon, a metal, and a mixture of nitrogen and oxygen in the form MSi[N1−xOx]2, where M is a metal and X is 0≦X
摘要翻译：半导体结构包括硅衬底（10），一层或多层单晶氧化物或氮化物（26），以及在硅衬底和一层或多层单晶氧化物或氮化物之间的界面（14），界面用与硅的晶格常数匹配的结晶材料制成。该界面包括硅，氮和MSiN 2形式的金属的原子层，其中M是金属。在第二个实施方案中，界面包括形式为MSi [N1-xOx] 2的硅原子层，金属和氮和氧的混合物，其中M是金属，X是0 <= X <1。

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