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1. 发明申请

US20070218640A1 SEMICONDUCTOR DEVICE HAVING A GATE WITH A THIN CONDUCTIVE LAYER 审中-公开
标题翻译：具有薄导电层的栅极的半导体器件
公开(公告)号：US20070218640A1
公开(公告)日：2007-09-20
申请号：US11752544
申请日：2007-05-23
申请人： Sinan Goktepeli , Alexander Demkov , Marius Orlowski
发明人： Sinan Goktepeli , Alexander Demkov , Marius Orlowski
IPC分类号： H01L21/336
CPC分类号： H01L29/42372
摘要： A semiconductor device having a gate with a thin conductive layer is described. As the physical dimensions of semiconductor devices are scaled below the sub-micron regime, very thin gate dielectrics are used. One problem encountered with very thin gate dielectrics is that the carriers can tunnel through the gate dielectric material, thus increasing the undesirable leakage current in the device. By using a thin layer for conductive layer, quantum confinement of carriers within conductive layer can be induced. This quantum confinement removes modes which are propagating in the direction normal to the interfacial plane from the Fermi level. Thus, the undesirable leakage current in the device can be reduced. Additional conductive layers may be used to provide more carriers.
摘要翻译：描述了具有导电层薄的栅极的半导体器件。由于半导体器件的物理尺寸缩小到亚微米级以下，所以使用非常薄的栅极电介质。非常薄的栅极电介质遇到的一个问题是载流子可以穿过栅极电介质材料，从而增加器件中不希望的泄漏电流。通过使用导电层的薄层，可以诱导导电层内的载流子的量子限制。该量子限制去除了从费米能级垂直于界面的方向传播的模式。因此，可以减少器件中不期望的泄漏电流。附加的导电层可用于提供更多的载体。

2. 发明申请

US20060060928A1 Semiconductor device having a gate with a thin conductive layer 有权
标题翻译：具有具有薄导电层的栅极的半导体器件
公开(公告)号：US20060060928A1
公开(公告)日：2006-03-23
申请号：US10944306
申请日：2004-09-17
申请人： Sinan Goktepeli , Alexander Demkov , Marius Orlowski
发明人： Sinan Goktepeli , Alexander Demkov , Marius Orlowski
IPC分类号： H01L29/76
CPC分类号： H01L29/42372
摘要： A semiconductor device (10) having a gate (16, 18 or 16, 18, 26, 28) with a thin conductive layer (18) is described. As the physical dimensions of semiconductor devices are scaled below the sub-micron regime, very thin gate dielectrics (16) are used. One problem encountered with very thin gate dielectrics is that the carriers can tunnel through the gate dielectric material, thus increasing the undesirable leakage current in the device. By using a thin layer for conductive layer (18), quantum confinement of carriers within conductive layer (18) can be induced. This quantum confinement removes modes which are propagating in the direction normal to the interfacial plane 15 from the Fermi level. Thus, the undesirable leakage current in the device (10) can be reduced. Additional conductive layers (e.g. 28) may be used to provide more carriers.
摘要翻译：描述了具有薄导电层（18）的栅极（16,18或16,18,26,28）的半导体器件（10）。由于半导体器件的物理尺寸缩小到亚微米级以下，所以使用非常薄的栅极电介质（16）。非常薄的栅极电介质遇到的一个问题是载流子可以穿过栅极电介质材料，从而增加器件中不希望的泄漏电流。通过使用用于导电层（18）的薄层，可以诱导导电层（18）内的载流子的量子限制。该量子限制去除了从费米能级垂直于界面15的方向传播的模式。因此，可以减少装置（10）中不期望的泄漏电流。附加的导电层（例如28）可用于提供更多的载体。

3. 发明申请

US20070173024A1 Method for producing two gates controlling the same channel 有权
公开(公告)号：US20070173024A1
公开(公告)日：2007-07-26
申请号：US11339101
申请日：2006-01-25
申请人： Sinan Goktepeli , Alexander Hoefler , Marius Orlowski
发明人： Sinan Goktepeli , Alexander Hoefler , Marius Orlowski
IPC分类号： H01L21/336
CPC分类号： H01L21/28132 , H01L21/823437 , H01L21/823468 , H01L27/0705 , H01L29/66484 , H01L29/7831
摘要： A semiconductor process and apparatus use a predetermined sequence of patterning and etching steps to etch a gate stack (62) formed over a substrate (11) and a first spacer structure (42), thereby forming etched gate structures (72, 74) that are physically separated from one another but that control a substrate channel (71) subsequently defined in the substrate (11) by source/drain regions (82, 102, 84, 104) that are implanted around the etched gate structures (72, 74). Depending on how the first spacer structure (42) is positioned and configured, the channel (71) may be controlled to provide either a logical AND gate (100) or logical OR gate (200) functionality.

4. 发明申请

US20070077706A1 Method of making a multi-bit nov-volatile memory (NYM) cell and structure 有权
标题翻译：制造多位非易失性存储器（NYM）单元和结构的方法
公开(公告)号：US20070077706A1
公开(公告)日：2007-04-05
申请号：US11240242
申请日：2005-09-30
申请人： Marius Orlowski , Sinan Goktepeli
发明人： Marius Orlowski , Sinan Goktepeli
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , H01L29/42332
摘要： A multi-bit non volatile memory cell includes a first floating gate sidewall spacer structure and a second floating gate sidewall spacer structure physically separated from the first floating gate sidewall spacer structure. Each floating gate sidewall spacer structure stores charge for logically storing a bit. The floating gate sidewall spacer structures are formed adjacent to a patterned structure by sidewall spacer formation processes from a layer of floating gate material (e.g. polysilicon). A control gate is formed over the floating gate sidewall spacer structures by forming a layer of control gate material and then patterning the layer of control gate material.
摘要翻译：多位非易失性存储单元包括第一浮栅侧壁间隔结构和与第一浮栅侧壁间隔结构物理分离的第二浮栅侧壁间隔结构。每个浮栅侧壁间隔结构存储逻辑存储位的电荷。通过从浮置栅极材料层（例如多晶硅）的侧壁间隔物形成工艺，将浮栅侧壁间隔结构形成为与图案化结构相邻。通过形成控制栅极材料层，然后对控制栅极材料层进行图案化，在浮栅侧壁间隔结构上形成控制栅极。

5. 发明授权

US07221006B2 GeSOI transistor with low junction current and low junction capacitance and method for making the same 有权
标题翻译：具有低结电流和低结电容的GeSOI晶体管及其制造方法
公开(公告)号：US07221006B2
公开(公告)日：2007-05-22
申请号：US11110234
申请日：2005-04-20
申请人： Marius Orlowski , Sinan Goktepeli , Chun-Li Liu
发明人： Marius Orlowski , Sinan Goktepeli , Chun-Li Liu
IPC分类号： H01L31/00
CPC分类号： H01L29/7848 , H01L21/7624 , H01L29/165 , H01L29/66545 , H01L29/66636
摘要： A semiconductor device (101) is provided herein which comprises a substrate (103) comprising germanium. The substrate has source (107) and drain (109) regions defined therein. A barrier layer (111) comprising a first material that has a higher bandgap (Eg) than germanium is disposed at the boundary of at least one of said source and drain regions. At least one of the source and drain regions comprises germanium.
摘要翻译：本文提供了一种包括包含锗的衬底（103）的半导体器件（101）。衬底具有限定在其中的源极（107）和漏极（109）。包括具有比锗更高的带隙（E））的第一材料的阻挡层（111）设置在所述源极和漏极区域中的至少一个的边界处。源区和漏区中的至少一个包括锗。

6. 发明申请

US20060237746A1 GeSOI transistor with low junction current and low junction capacitance and method for making the same 有权
标题翻译：具有低结电流和低结电容的GeSOI晶体管及其制造方法
公开(公告)号：US20060237746A1
公开(公告)日：2006-10-26
申请号：US11110234
申请日：2005-04-20
申请人： Marius Orlowski , Sinan Goktepeli , Chun-Li Liu
发明人： Marius Orlowski , Sinan Goktepeli , Chun-Li Liu
IPC分类号： H01L31/00
CPC分类号： H01L29/7848 , H01L21/7624 , H01L29/165 , H01L29/66545 , H01L29/66636
摘要： A semiconductor device (101) is provided herein which comprises a substrate (103) comprising germanium. The substrate has source (107) and drain (109) regions defined therein. A barrier layer (111) comprising a first material that has a higher bandgap (Eg) than germanium is disposed at the boundary of at least one of said source and drain regions. At least one of the source and drain regions comprises germanium.
摘要翻译：本文提供了一种包括包含锗的衬底（103）的半导体器件（101）。衬底具有限定在其中的源极（107）和漏极（109）。包括具有比锗更高的带隙（E））的第一材料的阻挡层（111）设置在所述源极和漏极区域中的至少一个的边界处。源区和漏区中的至少一个包括锗。

7. 发明申请

US20170155045A1 Method to Manufacture Highly Conductive Vias and PROM Memory Cells by Application of Electric Pulses 审中-公开
公开(公告)号：US20170155045A1
公开(公告)日：2017-06-01
申请号：US15365445
申请日：2016-11-30
申请人： Marius Orlowski , Gargi Ghosh , Anshuman Verma
发明人： Marius Orlowski , Gargi Ghosh , Anshuman Verma
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： H01L45/149 , G11C11/5614 , G11C13/0011 , G11C2013/0078 , H01L27/2472 , H01L45/08 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/145 , H01L45/146
摘要： A memory device having a first array of first electrodes extending along a first direction made from a first material and a second array of second electrodes extending along a second direction made from a second material. An intersection defined by the first array and the second array, wherein each intersection of the first array and the second array defines a two-terminal resistive memory cell, said memory cell formed by a conductive path between said first and second electrodes.

8. 发明授权

US08552501B2 Method of forming an inverted T shaped channel structure for an inverted T channel field effect transistor device 有权
标题翻译：形成用于反向T沟道场效应晶体管器件的反相T形沟道结构的方法
公开(公告)号：US08552501B2
公开(公告)日：2013-10-08
申请号：US13447369
申请日：2012-04-16
申请人： Marius Orlowski , Andreas Wild
发明人： Marius Orlowski , Andreas Wild
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L29/7854 , H01L29/66795 , H01L29/78687
摘要： A method of forming an inverted T shaped channel structure having a vertical channel portion and a horizontal channel portion for an Inverted T channel Field Effect Transistor ITFET device comprises semiconductor substrate, a first layer of a first semiconductor material over the semiconductor substrate and a second layer of a second semiconductor material over the first layer. The first and the second semiconductor materials are selected such that the first semiconductor material has a rate of removal which is less than a rate of removal of the second semiconductor material.
摘要翻译：形成具有用于反向T沟道场效应晶体管ITFET器件的垂直沟道部分和水平沟道部分的反向T形沟道结构的方法包括半导体衬底，半导体衬底上的第一半导体材料的第一层和第二层在第一层上的第二半导体材料。选择第一和第二半导体材料，使得第一半导体材料具有小于除去第二半导体材料的速率的去除速率。

9. 发明授权

US08202798B2 Improvements for reducing electromigration effect in an integrated circuit 有权
标题翻译：降低集成电路中电迁移效应的改进
公开(公告)号：US08202798B2
公开(公告)日：2012-06-19
申请号：US12675242
申请日：2007-09-20
申请人： Greg Braeckelmann , Hisao Kawasaki , Marius Orlowski , Emmanuel Petitprez
发明人： Greg Braeckelmann , Hisao Kawasaki , Marius Orlowski , Emmanuel Petitprez
IPC分类号： H01L21/4763
CPC分类号： H01L21/76838 , H01L21/7682 , H01L21/76831 , H01L23/53223 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit comprising one or more dielectric layers the or each dielectric layer being provided with one or more interconnects wherein the interconnect comprises metallic atoms moving from a first region of the interconnect to a second region of the interconnect when a current flows, characterized in that the interconnect comprises a donor zone in the first region of the interconnect for providing metallic atoms in order to compensate for movement of atoms from the first region and a receptor zone at the second region of the interconnect for receiving metallic atoms in order to compensate for movement of atoms to the second region.
摘要翻译：一种包括一个或多个电介质层的集成电路，其中或每个电介质层设置有一个或多个互连，其中互连包括当电流流动时从互连的第一区域移动到互连的第二区域的金属原子，其特征在于互连件包括在互连的第一区域中的供体区域，用于提供金属原子，以便补偿来自第一区域的原子的移动以及用于接收金属原子的互连的第二区域处的受体区域，以便补偿运动的原子到第二个区域。

10. 发明申请

US20100044762A1 METHOD FOR FORMING A SEMICONDUCTOR DEVICE AND STRUCTURE THEREOF 审中-公开
标题翻译：形成半导体器件及其结构的方法
公开(公告)号：US20100044762A1
公开(公告)日：2010-02-25
申请号：US12605556
申请日：2009-10-26
申请人： Marius Orlowski
发明人： Marius Orlowski
IPC分类号： H01L29/78 , H01L29/772
CPC分类号： H01L29/78684 , H01L29/66818 , H01L29/785
摘要： A non-planar semiconductor device (10) starts with a silicon fin (42). A source of germanium (e.g. 24, 26, 28, 30, 32) is provided to the fin (42). Some embodiments may use deposition to provide germanium; some embodiments may use ion implantation (30) to provide germanium; other methods may also be used to provide germanium. The fin (42) is then oxidized to form a silicon germanium channel region in the fin (36). In some embodiments, the entire fin (42) is transformed from silicon to silicon germanium. One or more fins (36) may be used to form a non-planar semiconductor device, such as, for example, a FINFET, MIGFET, Tri-gate transistor, or multi-gate transistor.
摘要翻译：非平面半导体器件（10）从硅片（42）开始。将锗源（例如24,26,28,30,32）提供给翅片（42）。一些实施例可以使用沉积来提供锗; 一些实施例可以使用离子注入（30）来提供锗; 也可以使用其它方法来提供锗。然后将翅片（42）氧化以在翅片（36）中形成硅锗通道区域。在一些实施例中，整个鳍（42）从硅转变为硅锗。可以使用一个或多个翅片（36）来形成非平面半导体器件，例如FINFET，MIGFET，三栅极晶体管或多栅极晶体管。

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