专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20060043422A1 Transistor structure with stress modification and capacitive reduction feature in a width direction and method thereof 有权
标题翻译：具有应力改变和宽度方向的电容减小特性的晶体管结构及其方法
公开(公告)号：US20060043422A1
公开(公告)日：2006-03-02
申请号：US10925084
申请日：2004-08-24
申请人： Jian Chen , Michael Mendicino , Vance Adams , Choh-Fei Yeap , Venkat Kolagunta
发明人： Jian Chen , Michael Mendicino , Vance Adams , Choh-Fei Yeap , Venkat Kolagunta
IPC分类号： H01L29/76 , H01L31/113
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823814 , H01L21/823828
摘要： A transistor comprises a source and drain positioned within an active region. A gate overlies a channel area of the active region, wherein the channel region separates the source and drain. The transistor further comprises at least one stress modifier and capacitive reduction feature extending from the source to the drain and underlying the gate for reducing capacitance associated with the gate, source and drain. The at least one stress modifier and capacitive reduction feature comprises dielectric and includes a shape defined at least partially by the active region.
摘要翻译：晶体管包括位于有源区域内的源极和漏极。栅极覆盖有源区的沟道区，其中沟道区分离源极和漏极。晶体管还包括至少一个应力调节器和电容降低特征，其从源极延伸到漏极并且在栅极下方，用于减小与栅极，源极和漏极相关联的电容。所述至少一个应力调节剂和电容还原特征包括电介质并且包括至少部分地由有源区限定的形状。

2. 发明申请

US20050190421A1 Integrated circuit with multiple spacer insulating region widths 有权
标题翻译：具有多个间隔绝缘区域宽度的集成电路
公开(公告)号：US20050190421A1
公开(公告)日：2005-09-01
申请号：US10790420
申请日：2004-03-01
申请人： Jian Chen , Vance Adams , Choh-Fei Yeap
发明人： Jian Chen , Vance Adams , Choh-Fei Yeap
IPC分类号： G02B26/08 , H01L21/84 , H01L27/12
CPC分类号： H01L21/823864 , H01L21/823814 , H01L21/84 , H01L27/1203
摘要： An integrated circuit with both P-channel transistors (823) and N-channel transistors (821) with different spacer insulating region widths. In one example, the outer sidewall spacer (321) of the N-channel transistors is removed while the P-channel regions (115) are masked such that the spacer insulating region widths of the N-channel transistors is less than the spacer insulating region widths of the P-channel transistors. Also, the drain/source silicide regions (805) of the N-channel transistors are located closer to the gates (117) of those transistors than the P-channel source/drain suicide regions (809) are located to the gates (119) of those transistors. Providing the P-channel transistors with greater spacer insulating widths and greater distances between the source/drain silicide regions and gates may increase the relative compressive stress of the channel region of the P-channel transistors relative the stress of the channel region of the N-channel transistors, thereby increasing the performance of the P-channel transistors.
摘要翻译：具有不同间隔绝缘区宽度的具有P沟道晶体管（823）和N沟道晶体管（821）的集成电路。在一个示例中，除去N沟道晶体管的外侧壁间隔物（321），同时P沟道区域（115）被掩蔽，使得N沟道晶体管的间隔绝缘区域宽度小于间隔绝缘区域 P沟道晶体管的宽度。此外，N沟道晶体管的漏极/源极硅化物区域（805）位于比P沟道源极/漏极硅化物区域（809）位于栅极（119）处更靠近那些晶体管的栅极（117）的晶体管。在源/漏硅化物区域和栅极之间提供具有较大间隔绝缘宽度和较大距离的P沟道晶体管可以增加P沟道晶体管的沟道区相对于N沟道晶体管的沟道区的应力的相对压缩应力，通道晶体管，从而增加P沟道晶体管的性能。

3. 发明申请

US20070202651A1 Semiconductor process integrating source/drain stressors and interlevel dielectric layer stressors 失效
标题翻译：集成源极/漏极应力和半导体介电层应力的半导体工艺
公开(公告)号：US20070202651A1
公开(公告)日：2007-08-30
申请号：US11361171
申请日：2006-02-24
申请人： Da Zhang , Vance Adams , Bich-Yen Nguyen , Paul Grudowski
发明人： Da Zhang , Vance Adams , Bich-Yen Nguyen , Paul Grudowski
IPC分类号： H01L21/336
CPC分类号： H01L29/7846 , H01L29/165 , H01L29/66636 , H01L29/66772 , H01L29/7843 , H01L29/7848 , H01L29/78654
摘要： A semiconductor fabrication process includes forming isolation structures on either side of a transistor region, forming a gate structure overlying the transistor region, removing source/drain regions to form source/drain recesses, removing portions of the isolation structures to form recessed isolation structures, and filling the source/drain recesses with a source/drain stressor such as an epitaxially formed semiconductor. A lower surface of the source/drain recess is preferably deeper than an upper surface of the recessed isolation structure by approximately 10 to 30 nm. Filling the source/drain recesses may precede or follow forming the recessed isolation structures. An ILD stressor is then deposited over the transistor region such that the ILD stressor is adjacent to sidewalls of the source/drain structure thereby coupling the ILD stressor to the source/drain stressor. The ILD stressor is preferably compressive or tensile silicon nitride and the source/drain structure is preferably silicon germanium or silicon carbon.
摘要翻译：半导体制造工艺包括在晶体管区域的任一侧上形成隔离结构，形成覆盖晶体管区域的栅极结构，去除源极/漏极区域以形成源极/漏极凹部，去除隔离结构的部分以形成凹入的隔离结构;以及用诸如外延形成的半导体的源极/漏极应力源填充源/漏极凹部。源极/漏极凹部的下表面优选比凹入的隔离结构的上表面深大约10至30nm。填充源极/漏极凹部可以在形成凹入的隔离结构之前或之后。然后将ILD应激源沉积在晶体管区域上，使得ILD应力源与源极/漏极结构的侧壁相邻，从而将ILD应激源耦合到源极/漏极应力源。 ILD应力器优选为压缩或拉伸氮化硅，并且源极/漏极结构优选为硅锗或硅碳。

4. 发明申请

US20060240650A1 Semiconductor device having a plurality of different layers and method therefor 有权
标题翻译：具有多个不同层的半导体器件及其方法
公开(公告)号：US20060240650A1
公开(公告)日：2006-10-26
申请号：US11111451
申请日：2005-04-21
申请人： Marius Orlowski , Vance Adams
发明人： Marius Orlowski , Vance Adams
IPC分类号： H01L21/425 , H01L29/768 , H01L27/148 , H01L29/74
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823878 , H01L27/1203 , H01L29/165 , H01L29/78 , H01L29/7846 , H01L29/7848
摘要： Mechanical stress control may be achieved using materials having selected elastic moduli. These materials may be selectively formed by implantation, may be provided as a plurality of buried layers interposed between the substrate and the active area, and may be formed by replacing selected portions of one or more buried layers. Any one or more of these methods may be used in combination. Mechanical stress control may be useful in the channel region of a semiconductor device to maximize its performance. In addition, these same techniques and structures may be used for other purposes besides mechanical stress control.
摘要翻译：可以使用具有选定的弹性模量的材料实现机械应力控制。这些材料可以通过注入选择性地形成，可以设置为插入在基板和有源区域之间的多个掩埋层，并且可以通过替换一个或多个掩埋层的选定部分来形成。这些方法中的任何一种或多种可以组合使用。机械应力控制在半导体器件的通道区域中可能是有用的，以使其性能最大化。此外，除了机械应力控制之外，这些相同的技术和结构可以用于其它目的。

5. 发明申请

US20060166492A1 Semiconductor fabrication process employing stress inducing source drain structures with graded impurity concentration 有权
标题翻译：采用具有渐变杂质浓度的应力诱导源极漏极结构的半导体制造工艺
公开(公告)号：US20060166492A1
公开(公告)日：2006-07-27
申请号：US11043577
申请日：2005-01-26
申请人： Marius Orlowski , Vance Adams , Chun-Li Liu , Matthew Stoker
发明人： Marius Orlowski , Vance Adams , Chun-Li Liu , Matthew Stoker
IPC分类号： H01L21/4763
CPC分类号： H01L29/66545 , H01L21/28061 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/665 , H01L29/6656 , H01L29/66636 , H01L29/7833 , H01L29/7834 , H01L29/7848
摘要： A semiconductor fabrication process has recessed stress-inducing source/drain (SISD) structures that are formed using a multiple phase formation process. The SISD structures are semiconductor structures having a lattice constant that differs from a lattice constant of the semiconductor substrate in which the source/drain structures are recessed. The SISD structures preferably include semiconductor compound having a first element (e.g., silicon) and a second element (e.g., germanium or carbon). The SISD structure has a composition gradient wherein the percentage of the second element varies from the upper surface of the source/drain structure to a lower surface of the SISD structure. The SISD structure may include a first layer with a first composition of the semiconductor compound underlying a second layer with a second composition of the semiconductor compound. The second layer may include an impurity and have a higher percentage of the second element that the first layer.
摘要翻译：半导体制造工艺具有使用多相形成工艺形成的凹陷的应力诱导源极/漏极（SISD）结构。 SISD结构是具有不同于源/漏结构凹陷的半导体衬底的晶格常数的晶格常数的半导体结构。 SISD结构优选包括具有第一元素（例如硅）和第二元素（例如锗或碳）的半导体化合物。 SISD结构具有组成梯度，其中第二元素的百分比从源极/漏极结构的上表面到SISD结构的下表面变化。 SISD结构可以包括具有半导体化合物的第一组成的第一层，位于第二层下面，半导体化合物的第二组成。第二层可以包括杂质，并且具有比第一层更高百分比的第二元素。

6. 发明申请

US20060043498A1 Method and apparatus for performance enhancement in an asymmetrical semiconductor device 有权
标题翻译：用于不对称半导体器件中的性能增强的方法和装置
公开(公告)号：US20060043498A1
公开(公告)日：2006-03-02
申请号：US10924650
申请日：2004-08-24
申请人： Marius Orlowski , Vance Adams , Chun-Li Liu , Brian Winstead
发明人： Marius Orlowski , Vance Adams , Chun-Li Liu , Brian Winstead
IPC分类号： H01L29/76
CPC分类号： H01L29/0847 , H01L29/66636 , H01L29/66659 , H01L29/7835
摘要： A method and apparatus is presented that provides performance enhancement in a semiconductor device. In one embodiment, a first current region (64, 76, 23), a channel region and a second current region (75, 33, 66) are adjacent each other. The second current region (75, 33, 66) has a content of a first element of an alloy greater than a content of the first element in the first current region (64, 76, 23), wherein the second current region (75, 33, 66) has a content of the first element greater than a content of the first element in the channel region, the alloy further comprises a second element, the first element has a first valence number, and the second element has a second valence number. Furthermore, the sum of the first valence number and the second valence number is eight.
摘要翻译：提出了一种在半导体器件中提供性能增强的方法和装置。在一个实施例中，第一电流区域（64,76,23），沟道区域和第二电流区域（75,33,66）彼此相邻。第二电流区域（75,33,66）具有比第一电流区域（64,76,23）中的第一元件的含量大的合金的第一元素的含量，其中第二电流区域（75，所述第一元件的含量大于所述沟道区域中的所述第一元素的含量，所述合金还包括第二元素，所述第一元素具有第一价数，并且所述第二元素具有第二价数。此外，第一价数和第二价数之和为八。

7. 发明申请

US20070249127A1 Electronic device including a semiconductor layer and a sidewall spacer and a process of forming the same 审中-公开
标题翻译：包括半导体层和侧壁间隔物的电子器件及其制造方法
公开(公告)号：US20070249127A1
公开(公告)日：2007-10-25
申请号：US11409882
申请日：2006-04-24
申请人： Rode Mora , Vance Adams , Venkat Kolagunta , Michael Turner , Toni Van Gompel
发明人： Rode Mora , Vance Adams , Venkat Kolagunta , Michael Turner , Toni Van Gompel
IPC分类号： H01L21/336 , H01L27/12
CPC分类号： H01L21/84 , H01L27/1203
摘要： An electronic device can include a substrate, an insulating layer, and a semiconductor layer overlying the insulating layer, wherein the insulating layer lies between the substrate and the semiconductor layer. In one aspect, a process of forming the electronic device can include patterning the semiconductor layer to define an opening extending to the insulating layer. The semiconductor layer has a sidewall and a surface, the surface is spaced apart from the insulating layer, and the sidewall extends from the surface towards the insulating layer. The process can also include forming a sidewall spacer adjacent to the sidewall, wherein the sidewall spacer lies within the opening and adjacent to the sidewall, and is spaced apart from the surface. In another aspect, the electronic device can include a field isolation region including the sidewall spacer.
摘要翻译：电子器件可以包括衬底，绝缘层和覆盖绝缘层的半导体层，其中绝缘层位于衬底和半导体层之间。一方面，形成电子器件的工艺可以包括图案化半导体层以限定延伸到绝缘层的开口。半导体层具有侧壁和表面，表面与绝缘层间隔开，并且侧壁从表面向绝缘层延伸。该方法还可以包括形成邻近侧壁的侧壁间隔物，其中侧壁间隔物位于开口内且与侧壁相邻并且与表面间隔开。在另一方面，电子设备可以包括包括侧壁间隔物的场隔离区域。

8. 发明申请

US20070102755A1 Electronic device including a transistor structure having an active region adjacent to a stressor layer and a process for forming the electronic device 有权
标题翻译：电子器件包括具有与应力层相邻的有源区的晶体管结构和用于形成电子器件的工艺
公开(公告)号：US20070102755A1
公开(公告)日：2007-05-10
申请号：US11269303
申请日：2005-11-08
申请人： Vance Adams , Paul Grudowski , Venkat Kolagunta , Brian Winstead
发明人： Vance Adams , Paul Grudowski , Venkat Kolagunta , Brian Winstead
IPC分类号： H01L29/792
CPC分类号： H01L21/84 , H01L21/823412 , H01L21/823481 , H01L21/823807 , H01L21/823878 , H01L27/1203 , H01L29/045 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/7843
摘要： An electronic device can include a transistor structure of a first conductivity type, a field isolation region, and a layer of a first stress type overlying the field isolation region. For example, the transistor structure may be a p-channel transistor structure and the first stress type may be tensile, or the transistor structure may be an n-channel transistor structure and the first stress type may be compressive. The transistor structure can include a channel region that lies within an active region. An edge of the active region includes the interface between the channel region and the field isolation region. From a top view, the layer can include an edge the lies near the edge of the active region. The positional relationship between the edges can affect carrier mobility within the channel region of the transistor structure.
摘要翻译：电子器件可以包括第一导电类型的晶体管结构，场隔离区域和覆盖场隔离区域的第一应力类型的层。例如，晶体管结构可以是p沟道晶体管结构，并且第一应力类型可以是拉伸的，或者晶体管结构可以是n沟道晶体管结构，并且第一应力类型可以是压缩的。晶体管结构可以包括位于有源区内的沟道区。有源区域的边缘包括沟道区域和场隔离区域之间的界面。从顶视图，该层可以包括位于活动区域边缘附近的边缘。边缘之间的位置关系可以影响晶体管结构的沟道区内的载流子迁移率。

9. 发明申请

US20060011988A1 Integrated circuit with multiple spacer insulating region widths 审中-公开
标题翻译：具有多个间隔绝缘区域宽度的集成电路
公开(公告)号：US20060011988A1
公开(公告)日：2006-01-19
申请号：US11231087
申请日：2005-09-20
申请人： Jian Chen , Vance Adams , Choh-Fei Yeap
发明人： Jian Chen , Vance Adams , Choh-Fei Yeap
IPC分类号： H01L29/94
CPC分类号： H01L21/823864 , H01L21/823814 , H01L21/84 , H01L27/1203
摘要： An integrated circuit with both P-channel transistors (823) and N-channel transistors (821) with different spacer insulating region widths. In one example, the outer sidewall spacer (321) of the N-channel transistors is removed while the P-channel regions (115) are masked such that the spacer insulating region widths of the N-channel transistors is less than the spacer insulating region widths of the P-channel transistors. Also, the drain/source silicide regions (805) of the N-channel transistors are located closer to the gates (117) of those transistors than the P-channel source/drain silicide regions (809) are located to the gates (119) of those transistors. Providing the P-channel transistors with greater spacer insulating widths and greater distances between the source/drain silicide regions and gates may increase the relative compressive stress of the channel region of the P-channel transistors relative the stress of the channel region of the N-channel transistors, thereby increasing the performance of the P-channel transistors.
摘要翻译：具有不同间隔绝缘区宽度的具有P沟道晶体管（823）和N沟道晶体管（821）的集成电路。在一个示例中，除去N沟道晶体管的外侧壁间隔物（321），同时P沟道区域（115）被掩蔽，使得N沟道晶体管的间隔绝缘区域宽度小于间隔绝缘区域 P沟道晶体管的宽度。此外，N沟道晶体管的漏极/源极硅化物区域（805）位于比P沟道源极/漏极硅化物区域（809）位于栅极（119）处更靠近那些晶体管的栅极（117）的晶体管。在源/漏硅化物区域和栅极之间提供具有较大间隔绝缘宽度和较大距离的P沟道晶体管可以增加P沟道晶体管的沟道区相对于N沟道晶体管的沟道区的应力的相对压缩应力，通道晶体管，从而增加P沟道晶体管的性能。

10. 发明申请

US20050275017A1 Separately strained N-channel and P-channel transistors 失效
标题翻译：单独应变的N沟道和P沟道晶体管
公开(公告)号：US20050275017A1
公开(公告)日：2005-12-15
申请号：US10856581
申请日：2004-05-28
申请人： Scott Pozder , Salih Celik , Byoung Min , Vance Adams
发明人： Scott Pozder , Salih Celik , Byoung Min , Vance Adams
IPC分类号： H01L21/30 , H01L21/44 , H01L21/4763 , H01L21/58 , H01L21/822 , H01L27/01 , H01L27/06 , H01L27/12 , H01L29/40
CPC分类号： H01L27/0688 , H01L21/8221 , H01L24/29 , H01L24/83 , H01L27/1203 , H01L29/7842 , H01L2224/83191 , H01L2224/8385 , H01L2924/01005 , H01L2924/01015 , H01L2924/01032 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/04941 , H01L2924/07802 , H01L2924/14 , H01L2924/19043
摘要： An integrated circuit with a first plurality of transistors formed on a first wafer and second plurality of transistors formed on a second wafer. At least a substantial majority of the transistor of the first transistor are of a first conductivity type and at least a substantial majority of the transistors of the second plurality are of a second conductivity type. After wafers are bonded together, a portion of the second wafer is removed wherein the strain of the channels of the second plurality of transistors is more compressive than the strain of the channels of the first plurality of transistors.
摘要翻译：一种集成电路，其具有形成在第一晶片上的第一多个晶体管和形成在第二晶片上的第二多个晶体管。第一晶体管的至少绝大部分晶体管是第一导电类型，并且第二多晶体管的至少绝大部分晶体管是第二导电类型。在将晶片接合在一起之后，去除第二晶片的一部分，其中第二多个晶体管的通道的应变比第一多个晶体管的通道的应变更为压缩。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式