专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5463335A Power up detection circuits 失效
标题翻译：上电检测电路
公开(公告)号：US5463335A
公开(公告)日：1995-10-31
申请号：US969594
申请日：1992-10-30
申请人： Sridhar Divakaruni , Jeffrey H. Dreibelbis , Wayne F. Ellis , Anatol Furman , Howard L. Kalter
发明人： Sridhar Divakaruni , Jeffrey H. Dreibelbis , Wayne F. Ellis , Anatol Furman , Howard L. Kalter
IPC分类号： H01L27/00 , H03K17/22
CPC分类号： H03K17/223
摘要： A power up detection circuit is provided which includes a power supply terminal, an output terminal, an impedance device coupling the output terminal to the power supply terminal and a latch including a first inverter having a first device connected between the output terminal and a point of reference potential and a second device connected between the output terminal and the power supply terminal, the devices are designed so that subthreshold current passing through the first device is greater than the effective subthreshold current passing through the impedance device and the second device, and a second inverter including third and fourth devices which are designed so that a smaller subthreshold current passes through the third device than the subthreshold current passing through the fourth device. The power up circuit may further include a capacitor connected between the power supply terminal and gate electrodes of the first and second devices.
摘要翻译：提供了一种上电检测电路，其包括电源端子，输出端子，将输出端子耦合到电源端子的阻抗装置和包括第一反相器的锁存器，第一反相器具有连接在输出端子与点参考电位和连接在输出端子和电源端子之间的第二器件，器件被设计成使得通过第一器件的亚阈值电流大于通过阻抗器件和第二器件的有效亚阈值电流，并且第二器件逆变器包括第三和第四器件，其被设计为使得比通过第四器件的亚阈值电流更小的亚阈值电流通过第三器件。上电电路还可以包括连接在第一和第二器件的电源端子和栅电极之间的电容器。

2. 发明授权

US06426904B2 Structures for wafer level test and burn-in 失效
标题翻译：晶圆级测试和老化的结构
公开(公告)号：US06426904B2
公开(公告)日：2002-07-30
申请号：US09803500
申请日：2001-03-09
申请人： John E. Barth , Claude L. Bertin , Jeffrey H. Dreibelbis , Wayne F. Ellis , Wayne J. Howell , Erik L. Hedberg , Howard L. Kalter , William R. Tonti , Donald L. Wheater
发明人： John E. Barth , Claude L. Bertin , Jeffrey H. Dreibelbis , Wayne F. Ellis , Wayne J. Howell , Erik L. Hedberg , Howard L. Kalter , William R. Tonti , Donald L. Wheater
IPC分类号： G11C2900
CPC分类号： G01R31/2855 , G01R31/2806 , G01R31/2831 , G01R31/31905 , H01L2224/05624 , H01L2224/13 , H01L2224/45144 , H01L2224/45147 , H01L2924/00014
摘要： Wafer test and burn-in is accomplished with state machine or programmable test engines located on the wafer being tested. Each test engine requires less than 10 connections and each test engine can be connected to a plurality of chips, such as a row or a column of chips on the wafer. Thus, the number of pads of the wafer that must be connected for test is substantially reduced while a large degree of parallel testing is still provided. The test engines also permit on-wafer allocation of redundancy in parallel so that failing chips can be repaired after burn-in is complete. In addition, the programmable test engines can have their code altered so test programs can be modified to account for new information after the wafer has been fabricated. The test engines are used during burn-in to provide high frequency write signals to DRAM arrays that provide a higher effective voltage to the arrays, lowering the time required for burn-in. Connections to the wafer and between test engines and chips are provided along a membrane attached to the wafer. Membrane connectors can be formed or opened after the membrane is connected to the wafer so shorted chips can be disconnected. Preferably the membrane remains on the wafer after test, burn-in and dicing to provide a chip scale package. Thus, the very high cost of TCE matched materials, such as glass ceramic contactors, for wafer burn-in is avoided while providing benefit beyond test and burn-in for packaging.
摘要翻译：晶圆测试和老化是通过位于被测晶片上的状态机或可编程测试引擎完成的。每个测试引擎需要少于10个连接，并且每个测试引擎可以连接到多个芯片，例如晶片上的行或一列芯片。因此，仍然提供必须连接用于测试的晶片的焊盘数量，同时还提供大量的并行测试。测试引擎还允许并行的片上分配冗余，以便在老化完成后可以修复故障的芯片。此外，可编程测试引擎可以对其代码进行更改，因此可以修改测试程序以在晶圆制造之后考虑新的信息。在老化期间使用测试引擎向DRAM阵列提供高频写入信号，为阵列提供更高的有效电压，从而降低了老化所需的时间。沿着连接到晶片的膜提供与晶片和测试引擎与芯片之间的连接。膜连接器可以在膜连接到晶片之后形成或打开，因此短路芯片可以断开。优选地，膜在测试之后保留在晶片上，老化和切割以提供芯片级封装。因此，避免了TCE匹配材料（例如玻璃陶瓷接触器）用于晶片老化的非常高的成本，同时提供超出测试和包装封装的优点。

3. 发明授权

US06233184B1 Structures for wafer level test and burn-in 失效
标题翻译：晶圆级测试和老化的结构
公开(公告)号：US06233184B1
公开(公告)日：2001-05-15
申请号：US09191954
申请日：1998-11-13
申请人： John E. Barth , Claude L. Bertin , Jeffrey H. Dreibelbis , Wayne F. Ellis , Wayne J. Howell , Erik L. Hedberg , Howard L. Kalter , William R. Tonti , Donald L. Wheater
发明人： John E. Barth , Claude L. Bertin , Jeffrey H. Dreibelbis , Wayne F. Ellis , Wayne J. Howell , Erik L. Hedberg , Howard L. Kalter , William R. Tonti , Donald L. Wheater
IPC分类号： G11C2900
CPC分类号： G01R31/2855 , G01R31/2806 , G01R31/2831 , G01R31/31905 , H01L2224/05624 , H01L2224/13 , H01L2224/45144 , H01L2224/45147 , H01L2924/00014
摘要： Wafer test and burn-in is accomplished with state machine or programmable test engines located on the wafer being tested. Each test engine requires less than 10 connections and each test engine can be connected to a plurality of chips, such as a row or a column of chips on the wafer. Thus, the number of pads of the wafer that must be connected for test is substantially reduced while a large degree of parallel testing is still provided. The test engines also permit on-wafer allocation of redundancy in parallel so that failing chips can be repaired after burn-in is complete. In addition, the programmable test engines can have their code altered so test programs can be modified to account for new information after the wafer has been fabricated. The test engines are used during burn-in to provide high frequency write signals to DRAM arrays that provide a higher effective voltage to the arrays, lowering the time required for burn-in. Connections to the wafer and between test engines and chips are provided along a membrane attached to the wafer. Membrane connectors can be formed or opened after the membrane is connected to the wafer so shorted chips can be disconnected. Preferably the membrane remains on the wafer after test, burn-in and dicing to provide a chip scale package. Thus, the very high cost of TCE matched materials, such as glass ceramic contactors, for wafer burn-in is avoided while providing benefit beyond test and burn-in for packaging.
摘要翻译：晶圆测试和老化是通过位于被测晶片上的状态机或可编程测试引擎完成的。每个测试引擎需要少于10个连接，并且每个测试引擎可以连接到多个芯片，例如晶片上的行或一列芯片。因此，仍然提供必须连接用于测试的晶片的焊盘数量，同时还提供大量的并行测试。测试引擎还允许并行的片上分配冗余，以便在老化完成后可以修复故障的芯片。此外，可编程测试引擎可以对其代码进行更改，因此可以修改测试程序以在晶圆制造之后考虑新的信息。在老化期间使用测试引擎向DRAM阵列提供高频写入信号，为阵列提供更高的有效电压，从而降低老化所需的时间。沿着连接到晶片的膜提供与晶片和测试引擎与芯片之间的连接。膜连接器可以在膜连接到晶片之后形成或打开，因此短路芯片可以断开。优选地，膜在测试之后保留在晶片上，老化和切割以提供芯片级封装。因此，避免了TCE匹配材料（例如玻璃陶瓷接触器）用于晶片老化的非常高的成本，同时提供超出测试和包装封装的优点。

4. 发明授权

US6044024A Interactive method for self-adjusted access on embedded DRAM memory macros 失效
标题翻译：嵌入式DRAM内存宏自动调整访问的交互方式
公开(公告)号：US6044024A
公开(公告)日：2000-03-28
申请号：US7433
申请日：1998-01-14
申请人： John E. Barth , Jeffrey H. Dreibelbis , Howard L. Kalter
发明人： John E. Barth , Jeffrey H. Dreibelbis , Howard L. Kalter
IPC分类号： G11C11/417 , G06F12/00 , G11C7/10 , G11C11/401 , G11C11/407 , H01L21/822 , H01L27/04 , G11C16/04 , G11C7/02
CPC分类号： G11C7/10
摘要： An embedded memory macro device includes a memory system and a logic circuit constructed on a common semiconductor substrate. The memory system and logic circuit communicate through a handshake procedure via a system data interlock signal. During read cycles the memory system uses the system data interlock signal to tell the logic circuit when data at memory system data outputs is valid. In the preferred embodiment, during write cycles the memory system uses the system data interlock signal to tell the logic circuit when data has been successfully written. The logic circuit needs to wait only until the system data interlock signal permits it to proceed. It then signals the memory system to reset the system data interlock signal and can immediately initiate a new read or write cycle.
摘要翻译：嵌入式存储器宏器件包括存储器系统和构造在公共半导体衬底上的逻辑电路。存储器系统和逻辑电路经由系统数据互锁信号通过握手程序进行通信。在读周期中，当存储器系统数据输出的数据有效时，存储器系统使用系统数据互锁信号来告知逻辑电路。在优选实施例中，在写入周期期间，当数据被成功写入时，存储器系统使用系统数据互锁信号来告诉逻辑电路。逻辑电路需要等到系统数据互锁信号允许它继续进行。然后，它将信号通知存储系统以复位系统数据互锁信号，并可以立即启动新的读或写周期。

5. 发明授权

US5563086A Integrated memory cube, structure and fabrication 失效
标题翻译：集成存储立方体，结构和制造
公开(公告)号：US5563086A
公开(公告)日：1996-10-08
申请号：US406284
申请日：1995-03-17
申请人： Claude L. Bertin , Wayne J. Howell , Erik L. Hedberg , Howard L. Kalter , Gordon A. Kelley, Jr.
发明人： Claude L. Bertin , Wayne J. Howell , Erik L. Hedberg , Howard L. Kalter , Gordon A. Kelley, Jr.
IPC分类号： G11C5/00 , H01L25/065 , H01L21/70
CPC分类号： H01L25/0657 , G11C5/06 , H01L2224/48091 , H01L2225/0651 , H01L2225/06551 , H01L2225/06555 , H01L2225/06572 , H01L2225/06596 , H01L2924/10253
摘要： An integrated memory cube structure and method of fabrication wherein stacked semiconductor memory chips are integrated by a controlling logic chip such that a more powerful memory architecture is defined with the functional appearance of a single, higher level memory chip. A memory/logic cube is formed having N memory chips and at least one logic chip, with each memory chip of the cube having M memory devices. The controlling logic chip coordinates external communication with the N memory chips such that a single memory chip architecture with N.times.M memory devices appears at the cube's I/O pins. A corresponding fabrication technique includes an approach for facilitating metallization patterning on the side surface of the memory subunit.
摘要翻译：一种集成的存储立方体结构和制造方法，其中堆叠的半导体存储器芯片由控制逻辑芯片集成，使得更强大的存储器架构被定义为单个更高级存储器芯片的功能外观。形成具有N个存储器芯片和至少一个逻辑芯片的存储器/逻辑立方体，其中立方体的每个存储器芯片具有M个存储器件。控制逻辑芯片协调与N个存储器芯片的外部通信，使得具有NxM存储器件的单个存储器芯片架构出现在立方体的I / O引脚处。相应的制造技术包括用于在存储器子单元的侧表面上促进金属化图案化的方法。

6. 发明授权

US4603341A Stacked double dense read only memory 失效
标题翻译：堆叠双密度只读存储器
公开(公告)号：US4603341A
公开(公告)日：1986-07-29
申请号：US530452
申请日：1983-09-08
申请人： Claude L. Bertin , Howard L. Kalter
发明人： Claude L. Bertin , Howard L. Kalter
IPC分类号： G11C17/08 , H01L21/822 , H01L21/8246 , H01L27/00 , H01L27/06 , H01L27/10 , H01L27/112 , H01L29/78 , G11C17/00
CPC分类号： H01L27/11519 , H01L21/8221 , H01L27/0688 , H01L27/112
摘要： A read only memory array of stacked IGFET devices composed of first and second sub-arrays of field effect transistors. The first sub-array of first field effect transistors is formed in a substrate. Each of the first field effect transistor devices is responsive to a polysilicon gate electrode. The second sub-array of second field effect transistors is formed in a layer of laser annealed polysilicon material which overlies the first sub-array. The gate electrodes of the first field effect transistors act as the gate electrodes of the second field effect transistors.
摘要翻译：由场效应晶体管的第一和第二子阵列组成的堆叠IGFET器件的只读存储器阵列。第一场效应晶体管的第一子阵列形成在衬底中。第一场效应晶体管器件中的每一个都响应于多晶硅栅电极。第二场效应晶体管的第二子阵列形成在覆盖在第一子阵列上的激光退火多晶硅材料层中。第一场效应晶体管的栅电极用作第二场效应晶体管的栅电极。

7. 发明授权

US5972745A Method or forming self-aligned halo-isolated wells 失效
标题翻译：方法或形成自对准的卤素隔离井
公开(公告)号：US5972745A
公开(公告)日：1999-10-26
申请号：US866674
申请日：1997-05-30
申请人： Howard L. Kalter , Edward J. Nowak , Xiaowei Tian , Minh H. Tong , William R. Tonti
发明人： Howard L. Kalter , Edward J. Nowak , Xiaowei Tian , Minh H. Tong , William R. Tonti
IPC分类号： H01L21/265 , H01L21/761 , H01L21/8238
CPC分类号： H01L21/823892 , H01L21/761 , H01L21/26586
摘要： A method of forming a self-aligned halo-isolated well with a single mask is disclosed. First, a layer of resist is disposed over at least a portion of a substrate's surface. Then, an impurity of a first polarity type is implanted at an angle into the substrate through a gap in the layer of resist, thus forming a well having the impurity of the first polarity, which extends beneath the layer of resist. An impurity of a second polarity type is also implanted, using the same mask as previously used. The second implantation forms a well of the impurity of the second polarity disposed within the well of to impurity of the first polarity.
摘要翻译：公开了一种用单一掩模形成自对准卤素隔离井的方法。首先，将抗蚀剂层设置在衬底表面的至少一部分上。然后，第一极性类型的杂质通过抗蚀剂层中的间隙以一定角度注入到衬底中，从而形成具有在抗蚀剂层下方延伸的具有第一极性杂质的阱。使用与以前使用的相同的掩模也植入第二极性类型的杂质。第二次注入形成设置在第一极性杂质的阱内的第二极性杂质的阱。

8. 发明授权

US5814885A Very dense integrated circuit package 失效
标题翻译：非常密集的集成电路封装
公开(公告)号：US5814885A
公开(公告)日：1998-09-29
申请号：US848037
申请日：1997-04-28
申请人： H. Bernhard Pogge , Johann Greschner , Howard L. Kalter
发明人： H. Bernhard Pogge , Johann Greschner , Howard L. Kalter
IPC分类号： H01L23/13 , H01L29/06 , H01L29/04 , H01L23/06
CPC分类号： H01L24/95 , H01L23/13 , H01L29/0657 , H01L2224/83141 , H01L2224/95136 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01027 , H01L2924/01032 , H01L2924/01033 , H01L2924/01039 , H01L2924/10158 , H01L2924/10253 , H01L2924/10329 , H01L2924/12042 , H01L2924/14 , H01L2924/3025
摘要： An integrated circuit package including a carrier having a surface topography of projections or recesses for supporting individual semiconductor circuit chips having a conversely matching bottom surface topography to permit self-aligned positioning of the chip on the carrier.
摘要翻译：一种集成电路封装，包括具有用于支撑具有相反匹配的底表面形貌的各个半导体电路芯片的突起或凹槽的表面形貌的载体，以允许芯片在载体上的自对准定位。

9. 发明授权

US5571754A Method of fabrication of endcap chip with conductive, monolithic L-connect for multichip stack 失效
标题翻译：用于多芯片堆叠的具有导电的单片L形连接器的端盖芯片的制造方法
公开(公告)号：US5571754A
公开(公告)日：1996-11-05
申请号：US555738
申请日：1995-11-09
申请人： Claude L. Bertin , Wayne J. Howell , Howard L. Kalter
发明人： Claude L. Bertin , Wayne J. Howell , Howard L. Kalter
IPC分类号： H01L23/538 , H01L25/065 , H01L25/07 , H01L25/18 , H01L21/60
CPC分类号： H01L25/0657 , H01L25/18 , H01L2224/24145 , H01L2224/32145 , H01L2224/48145 , H01L2225/06506 , H01L2225/06524 , H01L2225/06541 , H01L2225/06551 , H01L2225/06586 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/19041
摘要： An endcap chip is provided for a multichip stack comprising multiple integrated circuit chips laminated together. The endcap chip has a substrate with an upper surface and a edge surface, which extends in a plane orthogonal to the upper surface. At least one conductive, monolithic L-connect is disposed over the substrate such that a first leg extends at least partially over the upper surface of the substrate and a second leg extends at least partially over the edge surface of the substrate. When the endcap chip is located at the end of the multichip stack, the at least one conductive, monolithic L-connect electrically connects metal on an end face of the stack to metal on a side face of the stack. A fabrication process is set forth for producing the endcap chip with lithographically defined dimensions.
摘要翻译：提供了一种用于多芯片堆叠的端盖芯片，其包括层叠在一起的多个集成电路芯片。端盖芯片具有上表面和边缘表面的基板，该基板在与上表面正交的平面中延伸。至少一个导电的单片L形连接器设置在衬底上，使得第一腿部至少部分地延伸到衬底的上表面上，并且第二腿部至少部分地延伸到衬底的边缘表面上。当端盖芯片位于多芯片堆叠的端部时，至少一个导电的单片L形连接器将堆叠的端面上的金属与堆叠的侧面上的金属电连接。阐述了用于制造具有光刻尺寸的端盖芯片的制造工艺。

10. 发明授权

US5561622A Integrated memory cube structure 失效
标题翻译：集成内存立方体结构
公开(公告)号：US5561622A
公开(公告)日：1996-10-01
申请号：US120993
申请日：1993-09-13
申请人： Claude L. Bertin , Wayne J. Howell , Erik L. Hedberg , Howard L. Kalter , Gordon A. Kelley, Jr.
发明人： Claude L. Bertin , Wayne J. Howell , Erik L. Hedberg , Howard L. Kalter , Gordon A. Kelley, Jr.
IPC分类号： G11C5/00 , H01L25/065 , G11C5/06 , H01L23/02
CPC分类号： H01L25/0657 , G11C5/06 , H01L2224/48091 , H01L2225/0651 , H01L2225/06551 , H01L2225/06555 , H01L2225/06572 , H01L2225/06596 , H01L2924/10253
摘要： An integrated memory cube structure and method of fabrication wherein stacked semiconductor memory chips are integrated by a controlling logic chip such that a more powerful memory architecture is defined with the functional appearance of a single, higher level memory chip. A memory/logic cube is formed having N memory chips and at least one logic chip, with each memory chip of the cube having M memory devices. The controlling logic chip coordinates external communication with the N memory chips such that a single memory chip architecture with N.times.M memory devices appears at the cube's I/O pins. A corresponding fabrication technique includes an approach for facilitating metallization patterning on the side surface of the memory subunit.
摘要翻译：一种集成的存储立方体结构和制造方法，其中堆叠的半导体存储器芯片由控制逻辑芯片集成，使得更强大的存储器架构被定义为单个更高级存储器芯片的功能外观。形成具有N个存储器芯片和至少一个逻辑芯片的存储器/逻辑立方体，其中立方体的每个存储器芯片具有M个存储器件。控制逻辑芯片协调与N个存储器芯片的外部通信，使得具有NxM存储器件的单个存储器芯片架构出现在立方体的I / O引脚处。相应的制造技术包括用于在存储器子单元的侧表面上促进金属化图案化的方法。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式