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1. 发明授权

US06451697B1 Method for abrasive-free metal CMP in passivation domain 失效
标题翻译：钝化区无磨料金属CMP的方法
公开(公告)号：US06451697B1
公开(公告)日：2002-09-17
申请号：US09544281
申请日：2000-04-06
申请人： Lizhong Sun , Shijian Li , Fritz Redeker
发明人： Lizhong Sun , Shijian Li , Fritz Redeker
IPC分类号： H01L21302
CPC分类号： H01L21/3212 , C09G1/00
摘要： Metal CMP with reduced dishing and overpolish insensitivity is achieved with an abrasive-free polishing composition having a pH and oxidation-reduction potential in the domain of passivation of the metal and, therefore, a low static etching rate at high temperatures, e.g., higher than 50° C. Embodiments of the present invention comprise CMP of Cu film without any abrasive using a composition comprising one or more chelating agents, one or more oxidizers, one or more corrosion inhibitors, one or more agents to achieve a pH of about 3 to about 10 and deionized water.
摘要翻译：具有减少的凹陷和过度不敏感性的金属CMP通过在金属钝化领域具有pH和氧化还原电位的无磨料抛光组合物实现，因此在高温下具有低的静态蚀刻速率，例如高于本发明的实施方案包括使用包含一种或多种螯合剂，一种或多种氧化剂，一种或多种腐蚀抑制剂，一种或多种pH达3〜约10和去离子水。

2. 发明授权

US06299741B1 Advanced electrolytic polish (AEP) assisted metal wafer planarization method and apparatus 失效
标题翻译：先进的电解抛光（AEP）辅助金属晶圆平面化方法和装置
公开(公告)号：US06299741B1
公开(公告)日：2001-10-09
申请号：US09450858
申请日：1999-11-29
申请人： Lizhong Sun , Stan Tsai , Fritz Redeker
发明人： Lizhong Sun , Stan Tsai , Fritz Redeker
IPC分类号： C25D1700
CPC分类号： H01L21/3212 , H01L21/32115
摘要： In advanced electrolytic polish (AEP) method, a metal wafer (10) acts as an anodic electrodes and another metal plate (65) is used as a cathodic electrode. A voltage differential is applied to the anode and cathode under a predetermined anodic dissolution current density. This causes a reaction that provides a planarized surface on the metal wafers. Additives are included in the electrolyte solution (55) which adsorb onto the wafer surface urging a higher removal rate at higher spots and a lower removal rate at lower spots. Also, in another embodiment of the present invention is a pulsed-electrolytic process (260) in which positive and negative potentials are applied to the anodic and cathodic electrodes alternately, further encouraging surface planarization.
摘要翻译：在高级电解抛光（AEP）方法中，金属晶片（10）用作阳极电极，另一金属板（65）用作阴极电极。在预定的阳极溶解电流密度下，对阳极和阴极施加电压差。这导致在金属晶片上提供平坦化表面的反应。添加剂被包括在吸附在晶片表面上的电解质溶液（55）中，促使较高点处的更高的去除率和较低的去除率降低。此外，在本发明的另一实施例中，脉冲电解方法（260）其中正电位和负电位交替地施加到阳极和阴极电极，进一步促进了表面平坦化。

3. 发明申请

US20120205807A1 DEVICE WITH POST-CONTACT BACK END OF LINE THROUGH-HOLE VIA INTEGRATION 有权
标题翻译：具有通过一体化的线接触后端的装置
公开(公告)号：US20120205807A1
公开(公告)日：2012-08-16
申请号：US13455453
申请日：2012-04-25
申请人： John Boyd , Fritz Redeker , Yezdi Dordi , Hyungsuk Alexander Yoon , Shijian Li
发明人： John Boyd , Fritz Redeker , Yezdi Dordi , Hyungsuk Alexander Yoon , Shijian Li
IPC分类号： H01L23/48
CPC分类号： H01L23/48 , H01L21/4763 , H01L21/76898 , H01L2924/14
摘要： Presented are device structures and methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. Another aspect of the present invention includes three-dimensional integrated circuits fabricated according to methods of the present invention.
摘要翻译：提出了三维集成电路的器件结构和方法，该三维集成电路包括用于三维集成电路的集成的线通孔的后接后端。本发明的另一方面包括根据本发明的方法制造的三维集成电路。

4. 发明申请

US20080315418A1 Methods of post-contact back end of line through-hole via integration 有权
标题翻译：通过一体化的后通孔后端的方法
公开(公告)号：US20080315418A1
公开(公告)日：2008-12-25
申请号：US11820811
申请日：2007-06-20
申请人： John Boyd , Fritz Redeker , Yezdi Dordi , Hyungsuk Alexander Yoon , Shijian Li
发明人： John Boyd , Fritz Redeker , Yezdi Dordi , Hyungsuk Alexander Yoon , Shijian Li
IPC分类号： H01L21/4763 , H01L23/48
CPC分类号： H01L23/48 , H01L21/4763 , H01L21/76898 , H01L2924/14
摘要： Presented are methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. In one embodiment, the method comprises forming metal plug contacts through a hard mask and a premetal dielectric to transistors in the semiconductor. The method also includes etching a hole for a through-hole via through the hard mask to the semiconductor using a patterned photoresist process, removing the patterned photoresist and using a hard mask process to etch the hole to an amount into the semiconductor. The method further includes depositing a dielectric liner to isolate the hole from the semiconductor, depositing a gapfill metal to fill the hole, and planarizing the surface of the substrate to the hard mask. Another aspect of the present invention includes three-dimensional integrated circuits fabricated according to methods of the present invention.
摘要翻译：提出了制造三维集成电路的方法，其包括用于三维集成电路的集成的线路通孔的后接触后端。在一个实施例中，该方法包括通过硬掩模和前金属电介质形成金属插头触点到半导体中的晶体管。该方法还包括使用图案化的光致抗蚀剂工艺将用于通孔的通孔穿过硬掩模蚀刻到半导体，去除图案化的光致抗蚀剂并使用硬掩模工艺将孔蚀刻到半导体中的量。所述方法还包括沉积介电衬垫以将所述孔与所述半导体隔离，沉积间隙填充金属以填充所述孔，以及将所述衬底的表面平面化至所述硬掩模。本发明的另一方面包括根据本发明的方法制造的三维集成电路。

5. 发明申请

US20080152464A1 METHODS, APPARATUSES, AND SYSTEMS FOR FABRICATING THREE DIMENSIONAL INTEGRATED CIRCUITS 有权
标题翻译：制造三维集成电路的方法，装置和系统
公开(公告)号：US20080152464A1
公开(公告)日：2008-06-26
申请号：US11958025
申请日：2007-12-17
申请人： Shijian LI , Fritz Redeker , Yezdi Dordi
发明人： Shijian LI , Fritz Redeker , Yezdi Dordi
IPC分类号： H01L21/677 , B25B5/00
CPC分类号： H01L21/70 , C23C16/045 , C23C16/4586 , H01L21/67017 , H01L21/677 , H01L21/6838 , H01L21/68714 , H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/12044 , Y10T24/44 , H01L2924/00012 , H01L2924/00
摘要： The present invention pertains to methods, apparatuses, and systems for fabricating three-dimensional integrated circuits. One embodiment of the method comprises providing a wafer or other substrate having a plurality of through holes. In addition, the method includes supporting the wafer or other substrate with a wafer or other substrate holder mounted in a process chamber. The method further includes generating a pressure differential between the front side of the wafer or other substrate and the back side of the wafer or other substrate while the wafer or other substrate is supported on the wafer or other substrate holder so that the pressure differential causes fluid flow through the through holes. Also, the method includes establishing process conditions in the process chamber for at least one process to fabricate integrated circuits. Embodiments of a system and embodiments of an apparatus according to the present invention are also presented.
摘要翻译：本发明涉及用于制造三维集成电路的方法，装置和系统。该方法的一个实施例包括提供具有多个通孔的晶片或其它基板。此外，该方法包括用安装在处理室中的晶片或其它衬底保持器来支撑晶片或其它衬底。该方法还包括在晶片或其它基板被支撑在晶片或其它基板保持器上的同时，在晶片或其它基板的前侧与晶片或其它基板的背面之间产生压差，使得压力差导致流体流过通孔。此外，该方法包括在处理室中建立用于制造集成电路的至少一个工艺的工艺条件。还提供了根据本发明的系统和实施例的装置的实施例。

6. 发明申请

US20110143553A1 INTEGRATED TOOL SETS AND PROCESS TO KEEP SUBSTRATE SURFACE WET DURING PLATING AND CLEAN IN FABRICATION OF ADVANCED NANO-ELECTRONIC DEVICES 审中-公开
标题翻译：综合工具集和工艺在高级纳米电子设备制造过程中保护基底表面湿润清洗和清洁
公开(公告)号：US20110143553A1
公开(公告)日：2011-06-16
申请号：US12965765
申请日：2010-12-10
申请人： Yaxin Wang , Shijian Li , Fritz Redeker , John Parks , Artur Kolics , Hyungsuk Alexander Yoon , Tarek Suwwan de Felipe , Mikhail Korolik
发明人： Yaxin Wang , Shijian Li , Fritz Redeker , John Parks , Artur Kolics , Hyungsuk Alexander Yoon , Tarek Suwwan de Felipe , Mikhail Korolik
IPC分类号： H01L21/469 , B05C3/02 , B05C11/00 , B05C11/02
CPC分类号： H01L21/288 , C23C18/1642 , C23C18/1689 , C23C18/1872 , H01L21/76849
摘要： Methods and systems for handling a substrate through processes including an integrated electroless deposition process includes processing a surface of the substrate in an electroless deposition module to deposit a layer over conductive features of the substrate using a deposition fluid. The surface of the substrate is then rinsed in the electroless deposition module with a rinsing fluid. The rinsing is controlled to prevent de-wetting of the surface so that a transfer film defined from the rinsing fluid remains coated over the surface of the substrate. The substrate is removed from the electroless deposition module while maintaining the transfer film over the surface of the substrate. The transfer film over the surface of the substrate prevents drying of the surface of the substrate so that the removing is wet. The substrate, once removed from the electroless deposition module, is moved into a post-deposition module while maintaining the transfer film over the surface of the substrate.
摘要翻译：用于通过包括集成无电沉积工艺的工艺处理衬底的方法和系统包括在无电沉积模块中处理衬底的表面以使用沉积流体在衬底的导电特征上沉积层。然后用清洗液在无电沉积模块中冲洗基材的表面。控制冲洗以防止表面的脱湿，使得从冲洗流体限定的转印膜保持涂覆在基材的表面上。将基底从无电沉积模块移除，同时将转印膜保持在衬底的表面上。衬底表面上的转印膜防止了衬底表面的干燥，使得去除被弄湿。一旦从无电镀沉积模块中取出的衬底被移动到后沉积模块中，同时将转印膜保持在衬底的表面上。

7. 发明授权

US07749893B2 Methods and systems for low interfacial oxide contact between barrier and copper metallization 有权
标题翻译：屏障和铜金属化之间的低界面氧化物接触的方法和系统
公开(公告)号：US07749893B2
公开(公告)日：2010-07-06
申请号：US11641361
申请日：2006-12-18
申请人： Fritz Redeker , John Boyd , Yezdi Dordi , Hyungsuk Alexander Yoon , Shijian Li
发明人： Fritz Redeker , John Boyd , Yezdi Dordi , Hyungsuk Alexander Yoon , Shijian Li
IPC分类号： H01L21/4763
CPC分类号： C25D7/123 , C23C18/1653 , C23C28/023 , C23C28/322 , C23C28/34 , C23C28/341 , H01L21/28562 , H01L21/76843 , H01L21/76849 , H01L21/76856 , H01L21/76862 , H01L21/76873 , H01L21/76874 , H01L23/53238 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to methods and systems for the metallization of semiconductor devices. One aspect of the present invention is a method of depositing a copper layer onto a barrier layer so as to produce a substantially oxygen free interface therebetween. In one embodiment, the method includes providing a substantially oxide free surface of the barrier layer. The method also includes depositing an amount of atomic layer deposition (ALD) copper on the oxide free surface of the barrier layer effective to prevent oxidation of the barrier layer. The method further includes depositing a gapfill copper layer over the ALD copper. Another aspect of the present invention is a system for depositing a copper layer onto barrier layer so as to produce a substantially oxygen-free interface therebetween. In one embodiment, the integrated system includes at least one barrier deposition module. The system also includes an ALD copper deposition module configured to deposit copper by atomic layer deposition. The system further includes a copper gapfill module and at least one transfer module coupled to the at least one barrier deposition module and to the ALD copper deposition module. The transfer module is configured so that the substrate can be transferred between the modules substantially without exposure to an oxide-forming environment.
摘要翻译：本发明涉及用于半导体器件金属化的方法和系统。本发明的一个方面是将铜层沉积在阻挡层上以在其间产生基本上无氧的界面的方法。在一个实施例中，该方法包括提供阻挡层的基本上无氧化物的表面。该方法还包括在阻挡层的无氧化物表面上沉积一定量的原子层沉积（ALD）铜，以有效地防止阻挡层的氧化。该方法还包括在ALD铜上沉积间隙填充铜层。本发明的另一方面是一种用于在阻挡层上沉积铜层以在其间产生基本上无氧的界面的系统。在一个实施例中，集成系统包括至少一个阻挡层沉积模块。该系统还包括配置为通过原子层沉积沉积铜的ALD铜沉积模块。该系统还包括铜间隙填充模块和耦合到至少一个阻挡层沉积模块和ALD铜沉积模块的至少一个传输模块。转移模块被配置为使得基板可以在基本上不暴露于氧化物形成环境的基础之间传递。

8. 发明授权

US08323460B2 Methods and systems for three-dimensional integrated circuit through hole via gapfill and overburden removal 有权
标题翻译：用于三维集成电路通孔的方法和系统通过间隙填充和覆盖层去除
公开(公告)号：US08323460B2
公开(公告)日：2012-12-04
申请号：US11820810
申请日：2007-06-20
申请人： John Boyd , Fritz Redeker , Yezdi Dordi , Hyungsuk Alexander Yoon , Shijian Li
发明人： John Boyd , Fritz Redeker , Yezdi Dordi , Hyungsuk Alexander Yoon , Shijian Li
IPC分类号： C25D17/00
CPC分类号： C25D3/00 , H01L21/2885 , H01L21/32115 , H01L21/67005 , H01L21/67023 , H01L21/67075 , H01L21/6708 , H01L21/6715 , H01L21/768 , H01L21/7684 , H01L21/76883 , H01L21/76898
摘要： Presented are methods and systems for fabricating three-dimensional integrated circuits having large diameter through-hole vias. One embodiment of the present invention provides a method of processing a wafer having holes for through-hole vias. The method comprises plating a gapfill metal on the wafer. The method also comprises chemically or electrochemically deplating a portion of the overburden metal. The method further comprises using chemical mechanical planarization to planarize the gapfill metal and to remove the remaining overburden metal. Another embodiment of the present invention is an integrated system comprising a process chamber for containing the wafer, a plating component integrated with the process chamber, and a deplating component integrated with the process chamber. The plating component is configured to electrochemically plate a gapfill metal onto the wafer to a least partially fill the holes. The deplating component is configured to chemically or to electrochemically remove a portion of the overburden metal formed by the plating component.
摘要翻译：提出了用于制造具有大直径通孔的三维集成电路的方法和系统。本发明的一个实施例提供一种处理具有用于通孔过孔的孔的晶片的方法。该方法包括在晶片上镀覆间隙填充金属。该方法还包括化学地或电化学地去除一部分覆盖层金属。该方法还包括使用化学机械平面化来平坦化间隙填充金属并除去剩余的覆盖层金属。本发明的另一实施例是一种集成系统，其包括用于容纳晶片的处理室，与处理室一体化的电镀部件，以及与处理室一体化的去掉部件。电镀部件被配置为将间隙填充金属电化学地平板化到晶片上以至少部分地填充孔。脱镀部件被配置为化学地或电化学地去除由电镀部件形成的覆盖层金属的一部分。

9. 发明授权

US08187968B2 Methods of post-contact back end of line through-hole via integration 有权
标题翻译：通过一体化的后通孔后端的方法
公开(公告)号：US08187968B2
公开(公告)日：2012-05-29
申请号：US12613518
申请日：2009-11-05
申请人： John Boyd , Fritz Redeker , Yezdi Dordi , Hyungsuk Alexander Yoon , Shijian Li
发明人： John Boyd , Fritz Redeker , Yezdi Dordi , Hyungsuk Alexander Yoon , Shijian Li
IPC分类号： H01L21/00
CPC分类号： H01L23/48 , H01L21/4763 , H01L21/76898 , H01L2924/14
摘要： Presented are methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. Another aspect of the present invention includes three-dimensional integrated circuits fabricated according to methods of the present invention.
摘要翻译：提出了制造三维集成电路的方法，其包括用于三维集成电路的集成的线路通孔的后接触后端。本发明的另一方面包括根据本发明的方法制造的三维集成电路。

10. 发明授权

US06322427B1 Conditioning fixed abrasive articles 有权
标题翻译：调理固定磨料制品
公开(公告)号：US06322427B1
公开(公告)日：2001-11-27
申请号：US09302530
申请日：1999-04-30
申请人： Shijian Li , Sidney Huey , Ramin Emami , Fritz Redeker , John White
发明人： Shijian Li , Sidney Huey , Ramin Emami , Fritz Redeker , John White
IPC分类号： B24B100
CPC分类号： B24B53/017 , B24B37/042
摘要： The useful lifetime of a fixed abrasive article is extended and wafer-to-wafer uniformity enhanced by preconditioning a fixed abrasive element and/or periodic conditioning after initial wafer polishing. Embodiments include preconditioning by forced removal of an upper binder-rich portion of the fixed abrasive elements to expose abrasive particles having a similar concentration as the bulk concentration at about one half the height of the elements. Embodiments further include periodic conditioning after initial wafer polishing by forced removal of an upper portion of the fixed abrasive elements.
摘要翻译：固定磨料制品的使用寿命延长，并且通过预先固定研磨元件和/或在初始晶片抛光之后进行周期性调节来提高晶片到晶片的均匀性。实施例包括通过强制去除固定研磨元件的上部粘结剂丰富部分来预处理，以使具有与元件高度的大约一半高度的体积浓度相似的浓度的磨料颗粒暴露。实施例还包括通过强制去除固定研磨元件的上部的初始晶片抛光之后的周期性调节。

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