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1. 发明授权

US08323460B2 Methods and systems for three-dimensional integrated circuit through hole via gapfill and overburden removal 有权
标题翻译：用于三维集成电路通孔的方法和系统通过间隙填充和覆盖层去除
公开(公告)号：US08323460B2
公开(公告)日：2012-12-04
申请号：US11820810
申请日：2007-06-20
申请人： John Boyd , Fritz Redeker , Yezdi Dordi , Hyungsuk Alexander Yoon , Shijian Li
发明人： John Boyd , Fritz Redeker , Yezdi Dordi , Hyungsuk Alexander Yoon , Shijian Li
IPC分类号： C25D17/00
CPC分类号： C25D3/00 , H01L21/2885 , H01L21/32115 , H01L21/67005 , H01L21/67023 , H01L21/67075 , H01L21/6708 , H01L21/6715 , H01L21/768 , H01L21/7684 , H01L21/76883 , H01L21/76898
摘要： Presented are methods and systems for fabricating three-dimensional integrated circuits having large diameter through-hole vias. One embodiment of the present invention provides a method of processing a wafer having holes for through-hole vias. The method comprises plating a gapfill metal on the wafer. The method also comprises chemically or electrochemically deplating a portion of the overburden metal. The method further comprises using chemical mechanical planarization to planarize the gapfill metal and to remove the remaining overburden metal. Another embodiment of the present invention is an integrated system comprising a process chamber for containing the wafer, a plating component integrated with the process chamber, and a deplating component integrated with the process chamber. The plating component is configured to electrochemically plate a gapfill metal onto the wafer to a least partially fill the holes. The deplating component is configured to chemically or to electrochemically remove a portion of the overburden metal formed by the plating component.
摘要翻译：提出了用于制造具有大直径通孔的三维集成电路的方法和系统。本发明的一个实施例提供一种处理具有用于通孔过孔的孔的晶片的方法。该方法包括在晶片上镀覆间隙填充金属。该方法还包括化学地或电化学地去除一部分覆盖层金属。该方法还包括使用化学机械平面化来平坦化间隙填充金属并除去剩余的覆盖层金属。本发明的另一实施例是一种集成系统，其包括用于容纳晶片的处理室，与处理室一体化的电镀部件，以及与处理室一体化的去掉部件。电镀部件被配置为将间隙填充金属电化学地平板化到晶片上以至少部分地填充孔。脱镀部件被配置为化学地或电化学地去除由电镀部件形成的覆盖层金属的一部分。

2. 发明授权

US08187968B2 Methods of post-contact back end of line through-hole via integration 有权
标题翻译：通过一体化的后通孔后端的方法
公开(公告)号：US08187968B2
公开(公告)日：2012-05-29
申请号：US12613518
申请日：2009-11-05
申请人： John Boyd , Fritz Redeker , Yezdi Dordi , Hyungsuk Alexander Yoon , Shijian Li
发明人： John Boyd , Fritz Redeker , Yezdi Dordi , Hyungsuk Alexander Yoon , Shijian Li
IPC分类号： H01L21/00
CPC分类号： H01L23/48 , H01L21/4763 , H01L21/76898 , H01L2924/14
摘要： Presented are methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. Another aspect of the present invention includes three-dimensional integrated circuits fabricated according to methods of the present invention.
摘要翻译：提出了制造三维集成电路的方法，其包括用于三维集成电路的集成的线路通孔的后接触后端。本发明的另一方面包括根据本发明的方法制造的三维集成电路。

3. 发明申请

US20120205807A1 DEVICE WITH POST-CONTACT BACK END OF LINE THROUGH-HOLE VIA INTEGRATION 有权
标题翻译：具有通过一体化的线接触后端的装置
公开(公告)号：US20120205807A1
公开(公告)日：2012-08-16
申请号：US13455453
申请日：2012-04-25
申请人： John Boyd , Fritz Redeker , Yezdi Dordi , Hyungsuk Alexander Yoon , Shijian Li
发明人： John Boyd , Fritz Redeker , Yezdi Dordi , Hyungsuk Alexander Yoon , Shijian Li
IPC分类号： H01L23/48
CPC分类号： H01L23/48 , H01L21/4763 , H01L21/76898 , H01L2924/14
摘要： Presented are device structures and methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. Another aspect of the present invention includes three-dimensional integrated circuits fabricated according to methods of the present invention.
摘要翻译：提出了三维集成电路的器件结构和方法，该三维集成电路包括用于三维集成电路的集成的线通孔的后接后端。本发明的另一方面包括根据本发明的方法制造的三维集成电路。

4. 发明申请

US20080315418A1 Methods of post-contact back end of line through-hole via integration 有权
标题翻译：通过一体化的后通孔后端的方法
公开(公告)号：US20080315418A1
公开(公告)日：2008-12-25
申请号：US11820811
申请日：2007-06-20
申请人： John Boyd , Fritz Redeker , Yezdi Dordi , Hyungsuk Alexander Yoon , Shijian Li
发明人： John Boyd , Fritz Redeker , Yezdi Dordi , Hyungsuk Alexander Yoon , Shijian Li
IPC分类号： H01L21/4763 , H01L23/48
CPC分类号： H01L23/48 , H01L21/4763 , H01L21/76898 , H01L2924/14
摘要： Presented are methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. In one embodiment, the method comprises forming metal plug contacts through a hard mask and a premetal dielectric to transistors in the semiconductor. The method also includes etching a hole for a through-hole via through the hard mask to the semiconductor using a patterned photoresist process, removing the patterned photoresist and using a hard mask process to etch the hole to an amount into the semiconductor. The method further includes depositing a dielectric liner to isolate the hole from the semiconductor, depositing a gapfill metal to fill the hole, and planarizing the surface of the substrate to the hard mask. Another aspect of the present invention includes three-dimensional integrated circuits fabricated according to methods of the present invention.
摘要翻译：提出了制造三维集成电路的方法，其包括用于三维集成电路的集成的线路通孔的后接触后端。在一个实施例中，该方法包括通过硬掩模和前金属电介质形成金属插头触点到半导体中的晶体管。该方法还包括使用图案化的光致抗蚀剂工艺将用于通孔的通孔穿过硬掩模蚀刻到半导体，去除图案化的光致抗蚀剂并使用硬掩模工艺将孔蚀刻到半导体中的量。所述方法还包括沉积介电衬垫以将所述孔与所述半导体隔离，沉积间隙填充金属以填充所述孔，以及将所述衬底的表面平面化至所述硬掩模。本发明的另一方面包括根据本发明的方法制造的三维集成电路。

5. 发明授权

US07749893B2 Methods and systems for low interfacial oxide contact between barrier and copper metallization 有权
标题翻译：屏障和铜金属化之间的低界面氧化物接触的方法和系统
公开(公告)号：US07749893B2
公开(公告)日：2010-07-06
申请号：US11641361
申请日：2006-12-18
申请人： Fritz Redeker , John Boyd , Yezdi Dordi , Hyungsuk Alexander Yoon , Shijian Li
发明人： Fritz Redeker , John Boyd , Yezdi Dordi , Hyungsuk Alexander Yoon , Shijian Li
IPC分类号： H01L21/4763
CPC分类号： C25D7/123 , C23C18/1653 , C23C28/023 , C23C28/322 , C23C28/34 , C23C28/341 , H01L21/28562 , H01L21/76843 , H01L21/76849 , H01L21/76856 , H01L21/76862 , H01L21/76873 , H01L21/76874 , H01L23/53238 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to methods and systems for the metallization of semiconductor devices. One aspect of the present invention is a method of depositing a copper layer onto a barrier layer so as to produce a substantially oxygen free interface therebetween. In one embodiment, the method includes providing a substantially oxide free surface of the barrier layer. The method also includes depositing an amount of atomic layer deposition (ALD) copper on the oxide free surface of the barrier layer effective to prevent oxidation of the barrier layer. The method further includes depositing a gapfill copper layer over the ALD copper. Another aspect of the present invention is a system for depositing a copper layer onto barrier layer so as to produce a substantially oxygen-free interface therebetween. In one embodiment, the integrated system includes at least one barrier deposition module. The system also includes an ALD copper deposition module configured to deposit copper by atomic layer deposition. The system further includes a copper gapfill module and at least one transfer module coupled to the at least one barrier deposition module and to the ALD copper deposition module. The transfer module is configured so that the substrate can be transferred between the modules substantially without exposure to an oxide-forming environment.
摘要翻译：本发明涉及用于半导体器件金属化的方法和系统。本发明的一个方面是将铜层沉积在阻挡层上以在其间产生基本上无氧的界面的方法。在一个实施例中，该方法包括提供阻挡层的基本上无氧化物的表面。该方法还包括在阻挡层的无氧化物表面上沉积一定量的原子层沉积（ALD）铜，以有效地防止阻挡层的氧化。该方法还包括在ALD铜上沉积间隙填充铜层。本发明的另一方面是一种用于在阻挡层上沉积铜层以在其间产生基本上无氧的界面的系统。在一个实施例中，集成系统包括至少一个阻挡层沉积模块。该系统还包括配置为通过原子层沉积沉积铜的ALD铜沉积模块。该系统还包括铜间隙填充模块和耦合到至少一个阻挡层沉积模块和ALD铜沉积模块的至少一个传输模块。转移模块被配置为使得基板可以在基本上不暴露于氧化物形成环境的基础之间传递。

6. 发明授权

US08673769B2 Methods and apparatuses for three dimensional integrated circuits 有权
标题翻译：三维集成电路的方法和装置
公开(公告)号：US08673769B2
公开(公告)日：2014-03-18
申请号：US11821051
申请日：2007-06-20
申请人： John Boyd , Fritz Redeker , Yezdi Dordi , Hyungsuk Alexander Yoon , Shijian Li
发明人： John Boyd , Fritz Redeker , Yezdi Dordi , Hyungsuk Alexander Yoon , Shijian Li
IPC分类号： H01L21/4763
CPC分类号： H01L21/44 , H01L21/76898 , H01L23/48 , H01L23/481 , H01L25/50 , H01L2924/0002 , H01L2924/00
摘要： Methods and apparatuses for fabricating three-dimensional integrated circuits having through hole vias are provided. One aspect of the present invention is a method of gapfill for through hole vias for three-dimensional integrated circuits. The method comprises providing a semiconductor wafer having a plurality of holes for through hole vias and depositing a conformal metal layer to partially fill the holes to leave open voids. The method also includes purging the voids and cleaning the surface of the voids and using a dry deposition process to fill or close the voids. Another aspect of the present invention is an electronic device structure for a three-dimensional integrated circuit.
摘要翻译：提供了具有通孔的三维集成电路的制造方法和装置。本发明的一个方面是用于三维集成电路的通孔通孔的间隙填充方法。该方法包括提供具有用于通孔通孔的多个孔的半导体晶片，并且沉积保形金属层以部分填充孔以留下开孔。该方法还包括清除空隙并清洁空隙的表面，并使用干式沉积工艺填充或封闭空隙。本发明的另一方面是一种用于三维集成电路的电子设备结构。

7. 发明授权

US08053355B2 Methods and systems for low interfacial oxide contact between barrier and copper metallization 有权
标题翻译：屏障和铜金属化之间的低界面氧化物接触的方法和系统
公开(公告)号：US08053355B2
公开(公告)日：2011-11-08
申请号：US12828082
申请日：2010-06-30
申请人： Fritz Redeker , John Boyd , Yezdi Dordi , Hyungsuk Alexander Yoon , Shijian Li
发明人： Fritz Redeker , John Boyd , Yezdi Dordi , Hyungsuk Alexander Yoon , Shijian Li
IPC分类号： H01L21/4763
CPC分类号： C25D7/123 , C23C18/1653 , C23C28/023 , C23C28/322 , C23C28/34 , C23C28/341 , H01L21/28562 , H01L21/76843 , H01L21/76849 , H01L21/76856 , H01L21/76862 , H01L21/76873 , H01L21/76874 , H01L23/53238 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to methods and systems for the metallization of semiconductor devices. One aspect of the present invention is a method of depositing a copper layer onto a barrier layer so as to produce a substantially oxygen free interface therebetween. In one embodiment, the method includes providing a substantially oxide free surface of the barrier layer. The method also includes depositing an amount of atomic layer deposition (ALD) copper on the oxide free surface of the barrier layer effective to prevent oxidation of the barrier layer. The method further includes depositing a gapfill copper layer over the ALD copper. Another aspect of the present invention is a system for depositing a copper layer onto barrier layer so as to produce a substantially oxygen-free interface therebetween. In one embodiment, the integrated system includes at least one barrier deposition module. The system also includes an ALD copper deposition module configured to deposit copper by atomic layer deposition. The system further includes a copper gapfill module and at least one transfer module coupled to the at least one barrier deposition module and to the ALD copper deposition module. The transfer module is configured so that the substrate can be transferred between the modules substantially without exposure to an oxide-forming environment.
摘要翻译：本发明涉及用于半导体器件金属化的方法和系统。本发明的一个方面是将铜层沉积在阻挡层上以在其间产生基本上无氧的界面的方法。在一个实施例中，该方法包括提供阻挡层的基本上无氧化物的表面。该方法还包括在阻挡层的无氧化物表面上沉积一定量的原子层沉积（ALD）铜，以有效地防止阻挡层的氧化。该方法还包括在ALD铜上沉积间隙填充铜层。本发明的另一方面是一种用于在阻挡层上沉积铜层以在其间产生基本上无氧的界面的系统。在一个实施例中，集成系统包括至少一个阻挡层沉积模块。该系统还包括配置为通过原子层沉积沉积铜的ALD铜沉积模块。该系统还包括铜间隙填充模块和耦合到至少一个阻挡层沉积模块和ALD铜沉积模块的至少一个传输模块。转移模块被配置为使得基板可以在基本上不暴露于氧化物形成环境的基础之间传递。

8. 发明申请

US20100044867A1 METHODS OF POST-CONTACT BACK END OF LINE THROUGH-HOLE VIA INTEGRATION 有权
标题翻译：通过一体化的线接触后端的方法
公开(公告)号：US20100044867A1
公开(公告)日：2010-02-25
申请号：US12613518
申请日：2009-11-05
申请人： John Boyd , Fritz Redeker , Yezdi Dordi , Hyungsuk Alexander Yoon , Shijian Li
发明人： John Boyd , Fritz Redeker , Yezdi Dordi , Hyungsuk Alexander Yoon , Shijian Li
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L23/48 , H01L21/4763 , H01L21/76898 , H01L2924/14
摘要： Presented are methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. Another aspect of the present invention includes three-dimensional integrated circuits fabricated according to methods of the present invention.
摘要翻译：提出了制造三维集成电路的方法，其包括用于三维集成电路的集成的线路通孔的后接触后端。本发明的另一方面包括根据本发明的方法制造的三维集成电路。

9. 发明授权

US08519461B2 Device with post-contact back end of line through-hole via integration 有权
标题翻译：具有后触点后端的器件通过集成的通孔通孔
公开(公告)号：US08519461B2
公开(公告)日：2013-08-27
申请号：US13455453
申请日：2012-04-25
申请人： John Boyd , Fritz Redeker , Yezdi Dordi , Hyungsuk Alexander Yoon , Shijian Li
发明人： John Boyd , Fritz Redeker , Yezdi Dordi , Hyungsuk Alexander Yoon , Shijian Li
IPC分类号： H01L21/02
CPC分类号： H01L23/48 , H01L21/4763 , H01L21/76898 , H01L2924/14
摘要： Presented are device structures and methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. Another aspect of the present invention includes three-dimensional integrated circuits fabricated according to methods of the present invention.
摘要翻译：提出了三维集成电路的器件结构和方法，该三维集成电路包括用于三维集成电路的集成的线通孔的后接后端。本发明的另一方面包括根据本发明的方法制造的三维集成电路。

10. 发明申请

US20100267229A1 METHODS AND SYSTEMS FOR LOW INTERFACIAL OXIDE CONTACT BETWEEN BARRIER AND COPPER METALLIZATION 有权
标题翻译：阻挡层和铜金属之间的低界面氧化物接触的方法和系统
公开(公告)号：US20100267229A1
公开(公告)日：2010-10-21
申请号：US12828082
申请日：2010-06-30
申请人： Fritz Redeker , John Boyd , Yezdi Dordi , Hyungsuk Alexander Yoon , Shijian Li
发明人： Fritz Redeker , John Boyd , Yezdi Dordi , Hyungsuk Alexander Yoon , Shijian Li
IPC分类号： H01L21/768
CPC分类号： C25D7/123 , C23C18/1653 , C23C28/023 , C23C28/322 , C23C28/34 , C23C28/341 , H01L21/28562 , H01L21/76843 , H01L21/76849 , H01L21/76856 , H01L21/76862 , H01L21/76873 , H01L21/76874 , H01L23/53238 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to methods and systems for the metallization of semiconductor devices. One aspect of the present invention is a method of depositing a copper layer onto a barrier layer so as to produce a substantially oxygen free interface therebetween. In one embodiment, the method includes providing a substantially oxide free surface of the barrier layer. The method also includes depositing an amount of atomic layer deposition (ALD) copper on the oxide free surface of the barrier layer effective to prevent oxidation of the barrier layer. The method further includes depositing a gapfill copper layer over the ALD copper. Another aspect of the present invention is a system for depositing a copper layer onto barrier layer so as to produce a substantially oxygen-free interface therebetween. In one embodiment, the integrated system includes at least one barrier deposition module. The system also includes an ALD copper deposition module configured to deposit copper by atomic layer deposition. The system further includes a copper gapfill module and at least one transfer module coupled to the at least one barrier deposition module and to the ALD copper deposition module. The transfer module is configured so that the substrate can be transferred between the modules substantially without exposure to an oxide-forming environment.
摘要翻译：本发明涉及用于半导体器件金属化的方法和系统。本发明的一个方面是将铜层沉积在阻挡层上以在其间产生基本上无氧的界面的方法。在一个实施例中，该方法包括提供阻挡层的基本上无氧化物的表面。该方法还包括在阻挡层的无氧化物表面上沉积一定量的原子层沉积（ALD）铜，以有效地防止阻挡层的氧化。该方法还包括在ALD铜上沉积间隙填充铜层。本发明的另一方面是一种用于在阻挡层上沉积铜层以在其间产生基本上无氧的界面的系统。在一个实施例中，集成系统包括至少一个阻挡层沉积模块。该系统还包括配置为通过原子层沉积沉积铜的ALD铜沉积模块。该系统还包括铜间隙填充模块和耦合到至少一个阻挡层沉积模块和ALD铜沉积模块的至少一个传输模块。转移模块被配置为使得基板可以在基本上不暴露于氧化物形成环境的基础之间传递。

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